CN100499045C - Integrated technology process for forming silicon germanium source-drain structure - Google Patents
Integrated technology process for forming silicon germanium source-drain structure Download PDFInfo
- Publication number
- CN100499045C CN100499045C CN 200510029704 CN200510029704A CN100499045C CN 100499045 C CN100499045 C CN 100499045C CN 200510029704 CN200510029704 CN 200510029704 CN 200510029704 A CN200510029704 A CN 200510029704A CN 100499045 C CN100499045 C CN 100499045C
- Authority
- CN
- China
- Prior art keywords
- lateral wall
- hard mask
- wall partitioning
- drain structure
- silicon germanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention is concerned with the integration method to form the embedding silicon germanium source-drain structure, it is: uses the polycrystalline silicon mask and the polycrystalline silicon interlayer as mask to process the silicon hollow erode and the silicon germanium extension, simultaneity removes the polycrystalline silicon mask and the polycrystalline silicon interlayer after achieves the silicon germanium extension of the source / leaking area, processes light doping drain (LDD) to form ONO sidewall interlayer, the heavy doping of the source-drain area, the formation of the self-aiming silicide, and the following working procedure.
Description
Technical field
The present invention relates to the manufacture method of PMOS, particularly relate to the integrated technology process of the PMOS that forms silicon germanium source-drain structure.
Background technology
At source and drain areas selective epitaxial growth SiGe is the very promising strain engineering technology that is used to improve P channel transistor (PMOS) performance.Normally after the polysilicon gate wall forms,, remove the hard mask on the polysilicon gate then in source and drain areas cave in etching and SiGe epitaxial growth.Yet because the heat treatment in the wall forming process strengthens the corrosion stability of the hard mask of polysilicon, etch rate is very low, therefore is not easy to remove the hard mask of polysilicon under the condition of not destroying wall.Because remove the etching that hard mask layer carries out, wall is corroded, cause problems such as device short circuit, have a strong impact on device performance.
Summary of the invention
The objective of the invention is to propose a kind of new process, this method adopts carries out the depression etching of silicon and the epitaxial growth of SiGe at source and drain areas earlier, and then forms ONO type wall.Therefore, this method can successfully be integrated in silicon germanium source-drain structure among the PMOS, and has avoided the destruction to wall.
The integrated technique flow process of formation silicon germanium source-drain structure of the present invention comprises the steps:
A) on silicon substrate, carry out shallow isolating trough, on silicon substrate, form the N/P well, grid oxic horizon, the polysilicon deposit forms hard mask deposition layer, the polysilicon photoetching, etching polysilicon is removed photoresist, and gate re-ox forms the polysilicon gate conductive structure;
B) the lateral wall partitioning layer material is sacrificed in the grid curb wall deposit, sacrifices lateral wall partitioning layer etching, and wet-cleaned forms autoregistration and sacrifices the lateral wall partitioning layer;
C) be mask protection polysilicon gate with hard mask and sacrifice lateral wall partitioning layer, carry out silicon substrate depression etching at source and drain areas;
D) at the regional epitaxial growth SiGe of etching that caves in;
E) remove hard mask and sacrifice lateral wall partitioning layer;
F) P type LDD mixes and injects;
G) deposit material spacer layer, the wall etching, wet-cleaned forms the lateral wall partitioning layer;
H) P type heavy doping forms metal silicide, contact hole, and other successive process.
According to the present invention, the material that forms hard mask is silicon oxynitride (SiON) or silicon oxynitride (SiON) and tetraethoxysilane (TEOS).
According to the present invention, the hard mask of sacrificing on lateral wall partitioning layer and the polysilicon gate constitutes mask jointly, and the protection polysilicon gate is removed simultaneously with hard mask then when being used to carry out silicon dent etching and SiGe epitaxial growth.After forming polysilicon gate, the epitaxial growth of source-drain area SiGe, form final ONO lateral wall partitioning layer again.Wherein sacrificing the lateral wall partitioning layer material is tetraethoxysilane (TEOS) or silicon nitride (SiN), or tetraethoxy silication thing (TEOS) and silicon nitride (SiN), forms with self aligned method deposit.
Hydrofluoric acid and phosphoric acid (HF+H are adopted in the removal of hard mask of the present invention and sacrifice lateral wall partitioning layer
3PO
4).
According to the present invention, the protection grid is the combination of hard mask used during by polysilicon gate photoetching and etching and the sacrifice lateral wall partitioning layer that formed by autoregistration when source-drain area carries out the epitaxial growth of the depression etching of silicon and SiGe.This combination by hard mask and autoregistration sacrifice lateral wall partitioning layer is removed after the epitaxial growth of the depression etching of finishing silicon and SiGe fully.By hydrofluoric acid and phosphoric acid (HF+H
3PO
4) removal of mixing etching.Then after finishing lightly doped drain, form new source, the interval/leakage formed by silica, silicon nitride and silica and the lateral wall partitioning layer of grid again.
Can effectively remove hard mask by method of the present invention, and formed ONO type wall can not be affected after removing hard mask, can guarantee the quality of successive process.
Description of drawings
Fig. 1 is that polysilicon gate forms later schematic cross-section.
Fig. 2 is the schematic cross-section after the deposit of lateral wall partitioning layer.
Fig. 3 is at self-aligned spacers wall that forms and the hard mask protection of polysilicon polysilicon gate, carries out the schematic cross-section after the silicon dent etching.
Fig. 4 is the schematic cross-section after the SiGe epitaxial growth is leaked in the source of silicon dent etching.
Fig. 5 is the schematic cross-section behind hard mask of removal and the lateral wall partitioning layer.
Fig. 6 is the schematic cross-section behind the P type light dope.
Fig. 7 is the schematic cross-section behind the formation ONO wall.
Description of reference numerals
1 silicon substrate, 2 N wells
3 gate oxide level, 4 polysilicon gates
7 sacrifice lateral wall partitioning layer 8 silicon dent
9 SiGe epitaxial growths, 10 P type light dopes
11 ONO walls
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing.
Form the integrated technology process of the PMOS of silicon germanium source-drain structure, comprise the steps:
A) at first on silicon substrate 1, form shallow isolating trough 6, on silicon substrate 1, form N well 2, form grid oxic horizon 3, the polysilicon layer deposit, the hard mask layer deposit, carry out the formation of polysilicon photoengraving pattern then, etching is removed photoresist, form polysilicon gate 4 conductive structures, hard mask 5, gate re-ox, as shown in Figure 1.Wherein hard mask material adopts silicon oxynitride and tetraethoxysilane, is to form by the plasma-reinforced chemical vapor deposition method.
B) polysilicon gate 4 side wall deposit material spacer layers 7, as shown in Figure 2, wherein material spacer layer is tetraethoxysilane, silicon nitride or tetraethoxysilane and silicon nitride.
C) the lateral wall partitioning layer material carries out etching, and wet-cleaned forms inter polysilicon interlayer 7; sacrifice lateral wall partitioning layer 7 with hard mask 5 of polysilicon and polysilicon gate is a mask protection polysilicon gate 4 then; source and drain areas is carried out the silicon dent etching, form silicon dent zone 8, as shown in Figure 3.
D) the sacrifice lateral wall partitioning layer 7 with hard mask 5 of polysilicon and polysilicon gate is a mask protection polysilicon gate 4, carries out the SiGe epitaxial growth on the silicon dent zone 8, forms strained source drain electrode 9, as shown in Figure 4.
E) the sacrifice lateral wall partitioning layer 7 of removal hard mask 5 of polysilicon and polysilicon gate adopts the mixing of hydrofluoric acid and phosphoric acid to carry out the wet etching removal, as shown in Figure 5.As can be seen from Table 1, the mixing of hydrofluoric acid and phosphoric acid is applied to the hard mask 5 of polysilicon that formed by silicon oxynitride and tetraethoxysilane (SiON+TEOS) by the plasma-reinforced chemical vapor deposition method and the sacrifice lateral wall partitioning layer 7 of the polysilicon gate that formed by tetraethoxysilane (TEOS), silicon nitride (SiN) or tetraethoxysilane and silicon nitride (TEOS+SiN), can come successfully they to be removed fully by the etch period of adjusting hydrofluoric acid and phosphoric acid, as the HF of elder generation, and then add 30 minutes H with 5 seconds
3PO
4
The contrast of table 1 different materials etch rate
| Etch rate | HF(A/sec) | H 3PO 4(A/sec) |
| SiON (before the tempering) | 4.64 | 90.08 |
| SiON (after the tempering in 10 hours) | 0.7(600A) 1.67(270A) | 8.1(600A) 5.53(270A) |
| TEOS | 15.13 | 8.16 |
| Plasma-reinforced chemical vapor deposition silica (after the |
10.47 | —— |
| Si
3N
4(after the |
0.23 | 72.42 |
F) the epitaxially grown source-drain electrode of SiGe is carried out P type ion light dope and inject (PLDD), as shown in Figure 6.
G) deposit tetraethoxysilane (TEOS), deposit silicon nitride (SiN), deposit tetraethoxysilane carry out the wall etching then, carry out wet-cleaned again, form ONO type wall, as shown in Figure 7.
H) P type heavy doping then forms metal silicide on grid and the source-drain electrode, and forms contact hole on the source-drain electrode, and other successive process.
According to the present invention, the material that forms hard mask is silicon oxynitride (SiON) and tetraethoxysilane (TEOS), sacrifice property lateral wall partitioning layer material is tetraethoxysilane (TEOS), or silicon nitride (SiN), or tetraethoxysilane (TEOS) and silicon nitride (SiN).Because hydrofluoric acid and phosphoric acid (HF+H3PO4) are adopted in the removal of hard mask and sacrifice property lateral wall partitioning layer, after forming SiGe ground source-drain structure, by adjusting the etch period of hydrofluoric acid and phosphoric acid, remove hard mask and sacrifice property lateral wall partitioning layer simultaneously, and then form ONO type wall.Therefore, the present invention adopts the source-drain structure that forms earlier SiGe, forms the wall of ONO type again, thereby very easily destroys the problem of ONO wall when having avoided removing polysilicon gate in the common integrated technique flow process.
Claims (11)
1. form the integrated technology process of silicon germanium source-drain structure, comprise the steps:
A) carry out shallow isolating trough on silicon substrate, form the N well, form grid oxic horizon, the polysilicon deposit forms polysilicon gate, and the polysilicon deposit forms hard mask deposition layer; Photoresist is removed in the polysilicon photoetching, forms polysilicon gate conductive structure and hard mask, gate re-ox;
B) at polysilicon gate side wall deposit material spacer layer, sacrifice lateral wall partitioning layer etching, wet-cleaned forms autoregistration and sacrifices the lateral wall partitioning layer;
C) be mask with hard mask of polysilicon and sacrifice lateral wall partitioning layer, carry out silicon substrate depression etching;
D) at the regional epitaxial growth SiGe of etching that caves in;
E) remove hard mask and sacrifice lateral wall partitioning layer;
F) epitaxially grown SiGe being carried out P type LDD doping injects;
G) deposit material spacer layer, the wall etching, wet-cleaned forms the lateral wall partitioning layer;
H) on grid and source-drain electrode, carry out the heavy doping of P type, form metal silicide and contact hole, and carry out other subsequent techniques.
2. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1; it is characterized in that; the hard mask that described autoregistration is sacrificed on lateral wall partitioning layer and the polysilicon gate constitutes mask jointly; the protection polysilicon gate is removed simultaneously with hard mask then when being used to carry out silicon dent etching and SiGe epitaxial growth.
3. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, the sacrifice lateral wall partitioning layer material of described protection polysilicon gate is a Si oxide.
4. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, the sacrifice lateral wall partitioning layer material of described protection polysilicon gate is silicon nitride (SiN).
5. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, the sacrifice lateral wall partitioning layer material of described protection polysilicon gate is tetraethoxysilane (TEOS) and silicon nitride (SiN).
6. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, the sacrifice lateral wall partitioning layer of described protection polysilicon gate adopts self aligned method to form.
7. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, hard mask deposition layer is a silicon oxynitride.
8. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, hard mask deposition layer is silicon oxynitride and tetraethoxysilane.
9. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1 is characterized in that, adopts hydrofluoric acid and phosphoric acid (HF+H
3PO
4) remove described hard mask and sacrifice the lateral wall partitioning layer.
10. the integrated technique flow process of formation silicon germanium source-drain structure according to claim 1, it is characterized in that described lateral wall partitioning layer material is tetraethoxysilane (TEOS) or silicon nitride (SiN) or tetraethoxy silication thing (TEOS) and silicon nitride (SiN).
11. Si oxide according to claim 3 is tetraethoxysilane (TEOS).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029704 CN100499045C (en) | 2005-09-15 | 2005-09-15 | Integrated technology process for forming silicon germanium source-drain structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029704 CN100499045C (en) | 2005-09-15 | 2005-09-15 | Integrated technology process for forming silicon germanium source-drain structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1933113A CN1933113A (en) | 2007-03-21 |
| CN100499045C true CN100499045C (en) | 2009-06-10 |
Family
ID=37878860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510029704 Expired - Fee Related CN100499045C (en) | 2005-09-15 | 2005-09-15 | Integrated technology process for forming silicon germanium source-drain structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100499045C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459132B (en) * | 2007-12-10 | 2010-11-03 | 上海华虹Nec电子有限公司 | Manufacturing process for high voltage planar power MOS device |
| CN102117828B (en) | 2009-12-30 | 2013-02-06 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US9093298B2 (en) * | 2013-08-22 | 2015-07-28 | Texas Instruments Incorporated | Silicide formation due to improved SiGe faceting |
| CN105336703B (en) * | 2014-08-07 | 2018-09-04 | 无锡华润上华科技有限公司 | A kind of production method of semiconductor devices |
-
2005
- 2005-09-15 CN CN 200510029704 patent/CN100499045C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1933113A (en) | 2007-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8283226B2 (en) | Method for manufacturing semiconductor device | |
| US5438009A (en) | Method of fabrication of MOSFET device with buried bit line | |
| DE102012101875B4 (en) | A method of manufacturing a high gate density semiconductor device | |
| US8912068B2 (en) | Semiconductor device with strained channel and method of fabricating the same | |
| US8058120B2 (en) | Integration scheme for strained source/drain CMOS using oxide hard mask | |
| CN109585550B (en) | Semiconductor structure and semiconductor manufacturing method | |
| KR100539265B1 (en) | Fabricating method of MOSFET having recessed channel | |
| KR100508756B1 (en) | Method for manufacturing a MOS transistor in semiconductor device | |
| CN102097381A (en) | CMOS (Complementary Metal-Oxide-Semiconductor) transistor and stress memory treatment method thereof | |
| CN100499045C (en) | Integrated technology process for forming silicon germanium source-drain structure | |
| KR101663829B1 (en) | Semiconductor device and method of manufacturing the same | |
| CN101202232B (en) | Method for forming semiconductor device and semiconductor device | |
| US20090057775A1 (en) | Semiconductor Device and Method for Manufacturing Semiconductor Device | |
| US20050026342A1 (en) | Semiconductor device having improved short channel effects, and method of forming thereof | |
| CN100514579C (en) | Production of strain silicon transistor | |
| US8642435B2 (en) | Performing treatment on stressors | |
| CN100499044C (en) | Strain source-drain producing method utilizing new hard mask | |
| US6987049B2 (en) | Semiconductor transistors and methods of fabricating the same | |
| US7629254B2 (en) | Semiconductor device | |
| KR100525912B1 (en) | Method of manufacturing a semiconductor device | |
| KR100412194B1 (en) | Method of manufacturing a semiconductor device | |
| KR100672171B1 (en) | Method for fabricating semiconductor device | |
| KR20060099826A (en) | Method for fabricating semiconductor device | |
| KR100429229B1 (en) | Method for Fabricating of Semiconductor Device | |
| US20070114619A1 (en) | Sidewall mosfets with embedded strained source/drain |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111123 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111123 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090610 Termination date: 20180915 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |