CN100495314C - Computer display matrix output device - Google Patents
Computer display matrix output device Download PDFInfo
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- CN100495314C CN100495314C CNB2006100623915A CN200610062391A CN100495314C CN 100495314 C CN100495314 C CN 100495314C CN B2006100623915 A CNB2006100623915 A CN B2006100623915A CN 200610062391 A CN200610062391 A CN 200610062391A CN 100495314 C CN100495314 C CN 100495314C
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- display
- display controller
- enable register
- matrix output
- pci
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- 239000011159 matrix material Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 claims description 12
- 230000003139 buffering effect Effects 0.000 claims description 10
- 238000011423 initialization method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Abstract
The apparatus comprises: at least one display matrix output unit. Each display matrix output unit comprises a PCE bride-connection chip, two display controller respectively connected to the PCI bridge-connection chip and an enable register selecting circuit. Said enable register selecting circuit is used for respectively selecting different I/O addresses for said two display controllers; the PCI bridge-connection is connected to the PCI bus of the computer; each display controller is connected to a display. The invention also reveals a powering initialization method used for one-by-one enabling and initializing each display controller. By the invention, multi display controllers can work on one PCI bus.
Description
[technical field]
The present invention relates to a kind of computing machine and show output unit, relate in particular to a kind of computer display matrix output device.
[background technology]
Computing machine has been widely used in various video output controls, as traffic monitoring, securities data shows and large-scale CAM/CAD design etc., need use the output form of a plurality of displays or video wall, these are used all to require to calculate to export and are not only one, but 2 power power is individual.In order to realize this requirement, generally can adopt multidisplay system's machine or with two kinds of working methods of multi-display card.Wherein the display terminal function is stronger, but price is higher, and multi-display card (external display) mode is general relatively more cheap under the situation of said function, so be subjected to user's welcome.
The computing machine of current popular all has only a VGA (Video Graphics Array) output with the display card general structure, also occur some now on the market and supported the display card of two or three VGA outputs, but it is high that price is wanted comparatively speaking, and because operating system can only be supported two display cards at most, thereby can't satisfy above-mentioned 2 the power power display or the output form of video wall, computing machine is restricted in the application in these fields.
[summary of the invention]
Technical matters to be solved by this invention is to provide a kind of computer display matrix output device, described display matrix output device can solve in the computer system can only the problem of two display cards, thereby has realized that a computer system has a plurality of outputs.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of computer display matrix output device is provided, described computing machine comprises pci bus and display device, it is characterized in that: described computer display matrix output device comprises at least one display matrix output unit, described display matrix output unit comprises a PCI bridging chip, be connected to one first display controller and one second display controller of described PCI bridging chip, and one the enable register that is connected in described first display controller select circuit, one second enable register that is connected in described second display controller is selected circuit, described first enable register selects circuit and described second enable register to select circuit to be respectively described first display controller and described second display controller is selected different I/O address, described PCI bridging chip is connected in described pci bus, described first display controller and described second display controller connect a display device respectively, and the default power-up initializing method of employing, enable one by one and described first display controller of initialization and second display controller, and described first display controller and second display controller are changed to frame buffering display mode.
The default power-up initializing method of described computer display matrix output device may further comprise the steps:
A) all the PCI bridges in the pci bus of described computing machine being made as VGA forbids;
B) described PCI bridging chip being set is that VGA enables;
C) selecting the enable register I/O address of circuit selection that described first display controller is set according to described first enable register is enabled state;
D) described first display controller of initialization, and described first display controller is changed to frame buffering display mode;
E) described first display controller is changed to illegal state;
F) selecting the enable register I/O address of circuit selection that described second display controller is set according to described second enable register is enabled state;
G) described second display controller of initialization, and described second display controller is changed to frame buffering display mode;
H) described second display controller being set is enabled state;
I) described PCI bridging chip being set is that VGA forbids.
Compared with prior art, the present invention has following beneficial effect: selecting circuit by different enable register is that display controller is selected different enable register I/O address, power-up initializing method by appointment again, enable each display controller one by one, and it is carried out initialization, display controller is changed to frame buffering display mode, thereby avoid the I/O address conflict between a plurality of display controllers, a plurality of display controller co-operation on a pci bus have been realized, control a plurality of display device, and then realize the display matrix output of a computer system.
[description of drawings]
The present invention is described in further detail below in conjunction with drawings and embodiments:
Fig. 1 is the functional-block diagram of computer display matrix output device of the present invention.
Fig. 2 is the power-up initializing method flow diagram of computer display matrix output device of the present invention.
[embodiment]
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
As shown in Figure 1, be one embodiment of the present invention.
Computer display matrix output device of the present invention, it comprises a display matrix output unit, described display matrix output unit comprises PCI bridging chip, display controller A, display controller B, enable register selection circuit A and enable register selection circuit B.Described PCI bridging chip is connected with the pci bus of computing machine, described display controller A is connected with the PCI bridging chip by pci bus, described display controller B is connected with the PCI bridging chip by pci bus, described enable register selects circuit A to be connected with display controller A, and described enable register selects circuit B to be connected with display controller B.The external display device of display controller A (figure does not show), as the VGA display, the external display device of while display controller B (figure does not show) is as the VGA display.
It is that described display controller A selects the enable register I/O address that wherein said enable register is selected circuit A, and it is that described display controller B selects the enable register I/O address that described enable register is selected circuit B.Because enable register is selected circuit A to be different from enable register and selected circuit B, thereby enable register selects the selected I/O address of circuit A to be different from the selected I/O address of enable register selection circuit B.Thereby avoided the address conflict between a plurality of display controllers.
In order to expand the demonstration output of computer system, described computer display matrix output device can comprise a plurality of display matrix output units that are parallel to pci bus, by the described computer display matrix output device of power-up initializing method initialization of appointment, realize a plurality of described display matrix output units and deposit.Because a display controller connects a display device, there is one to show output, thereby a described display matrix output unit can have two to show output, be appreciated that, when a plurality of display matrix output units are parallel to pci bus, can realize that 2 power power of a computer system shows output.
See also Fig. 2, when described a plurality of display matrix output unit is parallel on the pci bus, for guaranteeing the display matrix output unit operate as normal of the computer display matrix output device that each is in parallel, need to carry out initialization by the power-up initializing method of appointment, the step of the power-up initializing method of described appointment is:
A) all the PCI bridges in the pci bus of described computing machine being made as VGA forbids;
B) described PCI bridging chip being set is that VGA enables;
C) selecting the enable register I/O address of circuit A that described display controller A is set according to described enable register is enabled state;
D) the described display controller A of initialization, and display controller A is changed to frame buffering display mode;
E) more described display controller A is changed to illegal state;
F) selecting the enable register I/O address of circuit B that described display controller B is set according to described enable register is enabled state;
G) the described display controller B of initialization, and display controller B is changed to frame buffering display mode;
H) described display controller A being set is enabled state;
I) described PCI bridging chip being set is that VGA forbids.
Selecting circuit by different enable register is that display controller is selected different enable register I/O address, power-up initializing method by appointment again, enable each display controller one by one, and it is carried out initialization, display controller is changed to frame buffering display mode, thereby avoid the I/O address conflict between a plurality of display controllers, realized a plurality of display controller co-operation on the pci bus.
Be appreciated that, described computing machine shows when output unit comprises a plurality of display matrix output unit that is connected in parallel on pci bus, power-up initializing method by described appointment is carried out initialization one by one to each display matrix output unit of parallel connection, can realize that a computer system has a power power demonstration output of 2, thereby realize the matrix output of a computer system.
Claims (2)
1, a kind of computer display matrix output device, described computing machine comprises pci bus and display device, it is characterized in that: described computer display matrix output device comprises at least one display matrix output unit, described display matrix output unit comprises a PCI bridging chip, be connected to one first display controller and one second display controller of described PCI bridging chip, and one the enable register that is connected in described first display controller select circuit, one second enable register that is connected in described second display controller is selected circuit, described first enable register selects circuit and described second enable register to select circuit to be respectively described first display controller and described second display controller is selected different I/O address, described PCI bridging chip is connected in described pci bus, described first display controller and described second display controller connect a display device respectively, and the default power-up initializing method of employing, enable one by one and described first display controller of initialization and second display controller, and described first display controller and second display controller are changed to frame buffering display mode.
2, computer display matrix output device as claimed in claim 1 is characterized in that the default power-up initializing method of described computer display matrix output device may further comprise the steps:
A) all the PCI bridges in the pci bus of described computing machine being made as VGA forbids;
B) described PCI bridging chip being set is that VGA enables;
C) selecting the enable register I/O address of circuit selection that described first display controller is set according to described first enable register is enabled state;
D) described first display controller of initialization, and described first display controller is changed to frame buffering display mode;
E) described first display controller is changed to illegal state;
F) selecting the enable register I/O address of circuit selection that described second display controller is set according to described second enable register is enabled state;
G) described second display controller of initialization, and described second display controller is changed to frame buffering display mode;
H) described second display controller being set is enabled state;
I) described PCI bridging chip being set is that VGA forbids.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100623915A CN100495314C (en) | 2006-08-30 | 2006-08-30 | Computer display matrix output device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100623915A CN100495314C (en) | 2006-08-30 | 2006-08-30 | Computer display matrix output device |
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| Publication Number | Publication Date |
|---|---|
| CN101135961A CN101135961A (en) | 2008-03-05 |
| CN100495314C true CN100495314C (en) | 2009-06-03 |
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| CNB2006100623915A Active CN100495314C (en) | 2006-08-30 | 2006-08-30 | Computer display matrix output device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103105895A (en) * | 2011-11-15 | 2013-05-15 | 辉达公司 | Computer system and display cards thereof and method for processing graphs of computer system |
| CN109933434B (en) * | 2018-04-12 | 2021-06-18 | 威盛电子股份有限公司 | Electronic device and method for expanding peripheral equipment |
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Owner name: YANXIANG INTELLIGENT TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SHENGZHEN EVOC INTELLIGENT TECHNOLOGY CO., LTD. Effective date: 20091225 |
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