CN100492042C

CN100492042C - Device and method for creating a characteristic sign

Info

Publication number: CN100492042C
Application number: CNB2003801068603A
Authority: CN
Inventors: W·哈特; R·安格尔鲍尔; E·贝尔
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2002-12-20
Filing date: 2003-12-18
Publication date: 2009-05-27
Anticipated expiration: 2023-12-18
Also published as: DE10351442A1; CN1729402A; DE10351442A9

Abstract

A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cycle, a signature being formed in the shift registers after a certain number of data words and cycles, a code generator which generates at least one additional bit position in at least one additional shift register from each data word in the signature also being provided.

Description

The apparatus and method of construction feature symbol

Technical field

The present invention relates to the apparatus and method of construction feature symbol.

Background technology

Be the construction feature symbol, use MISR circuit (many input feature vectors of MISR=sign register), as for example by Paul H.Bardell Willam, H.McAnny and Jacob Savir are published in VLSI built-in test publication: the pseudorandom technology, 124 pages the above is such. in the text, be provided with the shift register of predetermined quantity, need the data of test to be abuttingly reposed against in order on these registers. at this, the data of the parallel arranged that has been coupled, and be shifted with a predetermined time clock by shift register. then, in shift register, after the data word and time clock of certain accurately quantification, just there is one can compare and verifiable characteristic symbol value with precognition characteristic symbol value. for test a process and relevant data in this process error freely, the characteristic symbol value received and desired characteristic symbol value is relatively just much of that. at this, the characteristic symbol value that also can obtain predicting by this way.

When at moment T, when certain input end has an error, be problematic, because at first the value of a mistake is write relevant shift register according to the method and apparatus of prior art.Therefore, the final characteristic symbol that is calculated is different with desired characteristic symbol. still, if except that next T+1 constantly, below, particularly an error appears in input end follow on the heels of, if not having MISR during this period is the anti-coupling shunt that characteristic symbol produces circuit, then in first input end error originally, by shift register with time clock corresponding to the interval of input end and some constantly, particularly to be compensated again after the displacement of time clock. like this, do not discovered during at the construction feature symbol in the error that occurs on the moment of so ging wrong and the data word position.

For addressing this problem, might when depositing in, consider, after data word, deposit opposite data word in being right after, so that compensating error in no instance, but discover error. still, this but makes the necessary computing and the quantity of time clock double.

Like this, just show that prior art is not can both provide optimum aspect each, and proposing thus of task is can research and develop a kind of improved apparatus and method for addressing the above problem in the construction feature symbolic range.

Summary of the invention

Starting point of the present invention is the apparatus and method of construction feature symbol, wherein be provided with the shift register of predetermined quantity, the input data of required detection with bit-wise as data word connected to one another and link on these registers, and will import data shift serially with the time clock that can be scheduled to, and after the data word of some and time clock, in shift register, make up a characteristic symbol, wherein add in a preferred manner a code generator is set, this code generator is created at least one the additional bit at least one additional shift register from each data word characteristic symbol. also promptly with at least one bit of optimal way expansion MISR, wherein this bit obtains from the complete data word of respectively adjoining respectively, and be input in the characteristic symbol together. thus, can guarantee in a preferred manner to address the above problem, need not repeatedly additional operations and time clock when characteristic symbol makes up.

Stop error concealment occurring under the situation of described multiple error expending by this way with seldom circuit.

In addition, advantage is by the XOR point, also is that xor logic connects each shift register is connected, and also can make each bit coupling by this XOR point.

Equally, on purpose replace XOR to connect, also be an XOR point, and use an equivalent point, also promptly the XOR that negates can imagine, so that with each bit of data word, on the other hand at least one bit in the code generator is coupled in the corresponding shift register on the one hand.

So constitute code generator in an advantageous manner, be that this code generator is realized ECC (error-tested and error correction), such as Hamming code, Berger sign indicating number (Berger codes) or Bose-Lin sign indicating number (Bose-Lin sign indicating number) or the like, so that the additional shift register that is used for the construction feature symbol of giving respective numbers with the bit of the corresponding quantity of each ECC sign indicating number. under the most general situation, can use a kind of code generator table (hardware realize or in software), so that distribute the expected code type of a random length for certain input code type of data word or bit. under the simplest situation, so constitute code generator in an advantageous manner, promptly this code generator makes up a parity check bit and this parity check bit is stipulated to an additional shift register.

Other advantage and favourable scheme are provided by instructions.

Description of drawings

Fig. 1 show have shift register 100 to 105 with XOR, also be the MISR circuit that xor logic is connected 106-111.

Fig. 2 shows same MISR circuit and has shift register 100-105 and XOR equally, also is that xor logic is connected 106-111.

Fig. 3 shows three data word DW1, DW2 and DW3, and they should be adjoined to input end Input0 to Input n-1. in this order

Fig. 4 shows with an i bit code maker and expands this MISR.

Embodiment

Fig. 1 has provided has shift register 100 to 105 and XOR, also be the MISR circuit that xor logic connects 106-111. at this, corresponding to reverse coupled a kind of mould type of determining is described. at this, input end Input0, Input1, Input2, Input3, Input4 and Input n-1 are coupled in the shift register, these input ends are corresponding to the corresponding bit of adjacent data word, and read in and move with given time clock. then, in shift register, can obtain state X0, X1, X2, X3, X4 and Xn-1, wherein n is the natural number greater than 0, and in this object lesson even minimum be 6.

Fig. 2 shows same MISR circuit and has shift register 100-105 and XOR equally, also be that xor logic connects 106-111. in addition, also add and described 2 xor logics connections 111 and 113, so connecting, these two logics after

shift register

100 and 102, operate in this example. relate to the type of MISR at this, Coupling point wherein, also be that XOR connection 112 and 113 can be selected in MISR arbitrarily as its quantity equally. input end 0 has also been described to n-1 here, and the state X0 to Xn-1 of shift register has been described equally, wherein n ∈ N.

Fig. 3 then shows three data word DW1, DW2 and DW3, the position is represented with BS0 and BSn-1 if they should be adjoined to input end Input0 to Input n-1. individual bit in this order. for example in data word DW1, adjoin an error F definitely now for Input1 at moment T, and moment T+1 equally afterwards also promptly also adjoins an error in Input2 in data word DW2, so like this in MISR with this error of time clock displacement post-compensation. the same error combination that also is applicable to other, this error combination will will cause compensating according to coupling time point and position in data word and corresponding input end.

Now, in Fig. 4, expand this MISR. at this with an i bit code maker, i is same as representing bit number greater than 0 natural number, used sign indicating number or the ECC sign indicating number of these several certificates in code generator is coupled into the bit of MISR. according to the code generator output of this quantity i by code generator, also can be additional to MISR, be provided with respective numbers shift register, mark with 408 at this. at this, the simplest situation is to realize that parity bit makes up, so that an additional shift register and another Input-1. only are set

Introduce at least one additional shift register or Coupling point that at least one is additional on which position in MISR, also be XOR point or equivalent point, can freely select, and here only illustrate. that is to say, conventional shift register 100-105 has here been described again in Fig. 4, the input end Input04 of at least one additional shift register 408. apparatus of the present invention wherein is set, Input14, Input24, Input34, Input44, Input (n-1) the 4 XOR point that here not only leads, also be that xor logic connects, and supply i bit code maker. like this, from the data word that arrives, generate additional information relatively with predetermined time clock with used sign indicating number (a particularly BCC), and shift register with its input respective numbers. in this example, unit 400-406 is set as the xor logic tie point, wherein in described this example except that the input end Input-i and state X-i of shift register 408, also obtain the conventional state X0 of shift register, X1, X2, X3 and Xn-1. have pointed out in other embodiments just in time that as the additional arrow of the output terminal of i bit code maker 407 not only one additional bits writes MISR, and be relevant with used code.

When using Hamming code, for example that is when ECC carries out single error error correction, 4 bit useful datas obtain 3 bit error-correcting codes. when the single error error correction of the ECC with 8 bit useful datas, obtain 4 bit error-correcting codes. when 16 bit useful datas, obtain 5 bit error-correcting codes, and when 32 bit useful datas, obtain 6 bit error-correcting codes. also promptly in general 2 ^k〉=m+k+1, wherein m is as being equivalent to the quantity of useful bit greater than 0 natural number, and if k as natural number equally corresponding to sign indicating number position or error correction bit or error correction code. should add and realize 2 error-detectings, then per 1 bit can be provided with more error correcting codes.

If for example use a kind of Berger sign indicating number, then when 4 bit useful datas, 3 additional sign indicating number positions, 5 kinds of states are set, when 8 bit useful datas, 4 additional sign indicating number positions, 9 kinds of states are set. when 16 bit useful datas, 5 additional sign indicating number positions are set, 17 kinds of states are arranged, and when 32 bit useful datas, 6 additional sign indicating number positions are set there are 33 kinds of states. usually have 2 here ^k〉=m+1 or K 〉=1d (m+1), wherein m is equivalent to the useful bit number of data, and k is equivalent to code bit number or error correcting code.

Also having other sign indicating number also is possible as the Brose-Lin sign indicating number at this, and wherein the quantity of bits of coded is also identical with the Berger sign indicating number at this, but detecting position only is mould 4 or mould 5.

According to this coding figure place k the output terminal of the code generator of this quantity, also promptly additional input end (inputs)-i can be set also thus, i=1 to k ∈ N wherein, and the shift register and the logic tie point of same quantity.

Thus, at least one position of MISR expansion, by from former data input Input0 to Input n-1, obtaining at least one bit parity sign indicating number or other sign indicating number, and together in the input feature vector symbol, for example in Fig. 4, indicate at this at modular type (Fig. 1). certainly, same situation also is applicable to type (Fig. 2). thus, this code generator can be a parity generator, i=1, wherein saying exactly in this case needs an additional trigger. for the situation that an error for example in Input3, occurs, be attached on the Input-1, also be that odd even Input goes up value that has changed of input. for sheltering this value under the situation of error having, then exactly in next time clock, not only an error must arranged also on the Input4 but also on Input0.Also promptly have a higher Hamming at interval here, and when having the error concealment of 2 errors, the precise time characteristic by necessity reduces significantly shelters probability.

As mentioned above, along with more cost on code bit, if then can expand Hamming arbitrarily at interval. replace XOR, use an equivalent logic to connect and be coupled, then no doubt can realize an inappreciable little redundance, but also always little than prior art error concealment probability significantly.

As other possibility. also can obtain a form for code generator 407 and distribute, also promptly use a code generator table, wherein the bit combination with the data word of importing is coupled into the sign indicating number position of predetermined quantity in the shift register of respective numbers relatively. and the bits of coded of the data bit of input being distributed to output arbitrarily by such code generator table is possible.

For from MISR, reading the characteristic symbol of structure, a switchgear S is set under the situation of serial, it can disconnect anti-coupling circuit, and make that reading shift register serially becomes possibility. on the other hand, as with shown in alphabetical P and the dash line like that, also might be the shift register that walks abreast, and the disposable thus characteristic symbol of from MISR, reading, so that the characteristic symbol of these characteristic symbols with corresponding expectation compared.

This shows that the present invention shows the safety coefficient apparently higher than common MISR, and negate on the contrary, show significantly less cost with being used for lasting necessary data word that compensating error shelters.

Thus, the present invention can be used in the high application of all security requirements, particularly control (ABS, ASR, ESP or the like), turns to, disconnects, also promptly usually controls or the like with lead exchange (x-by-wire), air bag, Electric Machine Control, linkage with lead with lead as brake in automotive field. and same, in the microcontroller or other semiconductor structure of the present invention in test specification, and in all BIST structures (built-in self test examination) and also have when optimizing product test and be applied.

Claims

1. the device of construction feature symbol, the shift register of predetermined quantity wherein is set, be furnished with the logic linkage unit between these shift registers, input data to be tested are stored on these registers as continuous data word is parallel with bit-wise, and these shift registers will be imported data further and be shifted serially with the time clock that can be scheduled to, wherein after the data word of some and time clock, in shift register, make up a characteristic symbol, it is characterized in that, an also additional code generator and at least one the additional shift register of being provided with in described device, wherein said data word is imported in this code generator, this code generator produces at least one additional bit from each data word, wherein should be transfused to this additional shift register by additional bit, this additional shift register is connected with the shift register of described predetermined quantity in order and has been constituted input feature vector sign register more than by these shift registers.

2. according to the described device of claim 1, it is characterized in that each shift register connects by XOR point, and each bit of data word is coupled into this XOR point with the construction feature symbol as at least one additional bits of this code generator equally.

3. according to the described device of claim 1, it is characterized in that each shift register connects by XOR point, and each bit of data word is coupled into this XOR point equally at least with the construction feature symbol as an additional bits of this code generator.

4. according to the described device of claim 1, it is characterized in that, this code generator so makes up, cause this code generator to realize a kind of error-tested and error correcting code, and the additional shift register that is used for the construction feature symbol of giving respective numbers with the bit of each error-tested and the corresponding quantity of error correcting code.

5. according to the described device of claim 1, it is characterized in that this code generator so makes up, cause this parity bits of code generator generation and give this parity bits regulation an additional shift register.

6. according to the described device of claim 4, it is characterized in that this code generator so makes up, cause this code generator to realize Hamming code.

7. according to the described device of claim 4, it is characterized in that this code generator so makes up, cause this code generator to realize Berger codes.

8. according to the described device of claim 4, it is characterized in that this code generator so makes up, cause this code generator to realize Bose-Lin sign indicating number.

9. according to the described device of claim 4, it is characterized in that this code generator so makes up, so that this code generator is realized a code generator table.

10. the method for construction feature symbol, the shift register of predetermined quantity wherein is set, be furnished with the logic linkage unit between these shift registers, input data to be tested are stored on these registers as continuous data word is parallel with bit-wise, and these shift registers will be imported data further and be shifted serially with the time clock that can be scheduled to, wherein after the data word of some and time clock, in shift register, make up a characteristic symbol, it is characterized in that, an also additional code generator and at least one the additional shift register of being provided with, wherein said data word is imported in this code generator, this code generator produces at least one additional bit from each data word, wherein should be transfused to this additional shift register by additional bit, this additional shift register is connected with the shift register of described predetermined quantity in order and has been constituted input feature vector sign register more than by these shift registers.