CN100490122C - Semiconductor element and making method - Google Patents
Semiconductor element and making method Download PDFInfo
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- CN100490122C CN100490122C CNB2005100081279A CN200510008127A CN100490122C CN 100490122 C CN100490122 C CN 100490122C CN B2005100081279 A CNB2005100081279 A CN B2005100081279A CN 200510008127 A CN200510008127 A CN 200510008127A CN 100490122 C CN100490122 C CN 100490122C
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Abstract
The method includes following steps: providing a substrate with storage unit zone and high voltage circuit zone; forming first, second source poles/drain poles zones on the two pieces of zone in the substrate; forming oxidizing layer, first conductive layer and topping layer in sequence on the substrate; defining floating grid on the storage unit zone, and removing out the topping layer and the first conductive layer from the high voltage circuit zone; thickening exposed the oxidizing layer; removing out the topping layer, and forming barrier layer on the exposed surface of floating grid; forming second conductive layer, defining out grid pole in the high voltage circuit zone, and defining out control grid pole in storage unit zone. Combining procedure for preparing storage unit and high voltage components, the method does not need to increase number of using photoresist so as to shorten fabricating flow and lowering fabricating cost.
Description
Technical field
The present invention relates to a kind of manufacture method of integrated circuit, particularly relate to a kind of semiconductor element and manufacture method thereof.
Background technology
Non-volatility memorizer (Non-Volatile Memory) is because of its circuit design, memory that is deposited in or data can not disappear because of the interruption of power supply supply, data can be carried out the action that deposits in, reads and remove repeatedly, and it has, and volume is little, access speed reaches the low advantage of power consumption soon, on the market it is had suitable demand.Yet the existing and non-volatility memorizer high voltage device process integration is a single level polysilicon disposable programmable element at present.This kind single level polysilicon disposable programmable element is more similar to the general high voltage element because of its structure, and is more or less freely in the integration of technology, by general industry is commonly used.But single level polysilicon disposable programmable element is low because of its tolerance, and reusable number of times is not high, and the user just wins access about tens of approximately times, clearly, can't take the demand on the industry into account.
Though it is more as for the accessible number of times of the read-only memory of traditional erasable programmable, but because memory cell need form two-layer polysilicon layer, with respectively as floating grid and control grid usefulness, between the two-layer polysilicon layer of memory cell and the high voltage device grid in other circuit region difference in height is arranged, so both process integration difficulty height, industry is not always with both process integration, even if memory and high voltage device will be formed on the same chip, often need extra several photoresist, therefore program is complicated, elongate overall Production Time, the manufacturing cost thereby the reduction of having no way of.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of semiconductor element is being provided, and makes that the read-only memory of erasable programmable and the manufacture process of high voltage device are integrated, and need not increase the photoresist number.
Another object of the present invention provides a kind of manufacture method of semiconductor element, the problem that the method can't can't be integrated with high voltage device except the read-only memory that can solve existing erasable programmable, low voltage component or he can also be planted semiconductor element and integrate mutually, improve and make efficient with the above two technology.
Another purpose of the present invention provides a kind of semiconductor element, and this kind is used for that memory in the high voltage device repeats to deposit in and the number of times of erasing is increased, and makes the data of storage be able to permanent preservation.
The present invention proposes a kind of manufacture method of semiconductor element, and the method provides substrate earlier, and this substrate comprises memory cell areas and high voltage circuit area.Then, in the substrate of memory cell areas, form first source/drain regions, and in the substrate of high voltage circuit area, form second source/drain regions.In substrate, form oxide layer, first conductive layer and cap layer then in regular turn.Continue it, the patterning cap layer and first conductive layer defining a floating grid in memory cell areas, and remove the cap layer and first conductive layer in the high voltage circuit area simultaneously.Next, carry out oxidation technology, so that the oxide layer that exposes thickens.Afterwards, remove the cap layer of memory cell areas, form the barrier layer on the floating grid surface of coming out then.In substrate, form second conductive layer then, cover oxide layer and barrier layer.Then patterning second conductive layer defining grid in high voltage circuit area, and defines the control grid in memory cell areas.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, on be set forth in and form before first and second source/drain regions, also be included in and form the high pressure wellblock in the substrate.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned thickness of oxide layer that is formed under first conductive layer is between 50 dust to 150 dusts.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned oxidated layer thickness that thickens is between 700 dust to 1000 dusts.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned oxide layer that thickens covers the sidewall of floating grid.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned oxidation technology comprises thermal oxidation technology.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material on above-mentioned barrier layer comprises silica.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the size of above-mentioned control grid is greater than the size of floating grid.
The present invention proposes the manufacture method of another kind of semiconductor element, at first provides substrate, substrate to include memory cell areas, high voltage circuit area and low-voltage circuit district.Afterwards, in the substrate of memory cell areas, form first source/drain regions, and in the substrate of high voltage circuit area, form second source/drain regions.Then, in substrate, form oxide layer, first conductive layer and cap layer in regular turn.Then, the patterning cap layer and first conductive layer defining floating grid in memory cell areas, and remove the cap layer and first conductive layer in the high voltage circuit area, and keep the cap layer and first conductive layer in the low-voltage circuit district.Next, carry out oxidation technology, so that the oxide layer that comes out thickens.Afterwards, remove first conductive layer and oxide layer in cap layer and the low-voltage circuit district.Next step forms the barrier layer on the surface of the exposure of floating grid, and forms gate insulation layer in the substrate in the low-voltage circuit district.Then, in substrate, form second conductive layer, cover gate insulation layer, oxide layer and barrier layer, patterning second conductive layer, in memory cell areas, to define the control grid, in high voltage circuit area, define first grid, and in the low-voltage circuit district, define second grid.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, on be set forth in and form before first and second source/drain regions, also be included in the substrate of memory cell areas and high voltage circuit area and form a high pressure wellblock.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned thickness of oxide layer that is formed under first conductive layer is between 50 dust to 150 dusts.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned oxidated layer thickness that thickens is between 700 dust to 1000 dusts.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the above-mentioned oxide layer that thickens covers the sidewall of floating grid.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material on barrier layer is identical with the material of gate insulation layer in the low-voltage circuit district in the said memory cells district.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the size of the control grid in said memory cells district is greater than the size of floating grid.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, on be set forth in and form after the second grid, also be included in the substrate in low-voltage circuit district and form the 3rd source/drain regions.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned oxidation technology comprises thermal oxidation technology.
The present invention proposes a kind of semiconductor element, and this semiconductor element comprises substrate, first source/drain regions, second source/drain regions, first grid insulating barrier, second gate insulation layer, floating grid, control grid, barrier layer and grid.Wherein substrate has memory cell areas and high voltage circuit area.First source/drain regions is to be configured in the substrate of memory cell areas.Second source/drain regions then is configured in the substrate of high voltage circuit area.In addition, first grid insulating barrier is in the substrate that is configured in the memory cell areas.As for second gate insulation layer is in the substrate that is configured in the high voltage circuit area, and wherein the thickness of second gate insulation layer is greater than the thickness of first grid insulating barrier.In addition, floating grid is to be positioned on the first grid insulating barrier.Insulating barrier is configured in the sidewall of this floating grid.The thickness of this insulating barrier equals the thickness of this second gate insulation layer.And the control grid is to be positioned at the floating grid top, wherein controls the size of the size of grid greater than floating grid.In addition, the barrier layer is to be disposed between floating grid and the control grid.Grid then is configured on second gate insulation layer.
According to the described semiconductor element of the preferred embodiments of the present invention, above-mentioned first source/drain regions is all identical with the degree of depth and the concentration of second source/drain.
According to the described semiconductor element of the preferred embodiments of the present invention, above-mentioned substrate also comprises the low-voltage circuit district, and comprises in the low-voltage circuit district and dispose a plurality of low voltage components.
The present invention can be with the process integration of memory cell and high voltage device together, and need not increase the photoresist number, therefore can shorten manufacturing process, reduces manufacturing cost.In addition, the present invention can also integrate low voltage component or other logic element with the technology of memory cell and high voltage device mutually.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A to Fig. 1 G is the manufacturing process generalized section according to a kind of semiconductor element of a preferred embodiment of the present invention.
Fig. 2 is the structural section according to a kind of semiconductor element of a preferred embodiment of the present invention.
The simple symbol explanation
100: substrate
101: the high pressure wellblock
103: isolation structure
102: memory cell areas
104: high voltage circuit area
106: the low-voltage circuit district
110a, 112a, 114a: source area
110b, 112b, 114b: drain region
122,122a: oxide layer
124,124a, 140: conductive layer
126,126a: cap layer
130: the barrier layer
122b, 132: gate insulation layer
124a: floating grid
142: the control grid
144,146: grid
Embodiment
Figure 1A to Fig. 1 G is the manufacturing process profile that illustrates according to a kind of semiconductor element of one embodiment of the present invention.
Please refer to Figure 1A, the manufacture method of semiconductor element of the present invention is for providing substrate 100 earlier, and this substrate 100 has memory cell areas 102, high voltage circuit area 104 and low-voltage circuit district 106.Wherein the material of substrate 100 for example is a silicon base, the semiconductor element kenel that cooperates institute's desire to form, and substrate 100 for example is P type silicon base or N type silicon base.Afterwards, in substrate 100, form isolation structure 103, defining many active elements district (not illustrating), and memory cell areas 102, high voltage circuit area 104, low-voltage circuit district 106 are kept apart.These isolation structures 103 for example are the fleet plough groove isolation structures (Shallow TrenchIsolation) to be illustrated among formed field oxide of regional oxidation (LOCOS) technology or the figure.
In a preferred embodiment, before or after forming isolation structure 103, also be included in the substrate 100 of memory cell areas 102 and high voltage circuit area 104 and form high pressure wellblock 101, the method of its formation for example is to carry out ion to inject, wherein for example be to inject P type ion or N type ion in the high pressure wellblock 101, its kenel on the element that institute's desire forms is decided.Afterwards, in the substrate 100 of memory cell areas 102, form the first source area 110a and the first drain region 110b, and in the substrate 100 of high voltage circuit area 104, form the second source area 112a and the second drain region 112b.Wherein, the formation method of source area 110a, 112a and drain region 110b, 112b for example is to carry out ion implantation technology, and by thermal process, makes the diffusion of impurities of injection.In a preferred embodiment, the first source/ drain regions 110a, 110b and the second source/ drain regions 112a, 112b form in same step, so the degree of depth of these two source/drain regions and concentration are all identical.
Then, form oxide layer 122, first conductive layer 124 and cap layer 126 in regular turn in substrate 100, wherein the 122 follow-up meetings of the oxide layer in memory cell areas 102 are used as first grid insulating barrier.In a preferred embodiment, the formation method of oxide layer 122 for example is thermal oxidation technology, chemical vapor deposition method or carries out other suitable technology.In a preferred embodiment, formed oxidated layer thickness for example is between 50 dust to 150 dusts.And the material of first conductive layer 124 for example is polysilicon or other suitable electric conducting material, and its formation method for example is to carry out chemical vapor deposition method.As for the material of cap layer 126 for example be silicon nitride or other suitable dielectric material, its formation method for example is a chemical vapor deposition method.
Continue it, please refer to Figure 1B, the patterning cap layer 126 and first conductive layer 124, with the cap layer 126a of formation patterning and the conductive layer 124a of patterning, and remove the cap layer 126 and first conductive layer 124 in the high voltage circuit area 104, wherein left conductive layer 124a is a floating grid in memory cell areas 102.The patterning cap layer 126 and first conductive layer 124, make the method that the cap layer 126 in the high voltage circuit area 104 and first conductive layer 124 also remove thereupon, and the cap layer 126a and the first conductive layer 124a in the low-voltage circuit district 106 are remained, and for example are to carry out photoetching process and etch process.
Then, please refer to Fig. 1 C, carry out oxidation technology, so that the oxide layer 122 that exposes thickens.The formation method of the oxide layer 122a that this thickens for example is a thermal oxidation technology, and the formed oxide layer 122a thickness that thickens for example is between 700 dust to 1000 dusts.In a preferred embodiment, the oxide layer 122a that thickens in the memory cell areas 102 covers the sidewall of floating grid 124a.
Next, please refer to Fig. 1 D, remove cap layer 126a in the memory cell areas 102 and the cap layer 126a in the low-voltage circuit district 106.Afterwards, remove the first conductive layer 124a and oxide layer 122 in the low-voltage circuit district 106.
Next step please refer to Fig. 1 E, and the floating grid 124a surface of coming out in memory cell areas 102 forms barrier layer 130, and forms gate insulation layer 132 in the substrate in low-voltage circuit district 106 100.In a preferred embodiment, formed barrier layer 130 is identical with the material of formed gate insulation layer 132 in the low-voltage circuit district 106 in the memory cell areas 102, and it for example is that silica and its formation method for example are thermal oxidation technology or chemical vapor deposition method.
Afterwards, please refer to Fig. 1 F, in substrate 100, form second conductive layer 140, cover gate insulation layer 132, the oxide layer 122a in the high voltage circuit area 104 and the barrier layer 130 in the memory cell areas 102 in the low-voltage circuit district 106.Wherein, the material of this second conductive layer 140 for example is a polysilicon, and its formation method for example is a chemical vapor deposition method.
Then, please refer to Fig. 1 G, patterning second conductive layer 140 to define control grid 142 in memory cell areas 102, defines first grid 144, and define second grid 146 in low-voltage circuit district 106 in high voltage circuit area 104.Wherein, the method for definition grid for example is to utilize photoetching process and etch process.In a preferred embodiment, the size of the control grid 142 in the memory cell areas 102 is greater than the size of floating grid 124a.
In addition, in another preferred embodiment, after forming second grid 146, also be included in the substrate 100 in low-voltage circuit district 106 and form the 3rd source area 114a and the 3rd drain region 114b.
Particularly, formed low voltage component is not limited to single kind of low voltage component in low-voltage circuit district 106, and it can also be the logic element of multiple low pressure, and it for example is the low voltage component with different gate insulation layer thickness.
In addition, what deserves to be mentioned is, though explain with the process integration in memory cell areas 102, high voltage circuit area 104 and low-voltage circuit district 106 in the above-described embodiment.As shown in Figure 2, the present invention can also only integrate at the high voltage circuit area 104 and the technology of memory cell areas 102 but in another preferred embodiment.And formed memory cell areas 102 can combine with other kind element or circuit with high voltage circuit area 104 afterwards again behind the process integration.
Below be illustrated at the structure of utilizing the said method gained.Please refer to Fig. 2, it illustrates the structural section of the semiconductor element with memory cell areas 102 and high voltage circuit area 104.
Wherein, include the first source/drain regions 110a/110b, first grid insulating barrier (oxide layer 122a), floating grid 124a, control grid 142 and barrier layer 130 in the memory cell areas 102.Wherein, the first source/drain regions 110a/110b is configured in the substrate 100 of memory cell areas 102.And first grid insulating barrier (oxide layer 122a) is disposed in the substrate 100 of memory cell areas 102.In addition, floating grid 124a is positioned on the first grid insulating barrier (oxide layer 122a).In addition, control grid 142 is positioned at floating grid 124a top, wherein controls the size of the size of grid 142 greater than floating grid 124a.Barrier layer 130 then is disposed between floating grid 124a and the control grid 142.
In addition, in high voltage circuit area 104, include the second source/drain regions 112a/112b, the second gate insulation layer 122b and grid 144.Wherein, the second source/drain regions 112a/112b is configured in the substrate 100 of high voltage circuit area 104.The second gate insulation layer 122b is configured in the substrate 100 of high voltage circuit area 104, and the thickness of the second gate insulation layer 122b is greater than the thickness of first grid insulating barrier (oxide layer 122a).Be configured on the second gate insulation layer 122b as for 144 of grids.
In a preferred embodiment, be configured in the first source/drain regions 110a/110b and the second source/drain regions 112a/112b that is configured in high voltage circuit area 104 substrates 100 in the substrate 100 of memory cell areas 102, both degree of depth and concentration are all identical.
In addition, in another preferred embodiment, this semiconductor element is except above-described memory cell areas 102 and high voltage circuit area 104, also comprise a low-voltage circuit district 106, shown in Fig. 1 G, comprise in this low-voltage circuit district 106 and disposed a plurality of low voltage components that each low voltage component for example is to have comprised the 3rd source/drain regions 114a/114b, gate insulation layer 132 and second grid 146.Wherein, the 3rd source/drain regions 114a/114b is the substrate 100 that is arranged in low-voltage circuit district 106.And gate insulation layer 132 is to be disposed in the substrate 100 in low-voltage circuit district 106.In addition, second grid 146 is to be positioned on the gate insulation layer 132.
In sum, the read-only memory of erasable programmable of the present invention can be incorporated in the technology of high voltage device, or in addition again with the process integration of low voltage component together, and do not need additionally to increase the photoresist number, therefore can reduce cost of manufacture.And because this has the read-only memory that memory in the semiconductor element of high voltage device is to use erasable programmable, so it deposits in and the number of times of the data of erasing can increase manyly, and is able to permanent storage data.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (18)
1, a kind of manufacture method of semiconductor element comprises:
One substrate is provided, and this substrate includes a memory cell areas and a high voltage circuit area;
In this substrate of this memory cell areas, form one first source/drain regions, and in this substrate of this high voltage circuit area, form one second source/drain regions;
In this substrate, form an oxide layer, one first conductive layer and a cap layer in regular turn;
This cap layer of patterning and this first conductive layer defining a floating grid in this memory cell areas, and remove this cap layer and this first conductive layer in this high voltage circuit area;
Carry out an oxidation technology, so that this oxide layer that exposes thickens, this oxide layer that wherein thickens covers the sidewall of this floating grid;
Remove this cap layer;
Form a barrier layer on this floating grid surface that exposes;
In this substrate, form one second conductive layer, cover this oxide layer and this barrier layer; And
This second conductive layer of patterning defining a grid in this high voltage circuit area, and defines a control grid in this memory cell areas.
2, the manufacture method of semiconductor element as claimed in claim 1 wherein before forming this first and second source/drain regions, also is included in and forms a high pressure wellblock in this substrate.
3, the manufacture method of semiconductor element as claimed in claim 1, wherein being formed on this beneath thickness of oxide layer of this first conductive layer is between 50 dust to 150 dusts.
4, the manufacture method of semiconductor element as claimed in claim 1, this oxidated layer thickness that wherein thickens are between 700 dust to 1000 dusts.
5, the manufacture method of semiconductor element as claimed in claim 1, wherein this oxidation technology comprises a thermal oxidation technology.
6, the manufacture method of semiconductor element as claimed in claim 1, wherein the material on this barrier layer comprises silica.
7, the manufacture method of semiconductor element as claimed in claim 1 wherein should be controlled the size of the size of grid greater than this floating grid.
8, a kind of manufacture method of semiconductor element comprises:
One substrate is provided, and this substrate includes a memory cell areas, a high voltage circuit area and a low-voltage circuit district;
In this substrate of this memory cell areas, form one first source/drain regions, and in this substrate of this high voltage circuit area, form one second source/drain regions;
In this substrate, form an oxide layer, one first conductive layer and a cap layer in regular turn;
This cap layer of patterning and this first conductive layer defining a floating grid in this memory cell areas, and remove this cap layer and this first conductive layer in this high voltage circuit area, and retain this cap layer and this first conductive layer in this low-voltage circuit district;
Carry out an oxidation technology, so that this oxide layer that comes out thickens, this oxide layer that wherein thickens covers the sidewall of this floating grid;
Remove this cap layer;
Remove this first conductive layer and this oxide layer in this low-voltage circuit district;
Surface in the exposure of this floating grid forms a barrier layer, and forms a gate insulation layer in this substrate in this low-voltage circuit district;
In this substrate, form one second conductive layer, cover this gate insulation layer, this oxide layer and this barrier layer; And
This second conductive layer of patterning to define a control grid in this memory cell areas, defines a first grid, and define a second grid in this low-voltage circuit district in this high voltage circuit area.
9, the manufacture method of semiconductor element as claimed in claim 8 wherein before forming this first and second source/drain, also is included in this substrate of this memory cell areas and this high voltage circuit area and forms a high pressure wellblock.
10, the manufacture method of semiconductor element as claimed in claim 8, wherein being formed on this beneath thickness of oxide layer of this first conductive layer is between 50 dust to 150 dusts.
11, the manufacture method of semiconductor element as claimed in claim 8, this oxidated layer thickness that wherein thickens are between 700 dust to 1000 dusts.
12, the manufacture method of semiconductor element as claimed in claim 8, wherein the material on this barrier layer is identical with the material of this gate insulation layer.
13, the manufacture method of semiconductor element as claimed in claim 8 wherein should be controlled the size of the size of grid greater than this floating grid.
14, the manufacture method of semiconductor element as claimed in claim 8 wherein after forming this second grid, also is included in this substrate in this low-voltage circuit district and forms one the 3rd source/drain regions.
15, the manufacture method of semiconductor element as claimed in claim 8, wherein this oxidation technology comprises a thermal oxidation technology.
16, a kind of semiconductor element comprises:
One substrate, this substrate have a memory cell areas and a high voltage circuit area;
One first source/drain regions is configured in this substrate of this memory cell areas;
One second source/drain regions is configured in this substrate of this high voltage circuit area;
One first grid insulating barrier is configured in this substrate in this memory cell areas;
One second gate insulation layer is configured in this substrate in this high voltage circuit area, and wherein the thickness of this second gate insulation layer is greater than the thickness of this first grid insulating barrier;
One floating grid is positioned on this first grid insulating barrier;
One insulating barrier is configured in the sidewall of this floating grid, and the thickness of this insulating barrier equals the thickness of this second gate insulation layer;
One control grid is positioned at this floating grid top, wherein should control the size of the size of grid greater than this floating grid;
One barrier layer is disposed between this floating grid and this control grid; And
One grid is configured on this second gate insulation layer.
17, semiconductor element as claimed in claim 16, wherein this first source/drain regions is all identical with the degree of depth and the concentration of this second source/drain.
18, semiconductor element as claimed in claim 16, wherein this substrate also comprises a low-voltage circuit district, and comprises in this low-voltage circuit district and dispose a plurality of low voltage components.
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| CNB2005100081279A CN100490122C (en) | 2005-02-05 | 2005-02-05 | Semiconductor element and making method |
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| CNB2005100081279A CN100490122C (en) | 2005-02-05 | 2005-02-05 | Semiconductor element and making method |
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