CN100487615C - Single-line two-way communication method of reorganizable controller - Google Patents
Single-line two-way communication method of reorganizable controller Download PDFInfo
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Abstract
A single line bidirectional communication method of a reconfigurable controller belonging to the technology field of communication engineering is provided. Through upper computer interface conversion module, the invention transforms positive and negative logical signals of serial communication into difference voltage signal and sends to a signal processing module, wherein, a microprocessor is for processing and responding to delivered message protocol, conversely, the information can also be sent from reconfigurable controller to the upper computer, and the delivered message protocol can be responded by the upper computer, during responsion, corresponding operations are executed according to different operating commands, the commands comprise starting parameterization, reading erasable memorizer operation, writing erasable memorizer operation, whole piece erasure operation of the erasable memorizer, stopping parameterization; during the operation execution, the communication state is displayed in real-time according to real-time communication state. By utilizing the characteristic of single line communication in the invention, wire harnesses are reduced for more than a half than universal serial or other wired communication, thereby realizing the stability of information interaction and data transferring of each numerical module.
Description
Technical field
The present invention relates to a kind of method of communication engineering technical field, particularly a kind of mongline two-way communication method of Reconfigurable Control device.
Background technology
The Reconfigurable Control device has good characteristics such as modularization, opening and portability because of it, and becomes the inexorable trend of controller developing direction.Information communication is as the contact tie between Reconfigurable Control device and the numerical control module, its effect is that the instruction of Reconfigurable Control device or data are sent to corresponding numerical control module, with the processing sequence of adjusting the numerical control module or realize other functions, simultaneously the information state of adjusted numerical control module is fed back to controller.Compare with the communication mode of traditional controller, the communication mode of Reconfigurable Control device is flexible more, open, has solved the shortcoming of the closure of traditional controller.
But,, need consider many-sided factors such as stability, arrangement space, interface, costs in view of the open reason of Reconfigurable Control device.And the standard traffic standard that present neither one is used for the Reconfigurable Control device can be used.General bluetooth, wireless communications method such as infrared, technical sophistication, cost is higher, and is subjected to the interference of various factors easily; Though serial, parallel or network communication method are simple and easy to usefulness, complex interfaces is unfavorable for the space layout of wire harness.
Find through literature search prior art, poplar is built and just waits the people at " the 8th postgraduate scientific seminar collection of thesis of Postgraduate School, Chinese Academy of Sciences's " 21 century Computer Science and Technology " " 2004 (7): " based on the design and the realization of the Reconfigurable Control device communications platform of CORBA " delivered on the 49-50, propose in this article to adopt the CORBA technology to realize a kind of communication means of open architecture controller, specific implementation is to introduce Real-Time Middleware CORBA technology in existing open architecture controller, controller software and system platform are separated, the communication that comes administration module spare by the CORBA technology is with mutual, its deficiency is the realization technical sophistication of the method, is unfavorable for popularizing of Reconfigurable Control device.The Chinese patent application patent No. 200410018473.0, patent name are the restructural digital control module, and this patent has proposed the reconfigurability of interface, and the com interface that each control module is passed through separately keeps intercommunication mutually.The software implementation method of having mentioned communication system that this invention is just summarized is not specifically related to means of communication or the method used.
Summary of the invention
The present invention is directed to above-mentioned the deficiencies in the prior art, a kind of mongline two-way communication method of Reconfigurable Control device has been proposed, make its by initiation parameter, the operation of read/write scratch pad memory, scratch pad memory monoblock erase operation, stop parametrization, realize the information interaction of each numerical control module and the stability of data transfer, wherein said single line can be that K bus or LIN bus constitute.
The present invention is achieved through the following technical solutions, comprises the steps:
Step 1, host computer sends communication file to signal conversion module input port from the serial port of host computer with the mixed logic signal by the form of communication protocol specified standard frame;
Described communication protocol specified standard frame is made up of the plurality of data bag, and each packet is by data packet head, data byte and verification and form, and data packet head is made up of operational order and operation address again.
Step 2, signal conversion module are converted into the differential voltage signal of single line to the mixed logic signal of serial communication after receiving communication file, and differential voltage signal are outputed to the signal processing module of Reconfigurable Control device;
Step 3 after the signal processing module of Reconfigurable Control device receives differential voltage signal, is resolved the file of receiving by the microprocessor of signal processing module inside;
Described microprocessor is resolved the file of receiving, be meant the operational order and the operation address that extract in the data packet head, and before executable operations, in scratch pad memory, seek the start address of the current operation of beginning, carry out initiation parameter again after the addressing success, read the scratch pad memory operation, write scratch pad memory operation, monoblock erasing erasable storer, stop any one or several traffic operation in the parametrization.
Described operational order comprises: initiation parameter, the operation of read/write scratch pad memory, scratch pad memory monoblock erase operation, stop parametrization.
Step 4 if when communicating by letter first, is carried out the operation of initiation parameter, otherwise is skipped this step;
The described operation of carrying out initiation parameter, be meant that microprocessor extracts the initiation parameter operational order in the data packet head, obtain the address location of monoblock scratch pad memory, carry out reading and writing data or exchange subsequent operation getting ready for successfully connecting, when traffic operation, microprocessor is handled the Data Control of scratch pad memory with the speed of maximum, and when initiation parameter is operated successfully, microprocessor is again by increasing data head, data tail and verification and with the form reverse link communication of encapsulation framing make host computer obtain the information of current operation and obtain the version number of related software.
Step 5 after step 4, if revise or rewrite the interior perhaps data of the scratch pad memory in the signal processing module, is then carried out scratch pad memory monoblock erasing instruction, otherwise is gone to step 7;
Described execution scratch pad memory monoblock erasing instruction; be meant that host computer sends the signal processing module of scratch pad memory monoblock obliterated data bag to the Reconfigurable Control device; carry out the erase operation of all data in the scratch pad memory; and when operating successfully; host computer obtain current associative operation comprise instruction and verification and Frame; when operation exception or time-delay, host computer obtains unusual contingent reason.
After data have been wiped free of in the step 6, scratch pad memory, carry out the operation of writing the scratch pad memory parameter;
The scratch pad memory parameter is write in described execution, be meant the frame file that sends the packet that comprises the write operation instruction by host computer, be sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor in the signal processing module carries out dissection process to the frame file, related data information is write in the scratch pad memory, and if write data to scratch pad memory success host computer obtain current operation comprise instruction and verification and Frame; If unusual the generation then stops write operation, host computer provides the reason that exception error may take place.
Step 7 is if only need read data in the scratch pad memory, the operation that then can directly read the scratch pad memory parameter after step 4; Otherwise via reading the scratch pad memory parameter after four, five, six steps;
The described scratch pad memory parameter that reads, be meant the frame file that sends the packet that comprises the read operation instruction by host computer, be sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor carries out dissection process to the frame file, seek the current scratch pad memory start address that will read, carry out read operation, if read the data success in the scratch pad memory, then host computer obtain comprise read scratch pad memory instruction, the current data that read and verification and information; If read latch or unusual the generation, then host computer provides the reason that relevant error takes place, described read latch, and the setting of its time is relevant with communication speed.
Step 8, when all communication processs finish, the host computer transmission stops the signal processing module of the frame of parametrization operation to the Reconfigurable Control device, when the microprocessor of signal processing module receives current data, resolve and get access to when stopping parameterized instruction manipulation, discharge all control function, finish whole traffic operation.
Compared with prior art, the present invention has following beneficial effect: the present invention passes through assessment and the analysis to the communication interface of Reconfigurable Control device, utilize the characteristics of single line communication, not only make the cheap of whole communication facilities, wire harness has reduced over half than general serial or other wire communications, and realizes the information interaction of each numerical control module and the stability of data transfer easily; In general, realized simple ease for use and reliability on the communication system software and hardware of Reconfigurable Control device; From technology angle, technology maturation is safeguarded simple; From the cost input, the invention enables the input cost of hardware low, easily popularize.
Description of drawings
Fig. 1 is a workflow diagram of the present invention;
Fig. 2 is the system framework figure of the employed mongline two-way communication equipment of embodiments of the invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 2, the equipment that present embodiment adopts comprises: the RS232 port, signal conversion module, the signal processing module of Reconfigurable Control device, signal conversion module comprises the RS232 serial driver and the first single line Control Driver, the signal processing module of Reconfigurable Control device comprises scratch pad memory, microprocessor, the second single line Control Driver, the RS232 port is arranged in host computer, comprise RS232 output port and RS232 input port, the RS232 output port is connected with the signal input port of RS232 serial driver, the signal output port of RS232 serial driver is connected with the RS232 input port, the RS232 serial driver will be converted into Transistor-Transistor Logic level from the mixed logic communication level of host computer, another of the serial input/output port of the first single line Control Driver and RS232 serial line interface driver links to each other to the I/O mouth, the order wire of the first single line Control Driver is connected with the order wire of the second single line Control Driver, the serial ports of the second single line Control Driver is connected with the serial port of microprocessor, scratch pad memory links to each other with signal port with the address port of microprocessor with signal port by address port, control the operation of scratch pad memory by microprocessor by address wire and signal wire, the second single line Control Driver transforms into the TTL signal of serial ports input the differential electric signal of single line output.
As shown in Figure 1, present embodiment specifically comprises the steps:
Step 1, host computer sends communication file to signal conversion module input port from the serial port of host computer with the mixed logic signal by the form of communication protocol specified standard frame.
Described communication protocol specified standard frame is made up of the plurality of data bag, and each packet is by data packet head, data byte and verification and constitute, and data packet head is made of operational order and operation address again.
Step 2, signal conversion module are converted into the differential voltage signal of single line to the mixed logic signal of serial communication after receiving communication file, and differential voltage signal are outputed to the signal processing module of Reconfigurable Control device.
Step 3 after the signal processing module of Reconfigurable Control device receives differential voltage signal, is resolved the file of receiving by microprocessor;
Described microprocessor is resolved the file of receiving, be meant the operational order and the operation address that extract in the data packet head, and before executable operations, in scratch pad memory, seek the start address of the current operation of beginning, carry out initiation parameter again after the addressing success, read the scratch pad memory operation, write scratch pad memory operation, monoblock erasing erasable storer, stop any one or several traffic operation in the parametrization.
Described operational order comprises: initiation parameter, the operation of read/write scratch pad memory, scratch pad memory monoblock erase operation, stop parametrization.The message information content of concrete traffic operation sees Table one.
The message information of the message operation of table one single line communication
| Message name | Instruction (sexadecimal) ID | Instruction (decimal system) ID | Form |
| Initiation parameter | 0x00 | 0 | Set form |
| Stop parametrization | 0x01 | 1 | Set form |
| The scratch pad memory monoblock is wiped | 0x02 | 2 | Set form |
| Read the scratch pad memory parameter | 0x04 | 4 | Set form |
| Write the scratch pad memory parameter | 0x05 | 5 | Set form |
Step 4 if when communicating by letter first, is carried out the operation of initiation parameter, otherwise is skipped this step.
The described operation of carrying out initiation parameter, be meant that microprocessor extracts the initiation parameter operational order in the data packet head, obtain the address location of monoblock scratch pad memory, carry out reading and writing data or exchange subsequent operation getting ready for successfully connecting, when traffic operation, microprocessor is handled the Data Control of scratch pad memory with the speed of maximum, and when initiation parameter is operated successfully, microprocessor is again by increasing data head, data tail and verification and with the form reverse link communication of encapsulation framing make host computer obtain the information of current operation and obtain the version number of related software.
The message format that host computer received when table two and table three represented respectively that initiation parameter sends reverse link communication behind message and the initiation parameter.
Table two initiation parameter sends message format
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x00 | The beginning parametrization |
| 3 | CHKSUM | 0xA8 | Verification and |
The message format that host computer receives after table three initialization
| Position # | Title | Content | Implication |
| 1 | LEN | X-1 | Data bit length |
| 2 | ID | 0x00 | Iterated command |
| 3..[X-1] | DATA[n] | Version number with ASCII character string representation software | |
| 3 | CHKSUM | Verification and |
Step 5 after step 4, if revise or rewrite the interior perhaps data of the scratch pad memory in the signal processing module, is then carried out scratch pad memory monoblock erasing instruction, otherwise is gone to step 7.
Described execution scratch pad memory monoblock erasing instruction; be meant that host computer sends the signal processing module of scratch pad memory monoblock obliterated data bag to the Reconfigurable Control device; carry out the erase operation of all data in the scratch pad memory; and when operating successfully; host computer obtain current associative operation comprise instruction and verification and Frame; when operation exception or time-delay, host computer obtains unusual contingent reason.
Following table four expression scratch pad memory monoblock is wiped the transmission message format, the message format that host computer received after the scratch pad memory monoblock was wiped and sent successfully under the table five expression normal condition.
Table four scratch pad memory monoblock is wiped the transmission message format
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x02 | The scratch pad memory monoblock is wiped |
| 3 | CHKSUM | 0xAA |
The message format that host computer received after table five sent successfully
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x02 | Iterated command |
| 3 | CHKSUM | 0xAA | Verification and |
After data have been wiped free of in the step 6, scratch pad memory, carry out the operation of writing the scratch pad memory parameter.
The scratch pad memory parameter is write in described execution, be meant the frame file that sends the packet that comprises the write operation instruction by host computer, be sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor in the signal processing module carries out dissection process to the frame file, related data information is write in the scratch pad memory, and if write data to scratch pad memory success host computer obtain current operation comprise instruction and verification and Frame; If unusual the generation then stops write operation, host computer provides the reason that exception error may take place.
Below table six expression write the message format of scratch pad memory parameter, table seven expression writes the message format that the host computer when correct receives.
Table six is write scratch pad memory and is sent message format
| Position # | Title | Content | Implication |
| 1 | LEN | X | Data bit length |
| 2 | ID | 0x05 | Write the scratch pad memory parameter |
| 3 | ADDR_HI | The high eight-bit of address | |
| 4 | ADDR_LO | Address low eight | |
| 3..[X-1] | DATA[n] | Write the data of scratch pad memory | |
| X | CHKSUM | Verification and |
Table seven writes the message format that the host computer when correct receives
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x05 | Iterated command |
| 3 | CHKSUM | 0xAD | Verification and |
Step 7 is if only need read data in the scratch pad memory, the operation that then can directly read the scratch pad memory parameter after step 4; Otherwise via reading the scratch pad memory parameter after four, five, six steps.
The described scratch pad memory parameter that reads, be meant the frame file that sends the packet that comprises the read operation instruction by host computer, be sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor carries out dissection process to the frame file, seek the current scratch pad memory start address that will read, carry out read operation, if read the data success in the scratch pad memory, then host computer obtain comprise read scratch pad memory instruction, the current data that read and verification and information; If read latch or unusual the generation, then host computer provides the reason that relevant error takes place, described read latch, and the setting of its time is relevant with communication speed.
The message format of scratch pad memory parameter is read in following table eight expression, the message format that host computer obtained when table nine expression was read successfully.
Table eight is read scratch pad memory and is sent message format
| Position # | Title | Content | Implication |
| 1 | LEN | 5 | Data bit length |
| 2 | ID | 0x04 | Read the scratch pad memory parameter |
| 3 | ADDR_HI | The high eight-bit of address | |
| 4 | ADDR_LO | Address low eight | |
| 5 | NUM_BYTES | The byte number of reading of data | |
| 6 | CHKSUM | Verification and |
The message format that host computer obtained when table nine read successfully
| Position # | Title | Content | Implication |
| 1 | LEN | X-1 | The length of variable (NUM_BYTES+2) |
| 2 | ID | 0x04 | Iterated command |
| 3..[X-1] | DATA[NUM_BYTES] | The scratch pad memory data that receive | |
| X | CHKSUM | Verification and |
Step 8, when all communication processs finish, the host computer transmission stops the signal processing module of the frame of parametrization operation to the Reconfigurable Control device, when the microprocessor of signal processing module receives current data, resolve and get access to when stopping parameterized instruction manipulation, discharge all control function, finish whole traffic operation.Concrete message format sees Table ten and table ten one.
Table ten stops parametrization and sends message format
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x01 | Stop parametrization |
| 3 | CHKSUM | 0xA9 | Verification and |
Table ten one stops the message format that host computer obtains after the parametrization
| Position # | Title | Content | Implication |
| 1 | LEN | 2 | Data bit length |
| 2 | ID | 0x01 | Iterated command |
| 3 | CHKSUM | 0xA9 | Verification and |
Wherein, in above-mentioned each step the table described in verification and be achieved as follows shown in:
Verification and realization be to obtain by all code bits and given benchmark position (CHECKSUM_BASE) XOR.When verification that host computer obtains and with result behind all data XORs that receive be 0, then explanation communication is finished smoothly.
Present embodiment passes through assessment and the analysis to the communication interface of Reconfigurable Control device, utilize the characteristics of single line communication, not only constitute the cheap of whole communication facilities, wire harness has reduced over half than general serial or other wire communications, and realizes the information interaction of each numerical control module and the stability of data transfer easily.
Claims (8)
1. the mongline two-way communication method of a Reconfigurable Control device is characterized in that, comprises the steps:
Step 1, host computer sends communication file to signal conversion module input port from the serial port of host computer with the mixed logic signal by the form of communication protocol specified standard frame;
Step 2, signal conversion module are converted into the differential voltage signal of single line to the mixed logic signal of serial communication after receiving communication file, and differential voltage signal are outputed to the signal processing module of Reconfigurable Control device;
Step 3 after the signal processing module of Reconfigurable Control device receives differential voltage signal, is resolved the file of receiving by the microprocessor of signal processing module inside, communicates operation by operational order in the parsing;
Step 4, if when communicating by letter first, microprocessor carries out the operation of initiation parameter, otherwise skips this step;
Step 5, after step 4, if revise or rewrite the interior perhaps data of the scratch pad memory in the signal processing module, then microprocessor is carried out scratch pad memory monoblock erasing instruction, otherwise goes to step 7;
After data had been wiped free of in the step 6, scratch pad memory, microprocessor was carried out the operation of writing the scratch pad memory parameter;
Step 7, if only need read data in the scratch pad memory, then microprocessor is promptly directly read the operation of scratch pad memory parameter after step 4, otherwise microprocessor reads the scratch pad memory parameter after via four, five, six steps;
Step 8, when all communication processs finish, the host computer transmission stops the signal processing module of the frame of parametrization operation to the Reconfigurable Control device, when the microprocessor of signal processing module receives current data, resolve and get access to when stopping parameterized instruction manipulation, discharge all control function, finish whole traffic operation.
2. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that, described communication protocol specified standard frame is made up of the plurality of data bag, each packet is by data packet head, data byte and verification and form, and data packet head is made up of operational order and operation address again.
3. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that, described microprocessor is resolved the file of receiving, be meant the operational order and the operation address that extract in the data packet head, and before executable operations, in scratch pad memory, seek the start address of the current operation of beginning, carry out initiation parameter again after the addressing success, read the scratch pad memory operation, write scratch pad memory operation, monoblock erasing erasable storer, stop any one or several traffic operation in the parametrization.
4. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that described operational order comprises: initiation parameter, read scratch pad memory operation, write scratch pad memory operation, scratch pad memory monoblock erase operation, stop parametrization.
5. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that, the described operation of carrying out initiation parameter, be meant that microprocessor extracts the initiation parameter operational order in the data packet head, obtain the address location of monoblock scratch pad memory, carry out reading and writing data or exchange subsequent operation getting ready for successfully connecting, when traffic operation, microprocessor is handled the Data Control of scratch pad memory with the speed of maximum, and when initiation parameter is operated successfully, microprocessor is again by increasing data head, data tail and verification and with the form reverse link communication of encapsulation framing make host computer obtain the information of current operation and obtain the version number of related software.
6. the mongline two-way communication method of Reconfigurable Control device according to claim 1; it is characterized in that; described execution scratch pad memory monoblock erasing instruction; be meant that host computer sends the signal processing module of scratch pad memory monoblock obliterated data bag to the Reconfigurable Control device; microprocessor in the signal processing module is carried out the erase operation of all data in the scratch pad memory; and when operating successfully; host computer obtain current associative operation comprise instruction and verification and Frame; when operation exception or time-delay, host computer obtains the reason of unusual generation.
7. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that, the operation of scratch pad memory parameter is write in described execution, be meant the frame file that sends the packet that comprises the write operation instruction by host computer, the frame file is sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor in the signal processing module carries out dissection process to the frame file, related data information is write in the scratch pad memory, if write data to scratch pad memory success, then host computer obtain current operation comprise instruction and verification and Frame; If unusual the generation then stops write operation, host computer provides the reason that exception error takes place.
8. the mongline two-way communication method of Reconfigurable Control device according to claim 1, it is characterized in that, the described scratch pad memory parameter that reads, be meant the frame file that sends the packet that comprises the read operation instruction by host computer, the frame file is sent to the signal processing module of Reconfigurable Control device by signal conversion module, microprocessor carries out dissection process to the frame file, seek the current scratch pad memory start address that will read, carry out read operation, if read the data success in the scratch pad memory, then host computer obtains to comprise and reads the scratch pad memory instruction, current data that read and verification and information; If read latch or unusual the generation, then host computer provides the reason that relevant error takes place, and the time of read latch is provided with relevant with communication speed.
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| CN104460406B (en) * | 2014-10-13 | 2017-04-26 | 深圳市江波龙电子有限公司 | Single-line communication method and single chip microcomputer firmware updating method based on single-line communication |
| CN108231126A (en) * | 2016-12-15 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of EMMC test methods and device |
| CN108231127A (en) * | 2016-12-15 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of EMMC test methods and device |
| CN109564557B (en) * | 2017-03-01 | 2021-01-29 | 华为技术有限公司 | Single-wire communication method and equipment |
| CN108874705B (en) * | 2018-05-03 | 2021-07-27 | 芜湖懒人智能科技有限公司 | Serial port-to-single line communication circuit |
| CN112968656B (en) * | 2021-02-01 | 2023-03-24 | 珠海格力电器股份有限公司 | Control device and method of motor controller and motor |
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