CN100479187C - Trench MOSFET technology for DC-DC converter applications - Google Patents
Trench MOSFET technology for DC-DC converter applications Download PDFInfo
- Publication number
- CN100479187C CN100479187C CNB2004800025944A CN200480002594A CN100479187C CN 100479187 C CN100479187 C CN 100479187C CN B2004800025944 A CNB2004800025944 A CN B2004800025944A CN 200480002594 A CN200480002594 A CN 200480002594A CN 100479187 C CN100479187 C CN 100479187C
- Authority
- CN
- China
- Prior art keywords
- groove
- region
- generates
- converter according
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000002441 reversible effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 26
- 239000010703 silicon Substances 0.000 description 26
- 239000002019 doping agent Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 230000005669 field effect Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 101100028477 Drosophila melanogaster Pak gene Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A trench power semiconductor device including a recessed termination structure (15).
Description
Technical field
The present invention relates to the application of groove mos field effect transistor (MOSFET) technology in DC-to-DC (DC-DC) converter.
The cross reference of relevant application
The application is the U.S. Patent application of submitting in September, 2003 the 10/674th, No. 444, autograph continues for the part of " semiconductor device processing ", this application requires in the U.S. Provisional Application the 60/415th of submission on September 30th, 2002, the priority that No. the 60/444th, 064, the U.S. Provisional Application of submitting in No. 302 and on January 29th, 2003.Also based on No. the 60/444th, 064, the U.S. Provisional Application of submitting on January 29th, 2003, denomination of invention is " application of trench MOSFET technology in DC-DC converter " to the application, requires priority hereby.
Background technology
DC-DC (DC-to-DC) converter is mainly used in the battery-operated devices such as laptop computer, mobile phone, personal digital assistant, is used for regulating cell to offer the electric power of device.The battery life that is used for mobile device depends on the efficient of power circuit, and is therefore, growing, require to provide the battery requirements of bigger electric energy and longer service time to become the important factor that the designer improves the DC-DC transducer effciency.
If some feature of semiconductor switching device can improve in the converter, the efficient of DC-DC converter is can be improved.Particularly when power supply mos field effect transistor (MOSFET) when being used for converter, the electric current capacitive that reduces on-resistance and grid electric charge and increase MOSFET will play an important role to the efficient that improves device.
A kind of method of improving power supply MOSFET key property, for example, the method for the on-resistance of MOSFET is the cell density that increases its active region.Yet the increase of cell density may be subjected to forming the restriction of the inherent defect of the material condition of this device and manufacturing procedure among the power supply MOSFET.
Photoetching is a special link in the course of processing, and it diminishes apparatus parts and is restricted.The material condition that part diminishes among a kind of MOSFET of restriction is to make the surface plane of the silicon chip of this device.In general, when the part of semiconductor device is made lessly, thereby when parts density strengthened, the surface of silicon chip (or silicon chip becomes the pole plate of its part in the course of processing) must make flatly as far as possible, so that the part that installs during the photoetching can normal imaging.When parts density increased, the surface plane of silicon chip just became critical factor.
Therefore, comparatively desirable method is the limitation that overcomes previous technology, so that obtain to have the device that source battery is arranged of higher active region density.
Summary of the invention
The present invention relates to around the device active region and be built with the trench-type power source semiconductor device of groove end on structure at device under the main surface, active region.Described groove end on structure can reduce the electric field that accumulates in terminal in large quantities, thereby need not use the P+ guard ring, also not the puncture voltage of entail dangers to device and durability.
Groove end on structure of the present invention comprises a field oxide and a field plate that is positioned at above the field oxide, and both all are created on and are distributed in the groove on every side of device active region.Field oxide in the end on structure of the present invention is after termination trench forms in semi-conductor silicon chip, adopts the LOCOS operation to grow.After measured, when silicon chip was full-size in DPAK, the typical avalanche energy of end on structure of the present invention was greater than 1J.
According to one aspect of the present invention, field oxide is distributed in the below on this surface, device active region.When field oxide was seated the top of silicon face, the field oxide periphery just had the photoresist thickening effect, and this thickening effect makes during the photoetching very difficulty of explanation sub-micron part.As everyone knows, field oxide is distributed in the below of active region upper surface, might strengthens resolution and improve the production difficulty of sub-micron part significantly.Therefore, when adopting groove end on structure of the present invention, the size of groove can be dwindled, thus the cell density of aggrandizement apparatus.For example, use method of the present invention, the thin photoresist of utilization can reduce below the width to 0.5 micron of groove.Adopt method of the present invention can obtain 0.4 micron groove width, compare, 20% improvement has been arranged with previous technology.Can believe, use principle of the present invention can also produce littler part.
In addition, can also obtain the more shallow groove of the degree of depth according to the production process of device of the present invention, thereby also can improve such as on-resistance and current-carrying capacity characteristic.
Moreover, in view of reducing of accessory size, apparatus of the present invention comprise a higher groove density.But it is shocking that it still can keep low grid electric charge, particularly Q
GDAnd Q
SWITCHAlthough all descend to some extent such as groove width and the such accessory size of groove depth, it is higher that the integrality of gate oxide still keeps.The present inventor finds that its dielectric integrity can reach more than the 7MV/cm.
In addition, in the operation of producing a preferred embodiment of the present invention, use contact method to optimize the length of groove, reduced the on-resistance of device.Although be the accessory size of submicron order, this new process sequences can make the covering of metal platform rank reach 100% fully.It can also use thin epitaxial loayer further to reduce on-resistance.
Another benefit of using thin epitaxial loayer is to reduce Q
Rr, Q when high frequency
RrImportant to managing.In a device of the present invention, further optimization can make resistance substrate reduce about 50%.
Description of drawings
Fig. 1 is the part cross-sectional view of semiconductor device of the present invention.
Fig. 2 a-2u has described the technology of production apparatus of the present invention.
The canonical transformation device circuit that is based on previous technology that Fig. 3 shows.
The quality factor of Fig. 4 graphic extension apparatus of the present invention are functions of trench depth.
Fig. 5 a-5b and 6a-6b are with the figure efficient of circuit efficiency and previous technique device in apparatus of the present invention relatively.
Embodiment
In Fig. 1, semiconductor device of the present invention forms in silicon chip 5, the channel region 12 that silicon chip 5 comprises the drain region 10 of first conduction type and uses the conduction type doping agent opposite with drain region 10 doping agents to mix up slightly.Semiconductor device of the present invention comprises the multiple groove 14 that extends to drain region 10 from silicon chip 5 top surfaces, and groove 14 is formed gate electrode 16 in this utilization such as the polysilicon electric conducting material that mixes up.Gate electrode 16 is because of oxide layer 18 and channel region 12 electric insulations.Oxide layer 18 is grown on the side walls of every groove 14, must be noted that to be formed with a thicker oxide layer 15 in the bottom of every groove.
Semiconductor device of the present invention also comprises autoregistration source region 20, and it is configured in the opposite side of every groove 14 and extends to desired depth less than channel region 12 thickness.The doping agent of autoregistration source region 20 usefulness and drain region 10 same conductivity mixes up.
Each gate electrode 16 is configured in the top surface of gate spacer 22, at the top surface of each gate spacer 22 one deck low-temperature insulation material 24 is housed.The doping agent height of contact zone 26 usefulness and channel region 12 same conductivity mixes up, and it is adjacent with each source region 20, extends from the top surface of channel region 12, preferably extends to the degree of depth less than adjacent source regions 20 degree of depth.The contact zone 26 that highly mixes up is created on the concave bottom portion of silicon chip 5 top surfaces.Source contact layer 28 is made of aluminium alloy usually, be configured in silicon chip 5 top surfaces above, contact with contact zone 26 resistives with source region 20, thereby make source region 20 and contact zone 26 short circuits.Electric leakage contact layer 30 can constitute with other suitable weld metal of trivalent metal or some, is configured in the scope of freedom of silicon chip 5, and is relative with source contact layer 28, contacts with drain region 10 resistives.
Semiconductor of the present invention comprises and contains termination area 40.This termination area 40 comprises a groove end on structure.This groove end on structure comprises that the degree of depth is lower than the field oxide 44 and the field plate 50 on surface, active region (include and activate the unit).End on structure is configured in around the active region of device.
Fig. 1 has only shown the part of the semiconductor device of producing according to the present invention.Those of ordinary skill in the art are bound to know, in the semiconductor device of reality, the active region must comprise the groove 14 of greater number.
Semiconductor device shown in Figure 1 is a kind of groove kind.The trench-type device is that voltage is added on the gate electrode 16, transforms so that will be close to the zone of oxide layer 18, and its source region 20 is electrically connected with its drain region 10.Semiconductor device shown in Figure 1 is a kind of N channel device, and the polarity of putting upside down doping agent in every district just can obtain a P channel device.
All semiconductor devices as shown in Figure 1 are according to following explained hereafter.
At first come 2a with the aid of pictures, generate cushion oxide layer 32 during beginning earlier at silicon chip 5 epitaxial loayers 3 tops, mix up with the first conduction type doping agent.In the embodiment shown, the first conduction type doping agent is a N type doping agent.Then, the conduction type doping agent (P type) relative with the first conduction type doping agent injects by cushion oxide layer 32 and forms shallow channel injection region 34, and this is the channel region described below 12 (Fig. 1) that formed afterwards.
Come 2b with the aid of pictures below, nitride white layer 36 is deposited in the top of cushion oxide layer 32, and the activation mask that contains one deck photoresist 38 is deposited on the overwhelming majority of nitride white layer 36, only makes termination area 40 be exposed to the outside.Next step shown in Fig. 2 c, utilizes photoresist 38 as mask, for example adopts dry etching technology conventional, that people know or other suitable lithographic technique to generate termination recess 42.Remove photoresist 38 then, the doping agent in the shallow channel injection region 34 drives the channel region 12 shown in generation Fig. 2 d with the form of diffusion-driven.Though do not mark among the figure, must be noted that termination recess 42 has been configured in around the active region of device this moment.
Next step 2e with the aid of pictures again, field oxide 44 generate in termination recess 42, thereby groove field oxide end on structure can be provided.
Next step 2f with the aid of pictures, trench mask 46 has been deposited on the top surface of nitride white layer 36 and field oxide 44.Trench mask 46 comprises opening 48, and this opening can be discerned the position of the following groove 14 (Fig. 1) that generates in silicon chip 5.Next step, groove 14 is generating on the position by opening 48 identifications on the silicon chip 5, shown in Fig. 2 g.Groove 14 usefulness dry etchings generate, and extend to the predetermined degree of depth in drift region 4 from the top surface of silicon chip 5 by channel region 12.Must be pointed out that groove 14 also can extend to the position that is lower than drift region 4.Need point out also that simultaneously groove 14 can be parallel rectangular, hexagon or other some forms, though rectangular form is even more ideal, because rectangular form can further reduce the grid electric charge.
After groove 14 generated, one deck sacrificial oxide layer was in side walls and bottom growth, the etching then of groove 14.After this remove trench mask 46, next step generates cushion oxide layer 32, shown in Fig. 2 h in groove 14.2h with the aid of pictures again, nitride white layer 36 extends on the cushion oxide layer 32 that is positioned at groove 14 inside because of the nitride white layer precipitation.
2i with the aid of pictures more below, the part that is configured in the nitride white layer 36 of every groove 14 bottoms is eliminated by for example dry etching, and grows the oxide layer 15 of a bed thickness on every groove 14 bottoms.The nitride white layer 36 that is configured on every groove 14 side walls is a kind of retardant of oxidation agent, and it can stop the oxide growth on groove 14 side walls and allow to grow on every groove bottom the oxide layer of a bed thickness.Therefore, may be covered with one deck oxide layer as thin as a wafer on every groove 14 side walls, and its bottom is because 15 insulation fully of the oxide layer of a bed thickness.
Next step is shown in Fig. 2 j, and nitride white layer 36 parts that cover on groove 14 side walls are eliminated by for example wet etching, and gate oxide 18 is grown within every groove 14.With one deck polysilicon 50 precipitations, make groove 14 then by the polysilicon filling.
Next 2k with the aid of pictures again, the polysilicon mask 52 of generation covers termination area 40 at least, next, generates gate electrode 16, and polysilicon layer 50 is etched, so that all have polysilicon body to extend to the position that exceeds channel region 12 from its bottom in every groove 14 inside.Like this, one deck polysilicon is just stayed the below of polysilicon mask 52, and it will constitute field plate as shown in figure 21 in the back.
The top surface of the gate electrode 16 among the 2m next with the aid of pictures again, every groove 14 is by such as thermal oxidation and oxidation generates separator 22.Subsequently, nearly all nitride white layer 36 only stays near the sub-fraction nitride white layer 36 the end on structure of semiconductor device, shown in Fig. 2 n by being eliminated such as wet etching.
Follow to go out clearly after most nitride white layer 36, inject generation source region 20 required doping agents by the source mask and generate injection region, source 54, shown in Fig. 2 o.Injection region, source 54 had better not extend as the end on structure of device long.After injection region, source 54 generates, next be the entire top surface that low temperature oxide layer 24 is deposited in silicon chip 5, shown in Fig. 2 p.Must be noted that, after the polysilicon thermal oxidation generates separator 22, just generate injection region, source 54.After thermal oxidation process, inject the source doping agent, can make the last degree of depth in source region 20 remain to minimum.Like this, the thickness of the degree of depth of channel region 12 and epitaxial loayer 3 all can minimize.Therefore, can reduce the on-resistance of device by raceway groove in the shortening device and the thickness that reduces drift region 4.
Next source contact mask 56 generates on low temperature oxide layer 24, shown in Fig. 2 q.It generates by imitation photoetching agent layer in a kind of known mode, includes opening 58.Opening 58 at first is used for the part of taper etch low temperature oxide layer 24, makes the etching area extend laterally to source contact mask 56, extends lengthwise into the degree of depth that is lower than low temperature oxide layer 24 thickness.Then, use the opening 58 on the source contact mask 56 that etching is proceeded in the vertical, form groove 25, its degree of depth is lower than injection region, source 54, shown in Fig. 2 r.In case the source contact forms, initial taper etch can be improved step and cover.
Next source contact mask 56 is removed, the doping agent in the injection region, source 54 generates source region 20 because of diffusion-driven, shown in Fig. 2 s.After the diffusion-driven of source, as mask, next again by the implantation step of diffusion-driven, the contact zone 26 that highly mixes up generates between source region 20, shown in Fig. 2 t by utilization low temperature oxide layer 24.Then, low temperature oxide layer 24 may be etched and expose source region 20 parts of silicon chip 5 top end surfaces.
Efficient to apparatus of the present invention in converter circuit is evaluated.Please see Figure 3, one typical converter circuits and comprise Control FET (controlling filed effect transistor) 100 and Sync FET (synchronizing field effect transistor) 200.
In order to measure the efficient of apparatus of the present invention, produced the N channel device of several 30V, and the position of Sync FET 200 and the position of Control FET 100 are tested respectively in converter circuit.For Sync FET 200 and Control FET 100, the cell distance of every kind of device has all carried out optimization process, so that obtain performance in the best circuit.Table 1 has shown the quality factor of every kind of testing apparatus.
| Parameter | Unit | Control FET | Sync FET |
| R Si*AA@10V GS | mOhm* |
16 | 12 |
| R Si*AA@4.5V GS | mOhm* |
22 | 17 |
| R Si*Q G@4.5V GS | mOhm* |
75 | 77 |
| Q G/AA@4.5V GS | nC/mm 2 | 3.4 | 4.7 |
| Q GD/AA@4.5V GS | nC/mm 2 | 0.9 | 1.4 |
| Q SWITCH/AA@4.5V GS | nC/mm 2 | 1.3 | 1.8 |
Table 1
Known to the general general knowledge, in known reference depth, trench depth is dark more, and on-resistance is just low more., a darker groove but causes higher grid electric charge, and this does not meet needs.
Please see Figure 4, experimental data shows surprisingly, in a device of the present invention, if reduce the degree of depth of groove, can obtain the on-resistance an of the best and the combination, particularly Fig. 4 of grid electric charge and show that R*Qg and R*Qsw have minimum value when 100% nominal trench depth.
When die size is known,, adopted a kind of narrower cell distance in order to obtain alap on-resistance in Sync FET 200 positions.Cell distance that will be narrower and more shallow trench depth, low resistivity substrate and best epitaxial loayer combination can obtain unexpected low R
Si*The value of AA is 12mOhm*mm
2, and increase the grid electric charge not obviously.
In the position of Control FET 100, switching loss is the major part of total power consumption, and switching frequency rises strict more to the requirement of Control FET.When design Control FET 100, correct balance Rdson and grid electric charge are crucial.The advantage of apparatus of the present invention is can improve R*AA can improve Qg/AA again, therefore can produce the Control FET 100 of low grid electric charge and low on-resistance.The Control FET 100 of optimal design can reach the so low R of 75mohm.nC
*The Qg value.
In addition, suitable epitaxial optimization can make the Qrr of apparatus of the present invention from 13.4nC/mm
2Reduce to 5.1nC/mm
2, like this, switching frequency just can rise to and be higher than 1MHz.
Fig. 5 a-5b and 6a-6b have shown apparatus of the present invention and the previous technique device efficient comparative result when different switching frequency.Can find that from Fig. 5 a and 5b Control FET 100 of the present invention can provide at 200kHz and exceed 1% efficient, can provide at 1MHz to exceed 2% efficient.Fig. 6 a and 6b show that Sync FET 200 of the present invention can provide the efficient that exceeds 0.5%-1.5% respectively at 200kHz and 750kHz.
In sum, device of the present invention demonstrates superior performance.For example, when the optimization of the N of 30V slot field-effect transistor produced Sync FET 200, its quality factor R*AA can hang down and reach 12mOhm.mm
2When being configured to such as being trade mark with DirectFET, during the low temperature complete set of equipments sold by the agent, device of the present invention can transmit 113 amperes of peak currents, and its vestige is the vestige of the S0-8 complete set of equipments of overgauge never.Yet when being optimized to Control FET 100, the R*Qg of the N slot field-effect transistor of a 30V is 75mOhm.nC just only, and this is half of optimum value in the background technology known of current people.In device of the present invention, if epitaxial thickness is optimized, QRR Qrr/AA can be from 13.4nC/mm
2Reduce to 5.1nC/mm
2, the QRR of this reduction usually to high switching frequency (＞=1MHz) important to managing.When different switching frequency, these improved features all directly are converted to the circuit internal efficiency of bigger improvement.
Though the present invention is described with the certain embodiments form, for those of ordinary skill in the art, many other variation, modification and purposes are conspicuous.Therefore, the present invention preferably is not subjected to current specific openly being restricted, but is limited by additional claim.
Claims (8)
1, a kind of DC-DC converter, it comprises:
A synchronous semiconductor device; With
A control semiconductor device;
Wherein, at least a described semiconductor device comprises:
Semiconductor body with first conduction type, it comprises a channel region and a main surface with second conduction type;
An active region that in described semiconductor body, generates, described active region comprises a groove that extends to whole described channel region, with a grid structure that is configured in the described groove, described grid structure comprises the gate electrode of the gate oxide that is configured at least on the described groove side walls and and described gate oxide disposed adjacent; With
An end on structure, described end on structure comprises:
Termination trench that generates in described semiconductor body and one are in described termination trench and the field oxide that generates of described main lower face.
According to the described DC-DC converter of claim 1, it is characterized in that 2, described groove comprises an oxide bulk that generates in its bottom, described oxide bulk is than described gate oxidation bed thickness.
3, DC-DC converter according to claim 2, it is characterized in that, described semiconductor body is included in the conduction region with first conduction type that contiguous described groove generates in the described channel region, further, also comprise the Semiconductor substrate with described first conduction type, described semiconductor body generates on described Semiconductor substrate, wherein, the reversible raceway groove of described conduction region by closing on described groove is electrically connected with described Semiconductor substrate.
4, DC-DC converter according to claim 3 is characterized in that, described conduction region is the source region.
5, DC-DC converter according to claim 1 is characterized in that, the degree of depth of described groove is selected to obtaining best quality factor.
6, DC-DC converter according to claim 1 is characterized in that, described groove is rectangular groove.
7, DC-DC converter according to claim 1 is characterized in that, described groove is a unit.
8, DC-DC converter according to claim 7 is characterized in that, described unit is a hexagon.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44406403P | 2003-01-29 | 2003-01-29 | |
| US60/444,064 | 2003-01-29 | ||
| US10/766,465 | 2004-01-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1742377A CN1742377A (en) | 2006-03-01 |
| CN100479187C true CN100479187C (en) | 2009-04-15 |
Family
ID=36094018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800025944A Expired - Fee Related CN100479187C (en) | 2003-01-29 | 2004-01-28 | Trench MOSFET technology for DC-DC converter applications |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100479187C (en) |
| TW (1) | TWI270147B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5151258B2 (en) * | 2006-06-15 | 2013-02-27 | 株式会社リコー | Semiconductor device for step-up DC-DC converter and step-up DC-DC converter |
| CN102315264A (en) * | 2010-07-09 | 2012-01-11 | 苏州东微半导体有限公司 | Power device using spherical groove and making method for the power device |
| CN104795446B (en) * | 2015-04-17 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Trench gate mosfet and its manufacture method |
-
2004
- 2004-01-28 CN CNB2004800025944A patent/CN100479187C/en not_active Expired - Fee Related
- 2004-01-29 TW TW093101981A patent/TWI270147B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200423260A (en) | 2004-11-01 |
| TWI270147B (en) | 2007-01-01 |
| CN1742377A (en) | 2006-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9029215B2 (en) | Method of making an insulated gate semiconductor device having a shield electrode structure | |
| US7361555B2 (en) | Trench-gate transistors and their manufacture | |
| US7579650B2 (en) | Termination design for deep source electrode MOSFET | |
| US6929988B2 (en) | Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge | |
| US7332398B2 (en) | Manufacture of trench-gate semiconductor devices | |
| CN1695237B (en) | Semiconductor device processing | |
| US20100308400A1 (en) | Semiconductor Power Switches Having Trench Gates | |
| EP1415334A1 (en) | Manufacture of semiconductor devices with schottky barriers | |
| CN102007584A (en) | Semiconductor device structures and related processes | |
| JP4234586B2 (en) | Output MOSFET with deep injection junction | |
| US8921184B2 (en) | Method of making an electrode contact structure and structure therefor | |
| CN112864249A (en) | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof | |
| US7566622B2 (en) | Early contact, high cell density process | |
| US7557395B2 (en) | Trench MOSFET technology for DC-DC converter applications | |
| CN112864250A (en) | Groove type power semiconductor device for improving grid leakage charge and preparation method thereof | |
| CN100479187C (en) | Trench MOSFET technology for DC-DC converter applications | |
| US20030073289A1 (en) | Trench-gate semiconductor devices and their manufacture | |
| US11222974B2 (en) | Trench gate semiconductor device and method of manufacture | |
| TWI263279B (en) | Semiconductor device processing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090415 Termination date: 20120128 |