CN100479132C - Integrated circuit comb capacitor and forming method thereof - Google Patents
Integrated circuit comb capacitor and forming method thereof Download PDFInfo
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- CN100479132C CN100479132C CN200710001597.1A CN200710001597A CN100479132C CN 100479132 C CN100479132 C CN 100479132C CN 200710001597 A CN200710001597 A CN 200710001597A CN 100479132 C CN100479132 C CN 100479132C
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
Description
Technical field
The present invention relates generally to semiconductor device, more particularly, relate to improved integrated circuit comb capacitor.
Background technology
When the ULSI integrated circuit is reduced into littler size and function and current densities when increasing, the present and chips incorporate of the irrelevant Electronic Performances of many original and chips together.In addition, the distance that it utilizes the advantage of manufacturing cost and reduces electronic signal is with function and the performance cheap and the raising system of becoming.Become that a family device of integrate innovations focus is the BEOL passive device on the chip.Though their interconnection also is passive device strictly speaking, these terms are generally used for as resistor, capacitor, other passive electronic of inductor and varactor.Though being integrated in always, resistor and capacitor be used for transistor-transistor logic circuit among the FEOL, these FEOL passive devices lock into the non-linear and unnecessary spurious impedance of voltage always, and this makes it can not be used for analog circuit as a plurality of types of RF or wireless device.Usually in the time of only in being integrated in the BEOL wire level, inductor can obtain useful parameter.
To the BEOL capacitor, prevailing type of device is planar metal insulator metal (MIM) plane-parallel capacitor.This requires one or more additional optical mask level making down or electric pole plate, condenser dielectric with the contacting of battery lead plate.Common its is different from other interconnection that forms and contacts with via hole in identical wire level.The shortcoming of MIM capacitor is the mask that adds and the number of processing step, parasitic capacitance is asymmetric during with the coupling of the substrate of last or bottom electrode, the medium reliability that is used for enough capacitance densities under little thickness is limited, and the chip occupied area is often got rid of wiring the zone of requirement under MIM capacitor.
The BEOL capacitor of another kind of type is intersection comb shape-comb shape type; It comprises that a plurality of lines that are connected in parallel are to line capacitance device tooth (therefore, their capacitance), alternate bias between each is to line.Device depends between the wiring sidewall degree of depth of standard and minimum line spacing so that their electric capacity maximization.These sizes are set like this so that the single-stage comb shape-comb shape capacitance density of per unit layout area much smaller than the possible capacitance density of MIM capacitor, and the typically large-size that is associated with interconnect thickness and spacing departs from and makes it run into bigger challenge on design specification.On the other hand, intersect integrated circuit comb capacitor require not have additional photomask or processing step (as long as using medium between identical line) and for two electrodes not with substrate be coupled parasitic asymmetric.
Fig. 1 shows the integrated circuit comb capacitor 150 that forms according to prior art.Therefore according to prior art, compare with the interconnection 160 that forms in identical wire level, electrode for capacitors 150a has the identical degree of depth and the spacing between neighboring capacitors electrode 150a.Preferred capacitor is inlayed as the copper in low k dielectric (ε) material 102 of SiOH organic silicate glass by embedding and is made.Electrode for capacitors 150a is by their length (paper inside/outside), width, and if the degree of depth is spacing and be that trapezoidal their sidewall inclination angle (α) characterizes.When giving voltage in active IC circuit, continuous electrode 150a is typically so that alternately induction as Vdd (+) and ground connection (-) are setovered or had the AC signal with the execution capacitor function.
Recently, described a kind of integrated circuit comb capacitor 150 of enhancing, it has solved the part of the problems referred to above.Be called vertical parallel plates (VPP) capacitor, its multistage lamination by intersection integrated circuit comb capacitor 150 constitutes.To the VPP capacitor, area capacitance density equals the capacitance density of MIM device and does not increase photomask or processing step, and two electrodes is not had yet parasitic asymmetric.In addition, when multistage in conjunction with the time, the statistics variations of live width and spacing dimension tends to reach average so that obtain from the chip to the chip more consistent result with wafer to wafer, better mechanical performance and tolerance more closely.Shortcoming is the sum of series layout area that requirement obtains given electric capacity.
In present low k BEOL level, wherein the reduction of capacitance density directly and between line and the inter-stage dielectric constant proportional, integrated to the VPP capacitor, this shortcoming is more remarkable.This shortcoming is not suitable for the MIM situation of using the de-couple capacitors medium.Yet the other shortcoming of MIM capacitor still is applicable in low k BEOL integrated.In addition, promote dwindling of all wiring sizes along with CMOS dwindles, inter-stage BEOL vertical interval reduces and MIM thickness does not reduce, like this because on the MIM zone exceeding part make make difficult or impossible.Above-mentioned discussion provides, and still needs to obtain big capacitance density, particularly to low k BEOL integrated capacitor, and increases minimum mask level, the minimum capacitance tolerance, and keep electric capacity-parasitic symmetry of substrate coupling.
Needed in the technology is to improve low k BEOL integrated circuit comb capacitor, its minimum capacitance tolerance and symmetry and its additional masking level or processing step manufacturing with minimal amount of keeping electric capacity-substrate coupling parasitism.
Summary of the invention
The present invention is intended to a kind of method and structure.More particularly, method of the present invention is intended to a kind of method that is used to form capacitor, and this method comprises formation and modify steps.
Form step and be included in formation capacitor openings and noncapacitive device opening in the medium, and modify steps comprises the surface modified medium along capacitor openings, so that should revise the electric capacity that increases capacitor.More particularly, structure of the present invention is intended to comprise the capacitor of noncapacitive device and capacitor openings.In medium, form between noncapacitive device opening and the arest neighbors noncapacitive device opening in the same metal wire level and have prescribed distance, and the capacitor openings that in the same metal wire level, in medium, forms in the spacing that has between the arest neighbors capacitor openings less than the prescribed distance between arest neighbors noncapacitive device opening.
The first embodiment of the present invention is intended to be used to form the method for capacitor, and this method comprises deposition, forms, and protection is made, expansion and filling step.Deposition step comprises the deposition low k dielectric.The formation step is included in and forms opening in the low k dielectric, and wherein at least one opening is that non-capacitor openings and at least one opening are capacitor openings.The protection step comprises that any noncapacitive device opening of protection is not revised by dielectric constant.Manufacturing step comprises along the surface of capacitor openings makes the porous zone.Spread step comprises removing along the modification medium on the surface of capacitor openings by selectivity expands at least one capacitor openings.Filling step comprises with conductor material fills noncapacitive device opening and expanded capacitor device opening.
The second embodiment of the present invention is intended to be used to form the method for capacitor.This method comprises deposition, removes, and forms protection and implantation step.Deposition step comprises that deposition comprises the low k dielectric of dielectric matrix and pore former.Removing step comprises from low k dielectric and removes pore former.The formation step is included in and forms opening in the porous media, and wherein at least one opening is that non-capacitor openings and at least one opening are capacitor openings.The protection step comprises that any noncapacitive device opening of protection is not revised by dielectric constant.Implantation step comprises that the dielectric constant of described material is higher than the dielectric constant of porous media before described injection with the surface injection porous media of a material along capacitor openings.
The third embodiment of the present invention is intended to be used to form the method for capacitor, comprises deposition, forms, and protection is injected, and fills and remove step.Deposition step comprises that deposition comprises the low k dielectric of pore former.The formation step is included in and forms opening in the low k dielectric, and wherein at least one opening is that non-capacitor openings and at least one opening are capacitor openings.The protection step comprises that any noncapacitive device opening of protection is not fluctuateed by dielectric constant.Implantation step comprises that the dielectric constant of described material is higher than the dielectric constant of porous media before described injection with the surface injection porous media of a material along at least one capacitor openings.Filling step comprises with conductor material fills noncapacitive device and capacitor openings.Removing step comprises from low k dielectric and removes pore former.
The present invention is intended to have the integrated circuit comb capacitor of electrode for capacitors, and this electrode for capacitors contacts with via hole with other interconnection that forms in identical metal line level and compares, and has the spacing that reduces between the neighboring capacitors electrode.An additional nonessential photomask has formed integrated circuit comb capacitor by using at the most in the present invention, and it is compared with the integrated circuit comb capacitor of prior art has higher capacitance density.
Because previous reasons at least, the present invention has improved integrated circuit comb capacitor.
Description of drawings
Utilize the characteristic in the claims to set forth feature of the present invention and elements characteristic.Accompanying drawing only is used for illustration purpose and does not draw in proportion.In addition, similar in the accompanying drawings label is represented similar feature.Yet the present invention's institutional framework itself and method of operation can be understood by describing better with reference to back details in conjunction with the accompanying drawings, wherein:
Fig. 1 shows prior art integrated circuit comb capacitor 150.
Fig. 2 a-2e shows the formation according to the integrated circuit comb capacitor 250 of the first embodiment of the present invention.
Fig. 3 shows the VPP capacitor according to the first embodiment of the present invention.
Fig. 4 shows the modification of the VPP capacitor among Fig. 3.
Fig. 5 a-5e shows the formation of integrated circuit comb capacitor 550 according to a second embodiment of the present invention.
Fig. 6 a-6e shows the formation of the integrated circuit comb capacitor 250 of a third embodiment in accordance with the invention.
Embodiment
Now by the present invention is described with reference to the drawings.In the drawings, describe and schematically show the various aspects of structure more clearly to describe and to illustrate the present invention in simple mode.
Through summary and introduction, the present invention is intended to have the integrated circuit comb capacitor of electrode for capacitors, and this electrode for capacitors is compared with other interconnection that forms in identical metal line level and via hole contact has the spacing that reduces between the neighboring capacitors electrode.All embodiment of the present invention comprise the formation of capacitor openings and revise medium along the surface of capacitor openings so that this modification causes capacitor to have the capacitance density of increase.
Describe the first embodiment of the present invention with reference to figure 2a-2e, this embodiment has described the formation of an improved capacitor, the improved integrated circuit comb capacitor 250 of more specifically saying so.Generally first embodiment is described as forming modification medium 204, removes along the modification medium on the surface of capacitor openings 220, and fill capacitor openings 220 with conductor material 112 along the surface of the capacitor openings 220 that in low k dielectric 102, forms.To with reference to figure 2a-2e first embodiment be described more specifically respectively below.
Fig. 2 a shows the formation of singly inlaying noncapacitive device opening 210, and it forms the wiring of noncapacitive device in low k dielectric 102.Preferably, low k dielectric 102 comprises a kind of among SiCOH or the porous SiC OH.Although do not illustrate, can in low k dielectric 102, form dual damascene noncapacitive device opening 210 equally.Dual damascene noncapacitive device opening 210 comprises interconnection and via hole part.
Fig. 2 b shows the formation of singly inlaying capacitor openings 220 in low k dielectric 102, stops mask 222 protection noncapacitive device openings 210 simultaneously.Identical with noncapacitive device opening 210, singly inlay capacitor openings 220 although in Fig. 2 b, illustrated, also can in low k dielectric 102, form dual damascene capacitor openings 220.Dual damascene capacitor openings 220 comprises interconnection and via hole part.Form noncapacitive device opening 210 and capacitor openings 220 by conventional photomask and etching step.Though Fig. 2 a-2b shows and form noncapacitive device opening 210 and capacitor openings 220 in two step, can form noncapacitive device opening 210 and capacitor openings 220 with identical photomask in a step.
Fig. 2 c shows the surface modified low k dielectric 102 along capacitor openings 220.More particularly, the surface along capacitor openings 220 forms chemistry and/or physically modifying medium 204.By consume carbon and oxidation surplus material possibly from the surface of capacitor openings 220, form and revise medium 204.Usually, at room temperature, in the reactive ion etching instrument, utilize as O
2, N
2O or H
2The oxidation plasma of O or as N
2/ H
2Or H
2The activation of reduction plasma, consume the carbon of wafer.By the oxidation surplus material, in oxidation plasma, take place further to revise.By revising, revise medium 204 and cause porous class SiO
2Material.Low k dielectric 102 can have less than or approximate 3.0 dielectric constant, have dielectric constant and revise medium 204 greater than 4.0.Though revise the characteristic that medium 204 has high dielectric constant, this helps from the angle that increases capacitance density, and this material also has poor dielectric breakdown, and high electricity leaks and high water absorbs, and this angle from Performance And Reliability is unfavorable for.Therefore, shown in Fig. 2 d, selectivity is removed and is revised medium 204.
Fig. 2 d shows from the surface selectivity of capacitor openings and removes modification medium 204.Removed and stopped mask 222, therefore noncapacitive device opening has been exposed to etch process.As diluted hydrofluoric acid (DHF) for example 100: 1H
2Etching to modification medium 204 in the typical solution of O: HF is faster than the etching of low k dielectric 102.Different etch-rates causes the capacitor openings 220 revised darker and wideer, reduces in the spacing between the neighboring capacitors opening 220 and reduces in the bottom of wire level and the vertical interval between any conductor in the substrate so that contact with other interconnection in the same metal wire level and via hole to compare.As discussed above, the electric capacity of integrated circuit comb capacitor 250 increases along with the modification degree of depth of the electrode for capacitors 250a that reduces the spacing between the electrode for capacitors 250a and width.After removing modification medium 204, integrated circuit comb capacitor 250 will be metallized, leveling and covering.Final integrated circuit comb capacitor 250 has been shown in Fig. 2 e.
Fig. 2 e shows the capacitor of the first embodiment of the present invention, the capacitor that promptly has the electrode for capacitors 250a that deepens and widen, so that contact with via hole with other interconnection 160 in the same metal wire level and to compare, reduced the spacing between the neighboring capacitors electrode 250a.Conductor material 112, promptly copper is filled capacitor openings 220 and the noncapacitive device opening 210 revised.After this, leveling and cover 242 electrode for capacitors 250a and the interconnection 160.
Fig. 3 shows according to the VPP capacitor in the first embodiment of the present invention shown in Fig. 2 a-2e.As mentioned above, the VPP capacitor comprises the multistage lamination of integrated circuit comb capacitor 250.In Fig. 3, form each integrated circuit comb capacitor 350 of multistage lamination according to the first embodiment of the present invention.Fig. 2 a-2e shows and singly inlays capacitor, and Fig. 3 shows the dual damascene capacitor.Dual damascene capacitor shown in Figure 3 comprises interconnection and the via hole part that forms according to the first embodiment of the present invention.Therefore, deepen and widen electrode for capacitors 250a, compare, reduced the spacing between the neighboring capacitors electrode 250a so that contact with via hole with other interconnection in the same metal wire level.Though do not illustrate among Fig. 3, the VPP capacitor can also comprise singly inlays the integrated circuit comb capacitor lamination.
Fig. 4 shows the revision of the VPP capacitor of Fig. 3.The difference of the VPP capacitor of Fig. 4 and the VPP capacitor of Fig. 3 is removing modification medium 204 back (not shown), but before deposited conductor material 112, has carried out other step.More particularly, use the hard mask 424 of etching or chemico-mechanical polishing (CMP) to have the VPP capacitor that protrudes shape 450 with formation.As shown in Figure 4, protrude shape and make the VPP capacitor between neighboring capacitors electrode 250a, have minimum spacing, with relative at the top of the electrode for capacitors 250a shown in Fig. 2 e and 3 in the midpoint of electrode for capacitors 250a.Minimum spacing is at the mid point of neighboring capacitors electrode 250a, and is relative with the top of neighboring capacitors electrode 250a, is favourable from the angle of reliability, arrive with the degree that the leakage paths that technology causes takes place at the interface of coating 242.
Fig. 5 a-5e shows the formation of integrated circuit comb capacitor 550 according to a second embodiment of the present invention.Different with first embodiment is in a second embodiment, not remove along the modification medium 204 on the surface of capacitor openings 220, but inject high K medium 506.Below by more specifically describing second embodiment with reference to figure 5a-5e respectively.
Fig. 5 a shows the low k dielectric 102 of deposition on coating 242.Be pre-existing in electrode for capacitors 550a 242 times at coating.
Fig. 5 b shows the modification low k dielectric.This is revised and forms porous material 204.Be similar to the first embodiment of the present invention, the second embodiment of the present invention forms porous material 204, yet what be different from the first embodiment of the present invention is that in the second embodiment of the present invention, porous material 204 is not limited to the surface of capacitor openings 220.
Fig. 5 c shows the formation of noncapacitive device opening 210 and capacitor openings 220 in revising medium 204.Although in Fig. 5 c, in a step, form noncapacitive device opening 210 and capacitor openings 220 with identical photomask.Noncapacitive device opening 210 and capacitor openings 220 can also be formed, as formerly describing with reference to figure 2a-2b in two steps.Dual damascene capacitor openings 220 has been shown in Fig. 5 c.Therefore, capacitor openings 220 comprises interconnection and via hole part.
Fig. 5 d shows along the surface modified of capacitor openings 220 and revises medium 204.Once more, with stopping mask 222 protection noncapacitive device openings 222.As mentioned above, what be different from the first embodiment of the present invention is not remove in the second embodiment of the present invention and revise medium 204, but inject high K medium 506.High K medium 506 has than revising the higher dielectric constant of medium 204.
Fig. 5 e shows the capacitor openings 220 of filling noncapacitive device opening 210 and revising with conductor material 112.
Fig. 6 a-6e shows the formation of the integrated circuit comb capacitor 650 of a third embodiment in accordance with the invention.Be similar to the second embodiment of the present invention, in the third embodiment of the present invention, do not remove, but inject high K medium 506 along the modification medium 204 on the surface of capacitor openings 220.What be different from the second embodiment of the present invention is in the third embodiment of the present invention, to form after filling noncapacitive device opening 210 and capacitor openings 220 with conductor material 112 and revise medium 204.With reference to figure 6a-6e the 3rd embodiment is described more specifically respectively below.
Fig. 6 a shows the low k dielectric 102 of deposition on coating 242.Below coating 242, be pre-existing in the electrode for capacitors 550a that forms according to a second embodiment of the present invention.
Fig. 6 b shows and form noncapacitive device opening 210 and capacitor openings 220 in low k dielectric 102.What be different from the second embodiment of the present invention is not revise low k dielectric 102 before forming noncapacitive device opening 210 and capacitor openings 220.
Fig. 6 c shows the medium 204 of modification along the surface of capacitor openings 220.This step of the third embodiment of the present invention is similar to the step shown in Fig. 2 c of the first embodiment of the present invention.In the of the present invention second and the 3rd embodiment, all use to stop the noncapacitive device opening of mask 222 protections in low k dielectric 102, and make amendment along the surface of capacitor openings 220.This is revised along the surface of capacitor openings 220 and forms porous material 204.Be different from first embodiment, but be similar to second embodiment, in the 3rd embodiment, do not remove and revise medium 204.
Fig. 6 d shows the modification medium 204 of modification along the surface of capacitor openings 220.Once more, with stopping mask 222 protection noncapacitive device openings 210.As mentioned above, what be different from first embodiment is not remove to revise medium 204, but is similar to second embodiment, injects with high K medium 506 and revises medium 204.High K medium 506 has than revising the higher dielectric constant of medium 204.
Fig. 6 e shows the capacitor openings 220 of filling noncapacitive device opening 210 and revising with conductor material 112, and removes pore former (porogen) from low k dielectric 102.Be different from the second embodiment of the present invention, in the third embodiment of the present invention, remove pore former from low k dielectric 102 at noncapacitive device opening 210 and capacitor openings 220 formation backs.
Though specifically described the present invention in conjunction with detailed preferred embodiment and other alternative embodiment, should be understood that those skilled in the art can carry out many replacements, modification and change according to the narration of front.Therefore being intended to claims comprises all such replacements, modification and the change that falls into true scope of the present invention and spirit.
Claims (44)
1. a method that is used to form capacitor comprises the steps:
Form at least two capacitor openings and at least one noncapacitive device opening in medium, described capacitor forms in identical metal line level with noncapacitive device opening; And,
Modification is along the described medium on the surface of at least one capacitor openings in described at least two capacitor openings, so that described modification increases the electric capacity of described capacitor.
2. according to the process of claim 1 wherein that described modify steps comprises:
Consume carbon by described surface, revise medium along the described surface formation of described at least one capacitor openings from described at least one capacitor openings.
3. according to the method for claim 2, wherein said modify steps also comprises the steps:
Carry out described at least one capacitor openings of following steps expansion by selectivity:
Modification is along the described modification medium on the described surface of described at least one capacitor openings;
Remove along the described modification medium on the described surface of described at least one capacitor openings; And
Fill described capacitor openings with conductor material.
4. according to the process of claim 1 wherein that described medium is a porous, in described modification medium, form described at least one capacitor openings and described at least one noncapacitive device opening, and described modify steps comprises the steps:
The material that was higher than the described dielectric constant of described modification medium with dielectric constant before revising injects described modification medium along the described surface of described capacitor openings.
5. according to the method for claim 2, wherein said modify steps also comprises the steps:
The material that was higher than the described dielectric constant of described modification medium with dielectric constant before revising injects described modification medium along the described surface of described capacitor openings.
6. according to the process of claim 1 wherein that described medium is a kind of among SiCOH and the porous SiC OH.
7. according to the method for claim 2, wherein said consumption step comprises the activation oxidation plasma, and described oxidation plasma is O
2, N
2O and H
2A kind of among the O.
8. according to the method for claim 2, wherein said consumption step comprises activation reduction plasma, and described reduction plasma is N
2/ H
2And H
2In a kind of.
9. according to the method for claim 2, wherein said medium has and is less than or equal to 3.0 dielectric constant, and described modification medium has the dielectric constant greater than 4.0.
10. according to the method for claim 3, wherein remove described modification medium along the described surface of described at least one capacitor openings with diluted hydrofluoric acid.
11. according to the method for claim 3, wherein said conductor material comprises copper.
12. according to the method for claim 4, wherein use PVD, CVD, the described modification medium of a kind of injection among IPVD and the ALD.
13. according to the method for claim 5, wherein use PVD, CVD, the described modification medium of a kind of injection among IPVD and the ALD.
14. according to the method for claim 5, wherein said material comprises a kind of in metal material and the insulating material.
15. a capacitor comprises:
A plurality of noncapacitive device openings form in medium, have prescribed distance between the arest neighbors noncapacitive device opening in each noncapacitive device opening and the same metal wire level;
A plurality of capacitor openings, form in the described medium in the described same metal wire level identical with described a plurality of noncapacitive device openings, the spacing between each capacitor openings and the arest neighbors capacitor openings is less than the described prescribed distance between arest neighbors noncapacitive device opening.
16. according to the capacitor of claim 15, the degree of depth of wherein said capacitor openings is greater than the degree of depth of the noncapacitive device opening that forms in described same metal wire level.
17. according to the capacitor of claim 15, the width of wherein said capacitor openings is greater than the width of the noncapacitive device opening that forms in described same metal wire level.
18. according to the capacitor of claim 15, wherein said medium is a kind of among SiCOH and the porous SiC OH.
19. according to the capacitor of claim 15, the minimum spacing of wherein said capacitor openings spacing between the arest neighbors capacitor openings appears at the top of described capacitor openings.
20. according to the capacitor of claim 15, the minimum spacing of wherein said capacitor openings spacing between the arest neighbors capacitor openings appears at the mid point of described capacitor openings.
21. according to the capacitor of claim 15, wherein said capacitor openings comprises interconnecting parts and via hole part.
22. according to the capacitor of claim 21, wherein said capacitor openings comprises at least one lamination of capacitor openings, described capacitor openings has interconnecting parts and is connected to the via hole part of another lamination of capacitor openings.
23. a method that is used to form capacitor comprises the steps:
The deposition low k dielectric;
Form a plurality of openings in described low k dielectric, at least one opening is that non-capacitor openings and at least two openings are capacitor openings;
Protect any noncapacitive device opening not revised by dielectric constant;
Surface along at least one capacitor openings in described at least two capacitor openings forms the porous zone;
By removing described modification medium, expand described at least one capacitor openings along the described surface selectivity of described at least one capacitor openings; And,
Fill the capacitor openings of described noncapacitive device opening and described expansion with conductor material.
24. according to the method for claim 23, wherein said low k dielectric is SiCOH.
25., wherein remove described modification medium along the described surface of described at least one capacitor openings with diluted hydrofluoric acid according to the method for claim 23.
26. according to the method for claim 23, wherein said formation step comprises the described surface consumption carbon from described at least one capacitor openings.
27. according to the method for claim 26, wherein said consumption step comprises the activation oxidation plasma, described oxidation plasma is O
2, N
2O and H
2A kind of among the O.
28. according to the method for claim 26, wherein said consumption step comprises activation reduction plasma, described reduction plasma is N
2/ H
2And H
2In a kind of.
29. a method that is used to form capacitor comprises the steps:
Deposition comprises the low k dielectric of dielectric matrix and pore former;
Remove described pore former from described low k dielectric;
Form a plurality of openings in described porous media, at least one opening is that non-capacitor openings and at least two openings are capacitor openings;
Protect any noncapacitive device opening not revised by dielectric constant; And
Inject described porous media with a material along the surface of at least one capacitor openings in described at least two capacitor openings, the dielectric constant of described material is higher than the dielectric constant of described porous media before described injection.
30. according to the method for claim 29, the wherein said step of removing comprises:
Consume carbon from described low k dielectric.
31. according to the method for claim 29, wherein said low k dielectric comprises SiCOH.
32. according to the method for claim 29, wherein said low k dielectric has the dielectric constant less than 3.0, described porous media has the dielectric constant between 4.0 and 5.0.
33. according to the method for claim 29, wherein use PVD, CVD, the described porous media of a kind of injection among IPVD and the ALD.
34. according to the method for claim 29, wherein said material comprises a kind of in metal material and the insulating material.
35. according to the method for claim 30, wherein said consumption step comprises the activation oxidation plasma, described oxidation plasma is O
2, N
2O and H
2A kind of among the O.
36. according to the method for claim 30, wherein said consumption step comprises activation reduction plasma, described reduction plasma is N
2/ H
2And H
2In a kind of.
37. a method that is used to form capacitor comprises the steps:
Deposition comprises the low k dielectric of pore former;
Form a plurality of openings in described porous media, at least one opening is that non-capacitor openings and at least two openings are capacitor openings;
Protect any noncapacitive device opening not fluctuateed by dielectric constant; And
Inject described porous media with a material along the surface of at least one capacitor openings in described at least two capacitor openings, the dielectric constant of described material is higher than the dielectric constant of described porous media before described injection;
Fill described noncapacitive device opening and capacitor openings with conductor material; And,
Remove pore former from described low k dielectric.
38. according to the method for claim 37, the wherein said step of removing comprises:
Consume carbon from described low k dielectric.
39. according to the method for claim 37, wherein said low k dielectric comprises SiCOH.
40. according to the method for claim 37, wherein use PVD, CVD, the described porous media of a kind of injection among IPVD and the ALD.
41. according to the method for claim 37, wherein said low k dielectric has the dielectric constant less than 3.0, described porous media has the dielectric constant between 4.0 and 5.0.
42. according to the method for claim 37, wherein said material comprises a kind of in metal material and the insulating material.
43. according to the method for claim 38, wherein said consumption step comprises the activation oxidation plasma, described oxidation plasma is O
2, N
2O and H
2A kind of among the O.
44. according to the method for claim 38, wherein said consumption step comprises activation reduction plasma, described reduction plasma is N
2/ H
2And H
2In a kind of.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/306,746 US7585722B2 (en) | 2006-01-10 | 2006-01-10 | Integrated circuit comb capacitor |
| US11/306,746 | 2006-01-10 |
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| CN100479132C true CN100479132C (en) | 2009-04-15 |
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| JP5154744B2 (en) * | 2005-07-14 | 2013-02-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US7402883B2 (en) * | 2006-04-25 | 2008-07-22 | International Business Machines Corporation, Inc. | Back end of the line structures with liner and noble metal layer |
| US7456463B2 (en) * | 2007-02-06 | 2008-11-25 | International Business Machines Corporation | Capacitor having electrodes at different depths to reduce parasitic capacitance |
| US7759242B2 (en) | 2007-08-22 | 2010-07-20 | Qimonda Ag | Method of fabricating an integrated circuit |
| JP2009194072A (en) * | 2008-02-13 | 2009-08-27 | Toshiba Corp | Method of manufacturing semiconductor device |
| US8716778B2 (en) * | 2008-11-17 | 2014-05-06 | Altera Corporation | Metal-insulator-metal capacitors |
| US7745324B1 (en) | 2009-01-09 | 2010-06-29 | International Business Machines Corporation | Interconnect with recessed dielectric adjacent a noble metal cap |
| US8298902B2 (en) * | 2009-03-18 | 2012-10-30 | International Business Machines Corporation | Interconnect structures, methods for fabricating interconnect structures, and design structures for a radiofrequency integrated circuit |
| JP2011009581A (en) * | 2009-06-26 | 2011-01-13 | Renesas Electronics Corp | Process of producing semiconductor device and the semiconductor device |
| JP2011142724A (en) * | 2010-01-06 | 2011-07-21 | Hitachi Ltd | Noncontact power transmission device and near field antenna for same |
| US9070686B2 (en) * | 2011-05-31 | 2015-06-30 | International Business Machines Corporation | Wiring switch designs based on a field effect device for reconfigurable interconnect paths |
| FR2994019B1 (en) * | 2012-07-25 | 2016-05-06 | Commissariat Energie Atomique | METHOD FOR PROVIDING A CAPACITY |
| US8916461B2 (en) * | 2012-09-20 | 2014-12-23 | International Business Machines Corporation | Electronic fuse vias in interconnect structures |
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| US8901710B2 (en) * | 2013-02-27 | 2014-12-02 | International Business Machines Corporation | Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance |
| US9059305B2 (en) | 2013-03-04 | 2015-06-16 | International Business Machines Corporation | Planar qubits having increased coherence times |
| JP6197381B2 (en) * | 2013-06-05 | 2017-09-20 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| CN104319098B (en) * | 2014-09-17 | 2017-04-05 | 中国科学院物理研究所 | The preparation method of interdigital capacitor and the method for forming adjacent evaporation pattern |
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| US6426304B1 (en) * | 2000-06-30 | 2002-07-30 | Lam Research Corporation | Post etch photoresist strip with hydrogen for organosilicate glass low-κ etch applications |
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| US6656785B2 (en) * | 2001-10-15 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co. Ltd | MIM process for logic-based embedded RAM |
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| CN101000890A (en) | 2007-07-18 |
| US8120143B2 (en) | 2012-02-21 |
| US20080130200A1 (en) | 2008-06-05 |
| US20070158717A1 (en) | 2007-07-12 |
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