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CN100474581C - Bridging multi-chip packaging structure - Google Patents

Bridging multi-chip packaging structure Download PDF

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CN100474581C
CN100474581C CN 03156270 CN03156270A CN100474581C CN 100474581 C CN100474581 C CN 100474581C CN 03156270 CN03156270 CN 03156270 CN 03156270 A CN03156270 A CN 03156270A CN 100474581 C CN100474581 C CN 100474581C
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bridging
multi
chip
packaging
structure
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CN 03156270
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Chinese (zh)
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CN1591862A (en )
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洪志斌
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日月光半导体制造股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

一种桥接型式的多芯片封装构造主要包括一载板、一第一芯片、一第二芯片及至少一导电凸块。 Construct a multi-chip package includes a bridge type carrier, a first chip, a second chip and at least one conductive bump. 该载板具有一上表面及对应的一下表面,多个载板接点,位在载板的上表面。 Said carrier plate having an upper surface and a lower surface of the corresponding plurality of carrier contacts located in the upper surface of the carrier plate. 第一芯片具有一第一主动表面,该第一芯片还具有至少一第一接点,配置在第一芯片的第一主动表面上。 A first chip having a first active surface, the first chip further having at least a first contact disposed on a first surface of the first chip is active. 同样地,第二芯片具有一第二主动表面,该第二芯片还具有至少一第二接点,配置在第二芯片的第二主动表面上。 Likewise, the second chip having a second active surface, the second chip further having at least one second contact disposed on a second active surface of the second chip. 第一芯片的第一侧壁紧邻第二芯片的第二侧壁,且第一芯片的第一主动表面与第二芯片的第二主动表面为共平面的配置。 A first sidewall of the first chip proximate the second sidewall of the second chip, and the first active surface and second active surface of the second chip to the first chip is coplanar configuration. 导电凸块在第一芯片的第一主动表面上及第二芯片的第二主动表面上延伸,使第一芯片的第一接点与第二芯片的第二接点电性连接。 And a conductive bump extending over a second active surface of the second chip on a first active surface of the first chip, the first chip of the first contact point is electrically connected to the second of the second chip.

Description

桥接形式的多芯片封装构造技术领域本发明涉及一种多芯片封装构造,特别涉及一种桥接形式的多芯片封装构造。 BACKGROUND multi-chip package structure of the present invention relates to a bridge in the form of a multi-chip package structure, and particularly relates to multi-chip packages to construct a bridge form. 背景技术近年来,随着电子技术的日新月异,高科技电子产品也相继问世, 因而更人性化、功能性更佳的电子产品不断推陈出新,然而各种产品无不朝向轻、薄、短、小的趋势设计,以提供更便利舒适的使用。 In recent years, with the ever-changing electronic technology, high-tech electronic products have also come out, and therefore more humane, functional electronic products better their quality, but a variety of products are all facing the light, thin, short, small trend designed to provide a more convenient and comfortable to use. 而一个电子产品的完成,电子封装扮演着重要的角色,其芯片间电性连接的方式, 一般常见的有两种,第一种为引线键合(wire-bonding)的方式、第二种为倒装芯片(flip chip)的方式。 And a complete electronic products, electronic packaging plays an important role in its inter-chip electrically connected, generally there are two common, first as wire bonding (wire-bonding) the way, for the second flip chip (flip chip) approach. 就引线键合的方式而言,其利用一引线键合机台将其引线键合头先移动至芯片的接点上,并利用尖端放电的方式将导电线的端点熔化而成为球型的样式,如此便可以将导电线打到芯片的接点上,然后便移动引线键合头到另一芯片的接点上,而在移动的过程中,引线键合头亦会放出导电线,最后再利用超音波熔接的方式将导电线打到另一芯片的接点上。 Manner to wire bonding, the wire bonding which utilizes a machine to wire bonding head is moved to the first contacts on the chip, and use patterns of the end point discharge conductive wire is melted to become spherical style, thus it can be hit conductive lines on the chip contacts, and wire bond head is moved to another chip contacts, and the process of moving the wire bonding head will release conductive lines, and finally use of ultrasound welding the conductive wire manner hit another chip contacts. 接下来,将介绍一种已知利用引线键合方式的多芯片封装结构。 Next, the structure for a multichip package introduced using known wire bonding method. 请参照图1,其图示已知利用引线键合方式的多芯片封装结构的剖面示意图。 Referring to FIG 1, which illustrates a schematic diagram of a known cross-sectional configuration of a multi-chip package using a wire bonding method. 该封装结构包括一载板10、 一第一芯片12、 一第二芯片14、多条导电线160、 162、 164、 一封装材料18及多个焊球19。 The package structure comprises a carrier plate 10, a first chip 12, a second chip 14, a plurality of conductive lines 160, 162, 164, a plurality of solder balls 18 and the encapsulating material 19. 载板10具有一上表面102及对应的下表面104,而载板IO具有多个载板接点106 及第一芯片座105与第二芯片座109,载板接点106及第一芯片座105 与第二芯片座109位在载板10的上表面102上,并且载板接点106环绕在第一芯片座105与第二芯片座109的周围,而载板接点107位在载板10的下表面104上。 The lower carrier plate 10 having an upper surface 104 and the corresponding surface 102, the carrier plate having a plurality of carrier contacts IO 106 and the first die holder 105 and the second die pad 109, the contact carrier plate 106 and the first die holder 105 the second die pad 109 on the upper surface 102 of the carrier plate 10, and the contact carrier plate 106 surround the die pad 105 of the first and second die pad 109, the contact carrier plate 107 and the lower surface of the carrier plate 10 104 on. 第一芯片12具有一主动表面122及对应的第一背面124,而第一芯片12还具有多个第一芯片接点126,位在第一芯片12的主动表面122上。 The first chip 12 has an active surface 122 and the corresponding first back surface 124 and the first die 12 further having a first plurality of chip contacts 126, bit 122 on the active surface 12 of the first chip. 第一芯片12以其第一背面124并通过一黏着材料(未标示于图中)贴附到载板10的芯片座108上,而利用引线键合的方式使第一芯片12与载板10电性连接,其中导电线160的一端接合到第一芯片接点126上,而导电线160的另一端接合到载板接点106上。 The first chip 124 and the back surface 12 thereof through a first adhesive material (not shown in the figure) is attached to the die pad 108 of the carrier plate 10, and the use of the lead bonding the first chip 12 and the carrier 10 electrically connecting one end of the conductive wire 160 is bonded to contacts 126 on the first chip, the other end of the conductive wire 160 is bonded to the carrier board contacts 106. 同样地,第二芯片14具有一第二主动表面142及对应的第二背面144,而第二芯片14还具有多个第二芯片接点146,位在第二芯片14的第二主动表面142上。 Likewise, the second chip 14 has a second back surface 142 and the corresponding second active surface 144, a second chip 14 and second chip further having a plurality of contacts 146, 142 located in the second active surface of the second chip 14 . 第二芯片14以其第二背面144并通过一黏着材料(未标示于图中)贴附到载板10的芯片座109上,而利用引线键合的方式使第二芯片14与载板10电性连接,其中导电线162 的一端接合到第二芯片接点146上,而导电线162的另一端接合到载板接点108上。 The second chip 144 and the back surface 14 thereof through a second adhesive material (not shown in the figure) is attached to the die pad 109 of the carrier plate 10, the embodiment using the second wire bond chip 14 and the carrier 10 electrically connecting one end of the conductive wire 162 is bonded to the second chip contacts 146, 162 while the other end of the conductive wire is bonded to the carrier board contacts 108. 此外,第一芯片12与第二芯片14通过导电线164电性导通。 Further, the first chip and the second chip 12 14164 electrically conductive via a conductive line. 另外,封装材料18包覆第一芯片12、第二芯片14、载板10 的上表面102及导电线160、 162及164。 Further, the encapsulating material 18 covers the first chip 12, the second chip 14, the upper surface 10 of the carrier plate 102 and the conductive lines 160, 162 and 164. 在上述的封装结构中,第一芯片12通过导线164与第二芯片14 电性连接,然而由于导线164的截面积甚小并且长度甚长,因此特性阻抗匹配不良,使得讯号会被快速地衰减,并且在高频电路运作时, 会有电感电容寄生效应(Parasitics)的发生,以致产生讯号反射的情形。 In the package, the first chip 12 is connected via a wire 164 and a second chip 14 electrically, but since the cross-sectional area of ​​the wire 164 is very small and the length very long, so impedance characteristics poor, such that the signal is rapidly attenuated , and the case of operating at a high frequency circuit, there is inductance and capacitance parasitics (parasitics) occurs, so as to produce signal reflections. 此外,由于导线164与第一芯片接点传输路径的面积甚小,不利于电压及电流提供,导致电源及接地的效果变差。 Further, since the contact area of ​​the wire 164 and the first transmission path is very small chip, is not conducive to providing voltage and current, resulting in poor power and ground effects. 有鉴于此,为避免前述多芯片封装构造的缺点,以提升多芯片封装构造的芯片效能,实为一重要的课题。 In view of this, in order to avoid the disadvantages of the multi-chip package structure, a chip to improve performance of multi-chip package structure, in fact, a significant problem. 发明内容有鉴于上述课题,本发明的目的提供一种多芯片封装结构,以桥接型式的导电材料取代导电线,如此可縮短芯片间电性连接的距离, 使得多芯片封装结构的电性效能可以提高。 SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention to provide a multi-chip package structure, a conductive material bridge type substituted conductive lines, thus can shorten the distance between the chip is electrically connected, so that electrical performance multichip package structure can be improve.

由此,为了达成上述目的,本发明提出一种芯片封装结构,至少包括一载板、 一第一芯片、 一第二芯片及至少一导电凸块及多个焊球。 Thus, in order to achieve the above object, the present invention provides a chip package structure, comprising at least a carrier, a first chip, a second chip and at least one conductive bump and a plurality of solder balls. 载板具有一上表面及对应的下表面,载板还具至少一载板接点,均位在载板的上表面。 The carrier plate having an upper surface and a corresponding lower surface, the carrier plate further having at least one carrier contacts are located in the upper surface of the carrier plate. 第一芯片具有一第一主动表面,第一芯片还具有至少一第一芯片接点,配置在第一芯片的第一主动表面上。 A first chip having a first active surface, at least a first chip having a first chip further contacts disposed on a first surface of the first chip is active. 同样地,第二芯片具有一第二主动表面,第二芯片还具有至少一第二芯片接点, 配置在第二芯片的第二主动表面上。 Likewise, the second chip having a second active surface, the second chip further having at least one second chip contacts disposed on the second active surface of the second chip. 其中,第一芯片及第二芯片以引线键合方式配置于载板上,并与载板电性连接。 Wherein the first chip to the second chip and wire bonding is disposed on the carrier board and electrically connected to the carrier plate. 此外,第一芯片的至少一第一侧壁紧邻第二芯片的第二侧壁,并且第一芯片的第一主动表面与第二芯片的第二主动表面为共平面的配置。 Further, at least a first sidewall of the first chip proximate the second sidewall of the second chip, and the first active surface and second active surface of the second chip to the first chip is coplanar configuration. 导电凸块在第一芯片的第一主动表面上及第二芯片的第二表面上延伸,使第一芯片的第一接点与第二芯片的第二接点电性连接。 And a conductive bump extending on a second surface of the chip on the first active surface of the first chip, the first chip of the first contact point is electrically connected to the second of the second chip. 承上所述,其中芯片封装结构还包括一封装材料,包覆第一芯片及第二芯片、载板的上表面及导电凸块。 The bearing, wherein the chip package structure further includes a packaging material, covering the first chip and the second chip, on the surface of the carrier plate and the conductive bumps. 第一芯片接点及第二芯片接点分别位在第一芯片及第二芯片的边缘上,且紧邻配置。 The first chip and the second chip contacts contacts respectively located on the edge of the first chip and the second chip, and arranged in close proximity. 此外,导电凸块可以是锡铅合金、无铅导电材料或导电胶。 In addition, the conductive bumps may be a tin-lead alloy, lead-free conductive material or conductive paste. 综上所述,本发明的多芯片封装结构,由于芯片间的接点可以透过导电凸块电性连接,因此芯片接点间的传导路径甚短,且传导路径的径宽甚大,故可以降低传导阻抗,而减缓讯号的衰减,并且可以适于在高频电路的运作,而减少电感电容寄生效应的发生。 In summary, a multi-chip packaging structure of the present invention, since the contact between the chip may be electrically connected through the conductive bumps, and therefore the conduction path between the chip contacts is very short, and the width of the conduction path of very large diameter, it is possible to reduce conduction impedance, attenuation of the signal is slowed, and may be adapted to high frequency operation of the circuit, and reduce the parasitic inductance and capacitance effects. 另外,由于导电凸块与芯片接点接触的面积甚大,且载板接点可以直接与芯片接点接触,故可以避免发生如引线键合结构的阻抗不匹配的现象,并且会有甚佳的电源及接地效果。 Further, since the area of ​​the conductive bump in contact with the chip contacts is very large, and the contact carrier may be in direct contact with the chip contacts, so that phenomena such as the wire bonding structure of the impedance mismatch can be avoided, and there will be a very good power and ground effect. 以下将参照相关附图,说明依本发明较佳实施例的桥接形式的多芯片封装构造。 Below with reference to the related drawings, a multi-chip package structure of the preferred embodiment in the form of a bridge under this embodiment of the invention. 附图说明 BRIEF DESCRIPTION

图l为一示意图,显示已知多芯片封装构造。 Figure l is a schematic diagram showing a known multi-chip package structure. 图2为一示意图,显示本发明第一较佳实施例中的桥接形式的多芯片封装结构。 Figure 2 is a schematic diagram showing a bridge in the form of a first preferred embodiment of the present invention, a multi-chip package. 图3为一示意图,显示本发明第二较佳实施例中的桥接形式的多芯片封装结构。 3 is a schematic diagram showing a bridge in the form of a second preferred embodiment of the present invention, a multi-chip package. 图4为一示意图,显示本发明第三较佳实施例中的桥接形式的多芯片封装结构。 FIG 4 is a schematic diagram showing a bridge in the form of a third preferred embodiment of the present invention, a multi-chip package. 图5为一示意图,显示本发明第四较佳实施例中的桥接形式的多芯片封装结构。 FIG 5 is a schematic diagram showing a bridge in the form of a fourth preferred embodiment of the present invention, a multi-chip package. 图6为一示意图,显示本发明第五较佳实施例中的桥接形式的多芯片封装结构。 FIG 6 is a schematic diagram showing a bridge in the form of a fifth preferred embodiment of the present invention, a multi-chip package. 图7至图9为一示意图,显示本发明第四较佳实施例的一种桥接形式的多芯片封装结构制程的剖面示意图。 7 to FIG. 9 is a schematic cross-sectional view of one kind of bridge form a fourth preferred embodiment of the present invention is a multi-chip packaging structure of the display process. 图中符号说明 10 载板102 载板上表面104 载板下表面105 第一芯片座106、 108 载板接点107 导电组件(焊球)109 第二芯片座12 第一芯片122 第一主动面124 第一背面126 第一芯片接点14 第—心片142 第二主动表面144 第二背面146 第二芯片接点160、 162、 164 导电线18 封胶体20 载板201 开口202 载板上表面203 周壁204 载板下表面206、 208 载板接点207 导电组件(焊球)21 散热片22 第一心片221 第一侧壁222 第一主动面223 第三侧壁224 第一背面226、 228 第一芯片接点24 第一心片241 第二側壁242 第二主动表面243 第四侧壁244 第二背面246、 248 第二芯片接点254 屏蔽层256 开口258 焊料259 导电凸块260、 262 导电线264 导电凸块268 导电凸块28 封胶体29 填充体292 填充体上表面具体实施方式图2揭示一种本发明第一较佳实施例的桥接形式的多芯片封装构造,其主要包括一载板20、 一第一芯片22、 一第 DESCRIPTION OF REFERENCE NUMERALS 122 first surface 105 of the first active surface of the chip carrier 106, the carrier plate 108 under the carrier plate 10 the carrier plate 102 contacts surface 104 of carrier plate 107 conductive elements (balls) 10 912 second die pad of the first chip 124 in FIG. a first back surface 126 of the first chip contacts 14 - Tablet 142 144 146 The second surface of a second active chip 160 contacts a second rear surface 162, the conductive line 164 carrier 18 20 201 colloidal carrier plate opening 203 may be surface 202 of the peripheral wall 204 the lower surface of the carrier 206, the carrier plate 208 contacts the conductive assembly 207 (solder balls) 21 of the first fin 224 back surface 221 of the first side wall 22 of the first core sheet 223 of the third side wall 222 of the first active surfaces 226, 228 of the first chip a first core sheet 24 contacts the second side wall 242 244 241 243 second rear sidewall of the second active surface 246 of the fourth, the second chip 248 contacts the shield 256 254 259 260 an opening 258 of the solder, conductive lines 262 of conductive bumps 264 conductive bump block 268 colloidal conductive bumps 28 29 DETAILED DESCRIPTION FIG surface filler 292 is filled body 2 discloses a multi-chip package structure of the first bridge in the form of a preferred embodiment of the present invention, which mainly comprises a carrier 20, a The first chip 22, a first 芯片24及一导电凸块264。 A chip 24 and conductive bump 264. 该载板20具有一上表面202及对应的一下表面204,多个载板接点206、 208,均位在载板20的上表面。 The carrier plate 20 has a lower surface 204 and a corresponding upper surface 202, a plurality of carrier contacts 206, 208 are located in the upper surface 20 of the carrier plate. 第一芯片22具有一第一主动表面222,该第一芯片22还具有至少一第一接点226,配置在第一芯片22的第一主动表面222上。 The first chip 22 has a first active surface 222, the first chip 22 further has at least a first contact 226, arranged on a first active surface 222 of the first chip 22. 同样地,第二芯片24具有一第二主动表面242,该第二芯片24还具有至少一第二接点246,配置在第二芯片24的第二主动表面242上。 Likewise, the second chip 24 has a second active surface 242, the second chip 24 also has at least one second contact 246, arranged on a second active surface 242 of the second chip 24. 其中,第一芯片22以其背面(第一背面224)并通过一黏着材料(如银胶)设置于载板20上;同样地,第二芯片24以其背面(第二背面224)并通过一黏着材料(如银胶)设置于载板20上。 Wherein the first chip 22 with its back surface (a first back surface 224) by an adhesive material (e.g., silver paste) 20 is provided in the carrier plate; Likewise, the second chip 24 with its back surface (second back surface 224) and by an adhesive material (e.g., silver paste) on the carrier plate 20 is provided. 导电线260电性连接第一芯片22的第一接点226与载板20的载板接点206,而导电线262电性连接第二芯片24的第二接点246 与载板20的载板接点208。 Electrically conductive wires 260 connecting the first chip 22 and the carrier plate 226 first contacts 20 of the contact carrier plate 206, while conductive lines 262 are electrically connected to the second contact point 246 of the second chip 24 and the carrier plate 20 contacts the carrier 208 . 此外,第一芯片22的第一侧壁221紧邻第二芯片24的第二侧壁241 ,且第一芯片22的第一主动表面222与第二芯片24的第二主动表面242为共平面的配置,再者,第一芯片接点226及第二芯片接点246 分别位在第一芯片22及第二芯片24的边缘上,且紧邻配置。 Further, the first chip of a first sidewall proximate the second sidewall 22 122 24 of the second chip 241, and the first active surface 22 of the first chip 222 and the second active surface 242 of the second chip 24 is co-planar configuration, and further, the first chip and the second chip 226 contacts the contacts 246 are respectively located on the edge of the first chip 22 and the second chip 24, and is arranged in close proximity. 导电凸块264在第一芯片22的第一主动表面222上及第二芯片24的第二主动表面242上延伸,使第一芯片22的第一接点228与第二芯片24的第二接点248电性连接。 Conductive bumps 264 and 242 extending over a second active surface of the second chip 24 on a first active surface 222 of the first chip 22, so that the first contact of the second contact 22 of the first chip and the second chip 24 228 248 electrically connected. 承上所述,该多芯片封装结构还包括一封装材料280,包覆第一芯片22及第二芯片24、载板20的上表面202及导电凸块264。 The bearing, the multi-chip package structure 280 further comprises a packaging material, covering the first chip 22 and the second chip 24, the upper surface 20 of the carrier plate 202 and the conductive bump 264. 此外,上述的导电凸块264可以是锡铅合金、无铅导电材料或导电胶。 Further, the conductive bumps 264 may be a tin-lead alloy, lead-free conductive material or conductive paste. 如图3所示,本发明的第二较佳实施例的桥接形式的多芯片封装 As shown, the bridge forms a second preferred embodiment of the present invention, a multi-chip package 3

构造,当第一芯片22的第一侧边221与第二芯片24的第二侧边241 间具有一较大的空隙时,可先设置一填充体29,如不导电胶体。 Configuration, when the first side 221 of the first chip 22 having a larger gap and the second side 241 of the second chip 24, may be provided with a first filling body 29, as no conductive paste. 该填充体29的上表面与第一芯片22的第一主动表面222及第二芯片24的第二主动表面242共平面。 A second active surface 29 and the upper surface of the active surface of the first filling body 22 of the first chip and the second chip 24 222 242 coplanar. 接着,可以利用网板印刷的方式,形成一焊料到第一芯片接点226、第二芯片接点246及填充体的上表面292上, 其中焊料由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成,金属粒子均匀地混合在助焊剂中。 Next, using a screen printing can manner, forming a first solder to the chip contacts 226, 292 on an upper surface of the chip contacts 246 and the second filling body, wherein the solder flux by a (not shown) and a plurality of metal particles ( not shown) composed of the metal particles are uniformly mixed in the flux. 之后,便进行回焊的制程,使得金属粒子可以熔融聚合而固化形成导电凸块264到第一芯片接点226及第二芯片接点246上。 Thereafter, they perform the reflow process, so that the metal particles may be melt polymerization cured conductive bump 264 is formed on the first chip to the second chip contacts 226 and contacts 246. 其中第一芯片接点226及第二芯片接点246可通过导电凸块264相互电性连接,而导电凸块264比如是锡铅合金或是无铅导电材料。 Wherein the first chip and the second chip 226 contacts contacts 246 through 264 are electrically connected to the conductive bumps, the conductive bumps 264 such as a tin-lead alloy or lead-free conductive material. 接着,请参照图4,为本发明的第三较佳实施例的桥接形式的多芯片封装构造。 Next, referring to FIG 4, the bridge forms a third preferred embodiment of the present invention, a multi-chip package structure. 其中,载板20具有一开口201,第一芯片22及第二芯片24容置于该开口201中,而封胶体28包覆该载板20上表面202的部分、第一芯片22、第二芯片24及导电凸块264,并且使第一芯片22 及第二芯片24的背面外露的,以通过此进一步縮小整体封装构造的厚度。 Wherein, the carrier plate 20 has an opening 201, a first chip 22 and second chip 24 received in the opening 201, the cover portion 28 and the encapsulant surface 202 of the carrier plate 20, a first chip 22, the second chip 24 and conductive bumps 264, and the back surface 22 of the first chip and the second chip 24 is exposed, to further refine the overall thickness of the package through this configuration. 再者,承上所述,如图5所示,亦可设置一散热片21于载板20 下表面204,而第一芯片22及第二芯片24设置在散热片21上,如此更可提升封装体的散热效能,此为本发明的第四较佳实施例的桥接形式的多芯片封装构造。 Further, the above arrangements, as shown in FIG, 21 may also be provided with a fin 20 on the lower surface of the carrier plate 204, and the first chip 22 and the second chip 24 on the heat sink 21 is provided, can be improved even more so thermal performance of the package, in the form of a bridge to a fourth preferred embodiment of this embodiment of the present invention, a multi-chip package structure. 承上所述,请参照图6,为本发明的第五较佳实施例的桥接形式的多芯片封装构造。 Bridging a fifth preferred form of embodiment of the bearing, Referring to FIG 6, the present invention is a multi-chip package structure. 载板20亦具有一开口201,第一芯片22及第二芯片24同时容置于该开口201中,而该开口201的大小恰可容置第一芯片22及第二芯片24。 The carrier plate 20 also has an opening 201, a first chip 22 and second chip 24 at the same time received in the opening 201, which may be just the size of the opening 201 accommodating the first chip 22 and the second chip 24. 其中,第一芯片22具有一第三侧边223,第二芯片24具有一第四侧边243,开口20内具有一周壁203,该第一芯片22及第二芯片24的侧壁紧邻开口的周壁203,且第一芯片22的第一 Wherein the first chip 22 has a third side 223, a second chip 24 has a fourth side 243, the opening 20 has a peripheral wall 203, the side walls 22 of the first chip and the second chip 24 immediately adjacent the opening the peripheral wall 203, a first chip 22 and the first

主动表面222、第二芯片24的第二主动表面242与载板20的上表面202共平面配置。 Active surface 222, a second surface of the second active surface of chip 24 and the carrier 20 242 202 coplanar configuration. 接着,形成一第二导电凸块266以电性连接第一芯片22与载板20。 Subsequently, a second electrically conductive bump 266 is connected to the first chip 22 and the carrier 20 are formed. 同样地,另形成一第三导电凸块268以电性连接第二芯片24与载板20。 Similarly, the other forming a third conductive bump 268 is electrically connected to a second chip 24 and the carrier 20. 不论是上述何种实施例,皆可于载板的上表面或下表面另植接多个焊球于其上,用以与外界电性导通的接点。 Whether the above-described embodiment which, in Jieke upper surface or the lower surface of the carrier contact the other explant plurality of solder balls thereon for external electrical contact and conduction. 在上述的封装结构中,由于芯片接点间可以透过导电凸块电性连接,因此芯片接点间及芯片与载板接点间的传导路径甚短,且传导路径的径宽甚大,故可以降低传导阻抗,而减缓讯号的衰减,并且可以适于在高频电路的运作,而减少电感电容寄生效应(Parasitics)的发生。 In the package, since the inter-chip contacts can be connected through the conductive bumps electrically, and therefore the inter-chip contacts conductive path between it and the chip and the carrier contacts very short, and the conductive path diameter width is very large, it is possible to reduce conduction impedance, attenuation of the signal is slowed, and may be adapted to high frequency operation of the circuit, and reduce inductance and capacitance parasitics (parasitics) a. 此外,由于导电凸块与载板接点或芯片接点接触的面积甚大,且载板接点可以直接与芯片接点接触,因此其接触阻抗甚小,故可以避免发生阻抗不匹配的现象,以致产生讯号反射的情形。 Further, since the area of ​​the conductive bump contacts and the carrier contacts or chip contacts is very large, and the carrier contacts may be in contact directly with the chip contacts so that contact resistance is very small, so the phenomenon of impedance mismatch can be avoided, so as to produce the signal reflecting situation. 另外,由于本发明可以改善芯片封装结构中如上所述的电性效能,因此会有甚佳的电源及接地的效果。 Further, since the present invention can improve electrical performance of the chip package structure as described above, and therefore the effect will be very good power and ground. 在上述实施例中,以网板印刷的方式形成焊料于芯片接点上及载板点上,然而本发明形成焊料的方式并非仅限于此,请参照图7至图9, 亦可以先形成一屏蔽层(mask layer)254到第一芯片22的第一主动表面222、第二芯片24的第二主动表面242及载板20的上表面202上,当屏蔽层254为感光材质时,如光阻,便可以直接透过曝光的步骤而直接形成开口256,以暴露出第一芯片接点226、第二芯片接点246及载板接点208;当屏蔽层254为非感光材质时,便可以透过微影蚀刻等步骤而形成开口256,以暴露出第一芯片接点226、第二芯片接点246及载板接点208。 In the above embodiment, in order to screen printing a solder is formed on the chip carrier and the contacts on the point, however, the present invention is not limited to a solder, referring to FIG. 7 to FIG. 9, a mask can also be formed to layer (mask layer) 254 to the first active surface 222 of the first chip 22, the upper surface 202 of the second active surface 24 of chip 242 and the second carrier plate 20, when the shield layer 254 is a photosensitive material, such as photoresist , can be directly through the exposing step to form an opening 256 directly contacts 226 to expose the first chip, the second chip contacts 246 and the contact carrier plate 208; when the shield layer 254 is a non-photosensitive material, can pass through a micro Movies etching step to form an opening 256 to expose the first chip contacts 226, second contacts 246 and the chip carrier board contacts 208. 接着,便可以利用印刷的方式,形成一焊料258到屏蔽层254的开口256中,形成如图8所示的样式,其中焊料258由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成,金属粒子均匀地混合在助焊剂中。 Next, using a printing method can form a solder 258 into the opening 256 in the shield layer 254, patterned as shown in FIG. 8, wherein the solder flux by a 258 (not shown) and a plurality of metal particles (not shown) formed, metal particles are uniformly mixed in the flux. 之后,便进行回焊的制程,使得金属粒子可以熔融聚合而 Thereafter, they perform the reflow process, so that the metal particles may be melt polymerization

固化形成导电凸块259到第一芯片接点226、第二芯片接点246及载板接点208,如图9所示,其中第一芯片接点226可以通过导电凸块259 与第二芯片接点246电性连接。 Conductive bumps 259 to cure to form a first chip contacts 226, second contacts 246 and the chip carrier board contacts 208, shown in Figure 9, wherein the first chip 226 via the contacts 259 and the second conductive bump electrically connecting pads 246 connection. 同样地,第一芯片接点226可以通过导电凸块259与载板接点208电性连接。 Likewise, the first chip 226 contacts the contact 208 may be electrically connected through the conductive bumps 259 and the carrier. 接着,便将屏蔽层254去除。 Next, put the shielding layer 254 is removed. 其接下来的制程,如第一较佳实施例所述,在此便不再赘述。 Next, its manufacturing process, as described in the first preferred embodiment, will be omitted here. 需说明的是,图4、 5、 6、 7、 8及9中各组件的参考符号与图3中的各组件的参考符号相对应。 It is noted that, in FIG. 4, 5, 6, 7, 8 and 9, reference symbols of the components of FIG 3 with the reference symbol corresponding to each component. 于本实施例的详细说明中所提出的具体的实施例仅为了易于说明本发明的技术内容,而并非将本发明狭义地限制于该实施例,因此, 在不超出本发明的精神及以下申请专利范围的情况,可作种种变化实施。 Specific examples in the detailed description of the embodiments set forth merely for ease of description the technical details of the present invention, but not limit the present invention narrowly limited to this embodiment, therefore, without departing from spirit of the invention and the following claims the patentable scope of the case, various changes may be implemented.

Claims (31)

  1. 1. 一种桥接形式的多芯片封装构造,其特征在于,包含:一载板,该载板具有一上表面及一下表面;一第一芯片,其具有一第一主动表面、一第一背面及一第一侧壁,该第一主动表面具有至少一第一接点且该第一侧壁连接该第一主动表面与该第一背面,该第一芯片以该第一背面面向该封装载板的上表面配置,并与该载板电性连接;一第二芯片,其具有一第二主动表面、一第二背面及一第二侧壁,该第二主动表面具有至少一第二接点且该第二侧壁连接该第二主动表面与该第二背面,该第二芯片以该第二背面面向该封装载板的上表面配置,并与该载板电性连接;及至少一第一导电凸块,该导电凸块依附在该第一芯片的第一主动表面上及第二芯片的第二主动表面上延伸,使该第一芯片与该第二芯片电性连接。 A multi-chip package in the form of a bridge structure, characterized in that, comprising: a carrier plate, said carrier plate having an upper surface and a lower surface; a first chip having a first active surface, a back surface of the first and a first side wall, the first active surface having at least a first contact connecting the first sidewall and the first active surface and the back surface first, the first chip faces the back surface of the first package carrier the upper surface is configured and connected electrically to the carrier plate; a second chip having a second active surface, a second back surface and a second sidewall, the second active surface having at least a second contact and the second sidewall connected to the second active surface and the second back surface, the back surface of the second chip facing the upper surface of the second package carrier is disposed and connected electrically with the carrier; and at least one first conductive bumps, the conductive bumps attached to the second active surface and extending over a second active chip on the first surface of the first chip so that the first chip to the second chip is connected electrically.
  2. 2. 如权利要求l所述的桥接形式的多芯片封装构造,其中更包含一封装材料,其包覆该第一芯片、该第二芯片、该载板的上表面及该第一导电凸块。 2. A bridge according to claim l in the form of a multi-chip package structure, which comprises a further encapsulation material encapsulating the first chip, the second chip, the upper surface of said carrier plate and said first conductive bump .
  3. 3. 如权利要求l所述的桥接形式的多芯片封装构造,其中更包含多个导电组件,该导电组件设置在该载板的下表面。 L bridge form according to claim multi-chip package structure, which further comprises a plurality of conductive elements, the conductive elements provided on the lower surface of the carrier plate.
  4. 4. 如权利要求3所述的桥接形式的多芯片封装构造,其中所述导电组件为焊球。 4. The multi-chip package structure of the bridge form of claim 3, wherein said conductive component is a solder ball.
  5. 5. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一芯片具有的第一接点至少部分位于该第一芯片的边缘上。 5. A bridge according to claim l in the form of a multi-chip package structure, wherein the first chip having a first contact point is at least partially located on an edge of the first chip.
  6. 6. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第二芯片具有的第二接点至少部分位于该第二芯片的边缘上。 L in the form of bridge according to claim 6. The multi-chip package structure, wherein the second chip having a second contact at least partially located on an edge of the second chip.
  7. 7. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一导电凸块为锡铅合金。 7. A bridge according to claim l in the form of a multi-chip package structure, wherein said first conductive bump is tin-lead alloy.
  8. 8. 如权利要求l所述的桥接形式的多芯片封装构造,其中所述第一导电凸块无铅导电材料。 L in the form of the bridge as claimed in claim multi-chip package structure, wherein said first conductive bump lead-free conductive material.
  9. 9. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第一芯片的第一接点紧靠在该第二芯片的第二接点的旁边。 9. The multi-chip package structure of the bridge form of claim 1, wherein the first chip contacts abut against a first side of the second contact of the second chip.
  10. 10. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第一导电凸块为导电胶。 10. The multi-chip package structure of the bridge form of claim 1, wherein said first conductive bump to conductive paste.
  11. 11. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片的第二侧壁紧邻于所述第一芯片的第一侧壁。 11. The multi-chip package structure of the bridge form of claim 1, wherein a second sidewall of the second chip to the first sidewall proximate the first chip.
  12. 12. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片具有的第二接点紧邻于所述第一芯片具有的第一接点配置。 12. The multi-chip package structure of the bridge form of claim 1, wherein the second chip having a second contact proximate to said first chip having a first joint configuration.
  13. 13. 如权利要求1所述的桥接形式的多芯片封装构造,其中所述第二芯片的主动表面与所述第一芯片的主动表面为共平面的配置。 13. The multi-chip package structure of the bridge form of claim 1, wherein the active surface of the chip and a second active surface of the first chip is coplanar configuration.
  14. 14. 如权利要求1所述的桥接形式的多芯片封装构造,更包含多条导电线,其中第一芯片通过所述导电线与该载板电性连接。 14. The multi-chip package structure of the bridge form of claim 1, further comprising a plurality of conductive lines, wherein the first chip is connected electrically to the carrier board through the conductive wire.
  15. 15. 如权利要求1所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第二芯片通过所述导电线与该载板电性连接。 15. The multi-chip package structure of the bridge form of claim 1, further comprising a plurality of conductive lines, wherein the second chip is connected to the carrier through the electrically conductive lines.
  16. 16. 如权利要求13所述的桥接形式的多芯片封装构造,其中所述第一芯片的第一侧壁及所述第二芯片的第二侧壁间设置一填充体,该填充体具有一上表面,该上表面同时与第一芯片的主动表面与第二芯片的主动表面为共平面。 16. A multi-chip package structure as claimed in bridge form according to claim 13, wherein a first sidewall between the first chip and second side walls of the second chip is provided with a filler, the filler having a on the surface, the top surface while the active surface of the active surface of the first chip and the second chip is coplanar.
  17. 17. 如权利要求1所述的桥接形式的多芯片封装构造,其中该载板还具有一开口,所述第一芯片及所述第二芯片容置于该开口中。 17. The multi-chip package structure of the bridge form of claim 1, wherein the carrier also has an opening, the first chip and the second chip is received in the opening.
  18. 18. 如权利要求17所述的桥接形式的多芯片封装构造,其中还包含一散热片,所述散热片设置于该载板的下表面。 18. A multi-chip package structure as claimed in bridge form according to claim 17, further comprising a heat sink, the heat sink is provided on the lower surface of the carrier plate.
  19. 19. 如权利要求18所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置于该载板的上表面。 19. A multi-chip package structure as claimed in bridge form according to claim 18, further comprising a plurality of solder balls, the solder balls disposed on the surface of the carrier plate.
  20. 20. 如权利要求17所述的桥接形式的多芯片封装构造,其中所述开口内部具有一周壁,该第一芯片及该第二芯片还分别具有第三侧壁及一第四侧壁,且该第三侧壁及第四侧壁分别紧邻该周壁。 20. A multi-chip package structure as claimed in bridge form according to claim 17, wherein said inner opening having a peripheral wall, the first chip and the second chip further respectively have third sidewall and a fourth sidewall, and the third side wall and the fourth side wall adjacent to the peripheral wall respectively.
  21. 21. 如权利要求17所述的桥接形式的多芯片封装构造,其中所述第二芯片的主动表面、所述第一芯片的主动表面及所述载板的上表面为共平面的配置。 21. A multi-chip package structure as claimed in bridge form according to claim 17, wherein the active surface of the second chip, the first chip active surface and the upper surface of the carrier plate is coplanar configuration.
  22. 22. 如权利要求20所述的桥接形式的多芯片封装构造,其中还包含一散热片,该散热片设置于该载板的下表面。 22. A multi-chip package structure as claimed in bridge form according to claim 20, further comprising a heat sink, the heat sink is provided on the lower surface of the carrier plate.
  23. 23. 如权利要求21所述的桥接形式的多芯片封装构造,其中还包含一散热片,该散热片设置于该载板的下表面。 23. A multi-chip package structure as claimed in bridge form according to claim 21, further comprising a heat sink, the heat sink is provided on the lower surface of the carrier plate.
  24. 24. 如权利要求22所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置在该载板的上表面。 24. The multi-chip package structure of the bridge form of claim 22, further comprising a plurality of solder balls, the solder balls provided on the surface of the carrier plate.
  25. 25. 如权利要求23所述的桥接形式的多芯片封装构造,其中还包含多个焊球,所述焊球设置在该载板的上表面。 25. A multi-chip package structure as claimed in bridge form according to claim 23, further comprising a plurality of solder balls, the solder balls provided on the surface of the carrier plate.
  26. 26. 如权利要求17所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第一芯片通过所述导电线与该载板电性连接。 26. The multi-chip package structure of the bridge form of claim 17, further comprising a plurality of conductive lines, wherein the first chip is connected electrically to the carrier board through the conductive wire.
  27. 27. 如权利要求17所述的桥接形式的多芯片封装构造,还包含多条导电线,其中第二芯片通过所述导电线与该载板电性连接。 27. The multi-chip package structure of the bridge form of claim 17, further comprising a plurality of conductive lines, wherein the second chip is connected to the carrier through the electrically conductive lines.
  28. 28. 如权利要求20所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第一芯片通过所述第二导电凸块与该载板电性连接。 28. The multi-chip package structure of the bridge form of claim 20, further comprising at least a second conductive bump, wherein the first chip is connected through the second conductive bump electrically with the carrier plate.
  29. 29. 如权利要求20所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第二芯片通过所述第二导电凸块与该载板电性连接。 29. The multi-chip package structure of the bridge form of claim 20, further comprising at least a second conductive bump, wherein the second chip is connected through the second conductive bump electrically with the carrier plate.
  30. 30. 如权利要求21所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第一芯片通过所述第二导电凸块与该载板电性连接。 Multi-chip package structure of claim 21 in the form of a bridge as claimed in claim 30., further comprising at least a second conductive bump, wherein the first chip is connected through the second conductive bump electrically with the carrier plate.
  31. 31. 如权利要求21所述的桥接形式的多芯片封装构造,还包含至少一第二导电凸块,其中第二芯片通过所述第二导电凸块与该载板电性连接。 Multi-chip package structure of claim 21 in the form of a bridge as claimed in claim 31, further comprising at least a second conductive bump, wherein the second chip is connected through the second conductive bump electrically with the carrier plate.
CN 03156270 2003-09-02 2003-09-02 Bridging multi-chip packaging structure CN100474581C (en)

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US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US6020597A (en) 1997-03-05 2000-02-01 Lg Semicon Co., Ltd. Repairable multichip module
US6410983B1 (en) 1999-05-26 2002-06-25 Fujitsu Limited Semiconductor device having a plurality of multi-chip modules interconnected by a wiring board having an interface LSI chip
GB2373924A (en) 1997-05-17 2002-10-02 Hyundai Electronics Ind IC device with a metal thermal conductive layer having an opening for evacuating air

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US6020597A (en) 1997-03-05 2000-02-01 Lg Semicon Co., Ltd. Repairable multichip module
GB2373924A (en) 1997-05-17 2002-10-02 Hyundai Electronics Ind IC device with a metal thermal conductive layer having an opening for evacuating air
US6410983B1 (en) 1999-05-26 2002-06-25 Fujitsu Limited Semiconductor device having a plurality of multi-chip modules interconnected by a wiring board having an interface LSI chip

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