CN100474581C - Bridging multi-chip packaging structure - Google Patents

Bridging multi-chip packaging structure Download PDF

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Publication number
CN100474581C
CN100474581C CNB031562701A CN03156270A CN100474581C CN 100474581 C CN100474581 C CN 100474581C CN B031562701 A CNB031562701 A CN B031562701A CN 03156270 A CN03156270 A CN 03156270A CN 100474581 C CN100474581 C CN 100474581C
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China
Prior art keywords
chip
bridged
style
package structure
multichip package
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CNB031562701A
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CN1591862A (en
Inventor
洪志斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a bridged type multi-chip package structure. It mainly includes a carrier plate, a first chip, a second chip and at least a conductive body. Said carrier plate has an upper surface and correspondent lower surface, several carrier plate contacts are positioned on upper surface of said carrier plate. The first chip has a first active surface, said first chip also has at least a first contact which is placed on first active surface of said first chip. Similarly, the second chip has a second active surface, said second active surface also has at least a second contact. Which is placed on second active surface of said second chip. The first side wall of first chip is adjacent to second side wall of second chip, and the first active surface of first chip and second active surface of second chip are placed on a common plane. The conductive body is extended on first active surface of first chip and second active surface of second chip so as to make first contact of first chip and second contact of second chip be electrically connected.

Description

The multichip package structure of bridged-style
Technical field
The present invention relates to a kind of multichip package structure, particularly a kind of multichip package structure of bridged-style.
Background technology
In recent years, along with making rapid progress of electronic technology, the high-tech electronic product is also come out one after another, thereby more humane, functional better electronic product is constantly weeded out the old and bring forth the new, yet various products are invariably towards light, thin, short, little trend design, so that more convenient comfortable use to be provided.And the finishing an of electronic product, Electronic Packaging is being played the part of important role, the mode that its chip chamber electrically connects, general common has two kinds, and first kind of mode for lead-in wire bonding (wire-bonding), second kind are the mode of flip-chip (flip chip).With regard to the mode of lead-in wire bonding, it utilizes a wire bonder platform its lead bonding joint to be moved on the contact of chip earlier, and the mode of utilizing point discharge becomes the end points fusing of conductor wire the pattern of ball-type, so just conductor wire can be got on the contact of chip, just mobile then lead bonding joint is to the contact of another chip, and in the process that moves, lead bonding joint also can be emitted conductor wire, utilizes the ultrasonic waves fusing mode that conductor wire is got on the contact of another chip more at last.
Next, a kind of multichip packaging structure of known utilization lead-in wire bonding mode will be introduced.Please refer to Fig. 1, it illustrates the generalized section of the multichip packaging structure of known utilization lead-in wire bonding mode.This encapsulating structure comprises a support plate 10, one first chip 12, one second chip 14, many conductor wires 160,162,164, an encapsulating material 18 and a plurality of soldered balls 19.Support plate 10 has a upper surface 102 and corresponding lower surface 104, and support plate 10 has a plurality of carrier plate contacts 106 and first chip carrier 105 and second chip carrier 109,109 of the carrier plate contacts 106 and first chip carrier 105 and second chip carriers are on the upper surface 102 of support plate 10, and carrier plate contacts 106 be looped around first chip carrier 105 and second chip carrier 109 around, and 107 of carrier plate contacts are on the lower surface 104 of support plate 10.First chip 12 has an active surface 122 and the first corresponding back side 124, and first chip 12 also has a plurality of first chip contacts 126, and the position is on the active surface 122 of first chip 12.First chip 12 also attaches on the chip carrier 108 of support plate 10 by an adhesion material (not being shown among the figure) with its first back side 124, and the mode of utilizing the lead-in wire bonding electrically connects first chip 12 and support plate 10, wherein a termination of conductor wire 160 is incorporated on the first chip contact 126, and the other end of conductor wire 160 joins on the carrier plate contacts 106.Similarly, second chip 14 has one second active surface 142 and the second corresponding back side 144, and second chip 14 also has a plurality of second chip contacts 146, and the position is on second active surface 142 of second chip 14.Second chip 14 also attaches on the chip carrier 109 of support plate 10 by an adhesion material (not being shown among the figure) with its second back side 144, and the mode of utilizing the lead-in wire bonding electrically connects second chip 14 and support plate 10, wherein a termination of conductor wire 162 is incorporated on the second chip contact 146, and the other end of conductor wire 162 joins on the carrier plate contacts 108.In addition, first chip 12 and second chip 14 electrically conduct by conductor wire 164.In addition, encapsulating material 18 coats the upper surface 102 and the conductor wire 160,162 and 164 of first chip 12, second chip 14, support plate 10.
In above-mentioned encapsulating structure, first chip 12 electrically connects by the lead 164 and second chip 14, yet because the sectional area of lead 164 is very little and length is very long, therefore the characteristic impedance coupling is bad, make signal to be decayed apace, and when high-frequency circuit operates, have the generation of inductance capacitance ghost effect (Parasitics), so that produce the situation of signal reflection.In addition, because the area of the lead 164 and the first chip contact transmission path is very little, be unfavorable for that voltage and electric current provide, and cause the deleterious of power supply and ground connection.
In view of this, for avoiding the shortcoming of aforementioned multichip package structure,, be an important problem in fact to promote the chip usefulness of multichip package structure.
Summary of the invention
Because above-mentioned problem, purpose of the present invention provides a kind of multichip packaging structure, and the electric conducting material replacement conductor wire with the bridge joint pattern so can shorten the distance that chip chamber electrically connects, and makes the electrical property efficiency of multichip packaging structure to improve.
Thus, in order to reach above-mentioned purpose, the present invention proposes a kind of chip-packaging structure, comprises a support plate, one first chip, one second chip and at least one conductive projection and a plurality of soldered ball at least.Support plate has a upper surface and corresponding lower surface, and support plate is at least one carrier plate contacts of tool also, and all the position is in upper surface of said carrier plate.First chip has one first active surface, and first chip also has at least one first chip contact, is configured on first active surface of first chip.Similarly, second chip has one second active surface, and second chip also has at least one second chip contact, is configured on second active surface of second chip.Wherein, first chip and second chip are disposed on the support plate in lead-in wire bonding mode, and electrically connect with support plate.In addition, at least one the first side wall of first chip is close to second sidewall of second chip, and second active surface of first active surface of first chip and second chip is coplanar configuration.Conductive projection is extending on first active surface of first chip and on the second surface of second chip, and first contact of first chip and second contact of second chip are electrically connected.
From the above, wherein chip-packaging structure also comprises an encapsulating material, coats first chip and second chip, upper surface of said carrier plate and conductive projection.The first chip contact and second chip contact difference position are on the edge of first chip and second chip, and next-door neighbour's configuration.In addition, conductive projection can be leypewter, unleaded electric conducting material or conducting resinl.
In sum, multichip packaging structure of the present invention, because the contact of chip chamber can see through conductive projection and electrically connect, therefore the conducting path between the chip contact is very short, and the footpath of conducting path is wide very big, thus can reduce conduction resistance, and the decay that slows down signal, and can be suitable for running, and reduce the generation of inductance capacitance ghost effect at high-frequency circuit.In addition, because the area that contacts with the chip contact of conductive projection is very big, and carrier plate contacts can directly contact with the chip contact, thus can avoid taking place as the unmatched phenomenon of impedance of bonding structure that goes between, and have excellent power supply and ground connection effect.
Hereinafter with reference to relevant drawings, the multichip package structure according to the bridged-style of preferred embodiment of the present invention is described.
Description of drawings
Fig. 1 is a schematic diagram, shows known multichip package structure.
Fig. 2 is a schematic diagram, shows the multichip packaging structure of the bridged-style in the present invention's first preferred embodiment.
Fig. 3 is a schematic diagram, shows the multichip packaging structure of the bridged-style in the present invention's second preferred embodiment.
Fig. 4 is a schematic diagram, shows the multichip packaging structure of the bridged-style in the present invention's the 3rd preferred embodiment.
Fig. 5 is a schematic diagram, shows the multichip packaging structure of the bridged-style in the present invention's the 4th preferred embodiment.
Fig. 6 is a schematic diagram, shows the multichip packaging structure of the bridged-style in the present invention's the 5th preferred embodiment.
Fig. 7 to Fig. 9 is a schematic diagram, the generalized section of the multichip packaging structure processing procedure of a kind of bridged-style of demonstration the present invention the 4th preferred embodiment.
Symbol description among the figure
10 support plates
102 support plate upper surfaces
104 support plate lower surfaces
105 first chip carriers
106,108 carrier plate contacts
107 conductive components (soldered ball)
109 second chip carriers
12 first chips
122 first active surfaces
124 first back sides
126 first chip contacts
14 second chips
142 second active surfaces
144 second back sides
146 second chip contacts
160,162,164 conductor wires
18 adhesive bodies
20 support plates
201 openings
202 support plate upper surfaces
203 perisporiums
204 support plate lower surfaces
206,208 carrier plate contacts
207 conductive components (soldered ball)
21 fin
22 first chips
221 the first side walls
222 first active surfaces
223 the 3rd sidewalls
224 first back sides
226,228 first chip contacts
24 second chips
241 second sidewalls
242 second active surfaces
243 the 4th sidewalls
244 second back sides
246,248 second chip contacts
254 screens
256 openings
258 scolders
259 conductive projections
260,262 conductor wires
264 conductive projections
268 conductive projections
28 adhesive bodies
29 obturators
292 obturator upper surfaces
Embodiment
Fig. 2 discloses a kind of multichip package structure of bridged-style of the present invention's first preferred embodiment, and it mainly comprises a support plate 20, one first chip 22, one second chip 24 and a conductive projection 264.This support plate 20 has a upper surface 202 and corresponding a lower surface 204, a plurality of carrier plate contacts 206,208, and all the position is at the upper surface of support plate 20.First chip 22 has one first active surface 222, and this first chip 22 also has at least one first contact 226, is configured on first active surface 222 of first chip 22.Similarly, second chip 24 has one second active surface 242, and this second chip 24 also has at least one second contact 246, is configured on second active surface 242 of second chip 24.Wherein, first chip 22 also is arranged on the support plate 20 by an adhesion material (as elargol) with its back side (first back side 224); Similarly, second chip 24 also is arranged on the support plate 20 by an adhesion material (as elargol) with its back side (second back side 224).Conductor wire 260 electrically connects the carrier plate contacts 206 of first contact 226 with the support plate 20 of first chip 22, and conductor wire 262 electrically connects the carrier plate contacts 208 of second contact 246 with the support plate 20 of second chip 24.
In addition, second sidewall 241 of the first side wall 221 next-door neighbours second chip 24 of first chip 22, and second active surface 242 of first active surface 222 of first chip 22 and second chip 24 is coplanar configuration, moreover, the first chip contact 226 and the second chip contact, 246 difference positions are on the edge of first chip 22 and second chip 24, and next-door neighbour's configuration.Conductive projection 264 is extending on first active surface 222 of first chip 22 and on second active surface 242 of second chip 24, and first contact 228 of first chip 22 and second contact 248 of second chip 24 are electrically connected.From the above, this multichip packaging structure also comprises an encapsulating material 280, coats the upper surface 202 and the conductive projection 264 of first chip 22 and second chip 24, support plate 20.In addition, above-mentioned conductive projection 264 can be leypewter, unleaded electric conducting material or conducting resinl.
As shown in Figure 3, the multichip package structure of the bridged-style of second preferred embodiment of the present invention, when 241 of the second sides of the first side 221 of first chip 22 and second chip 24 have a bigger space, an obturator 29 can be set, earlier as non-conductive colloid.Second active surface, 242 coplines of first active surface 222 of the upper surface of this obturator 29 and first chip 22 and second chip 24.Then, can utilize the mode of screen printing, form a scolder to the upper surface 292 of the first chip contact 226, the second chip contact 246 and obturator, wherein scolder is made of a scaling powder (not illustrating) and a plurality of metallic (not illustrating), and metallic is blended in the scaling powder equably.Afterwards, just carry out the processing procedure of reflow, make that metallic can melt polymerization and solidify to form on conductive projection 264 to the first chip contacts 226 and the second chip contact 246.Wherein the first chip contact 226 and the second chip contact 246 can electrically connect mutually by conductive projection 264, and conductive projection 264 is such as being leypewter or unleaded electric conducting material.
Then, please refer to Fig. 4, be the multichip package structure of the bridged-style of the 3rd preferred embodiment of the present invention.Wherein, support plate 20 has an opening 201, first chip 22 and second chip 24 are placed in this opening 201, and adhesive body 28 coats part, first chip 22, second chip 24 and the conductive projection 264 of these support plate 20 upper surfaces 202, and expose at the back side that makes first chip 22 and second chip 24, further to dwindle the thickness of overall package structure by this.
Moreover, from the above, as shown in Figure 5, one fin 21 also can be set in support plate 20 lower surfaces 204, and first chip 22 and second chip 24 are arranged on the fin 21, so more can promote the heat dissipation of packaging body, this is the multichip package structure of the bridged-style of the 4th preferred embodiment of the present invention.
From the above, please refer to Fig. 6, be the multichip package structure of the bridged-style of the 5th preferred embodiment of the present invention.Support plate 20 also has an opening 201, the first chips 22 and second chip 24 is placed in this opening 201 simultaneously, and the size of this opening 201 just can ccontaining first chip 22 and second chip 24.Wherein, first chip 22 has one the 3rd side 223, second chip 24 has a four side 243, has a perisporium 203 in the opening 20, the perisporium 203 of the sidewall next-door neighbour opening of this first chip 22 and second chip 24, and first active surface 222 of first chip 22, second active surface 242 of second chip 24 and upper surface 202 coplanar configuration of support plate 20.Then, form one second conductive projection 266 to electrically connect first chip 22 and support plate 20.Similarly, other forms one the 3rd conductive projection 268 to electrically connect second chip 24 and support plate 20.
No matter be above-mentioned which kind of embodiment, all can plant in addition and connect a plurality of soldered balls thereon, in order to the contact that electrically conducts with the external world in upper surface of said carrier plate or lower surface.
In above-mentioned encapsulating structure, because can see through conductive projection between the chip contact electrically connects, therefore the conducting path that reaches between chip and carrier plate contacts between the chip contact is very short, and the footpath of conducting path is wide very big, so can reduce conduction resistance, and the decay that slows down signal, and can be suitable for running at high-frequency circuit, and reduce the generation of inductance capacitance ghost effect (Parasitics).In addition, because conductive projection is very big with the area that carrier plate contacts or chip contact contacts, and carrier plate contacts can directly contact with the chip contact, so its contact impedance is very little, so can avoid taking place the unmatched phenomenon of impedance, consequently produces the situation that signal reflects.In addition, because the present invention can improve aforesaid electrical property efficiency in the chip-packaging structure, therefore have the excellent power supply and the effect of ground connection.
In the above-described embodiments, mode with screen printing forms scolder on the chip contact and on the support plate point, yet the present invention forms the mode of scolder and is not limited only to this, please refer to Fig. 7 to Fig. 9, can also form first active surface 222 of a screen (mask layer) 254 to first chips 22 earlier, on second active surface 242 of second chip 24 and the upper surface 202 of support plate 20, when screen 254 is the sensitization material, as photoresistance, just can directly see through step of exposing and directly form opening 256, to expose the first chip contact 226, the second chip contact 246 and carrier plate contacts 208; When screen 254 is non-sensitization material, just can sees through step such as lithography and form opening 256, to expose the first chip contact 226, the second chip contact 246 and carrier plate contacts 208.Then, just can utilize the mode of printing, form a scolder 258 in the opening 256 of screen 254, form pattern as shown in Figure 8, wherein scolder 258 is made of a scaling powder (not illustrating) and a plurality of metallic (not illustrating), and metallic is blended in the scaling powder equably.Afterwards, just carry out the processing procedure of reflow, make that metallic can melt polymerization and solidify to form conductive projection 259 to first chip contacts 226, the second chip contact 246 and carrier plate contacts 208, as shown in Figure 9, wherein the first chip contact 226 can electrically connect by the conductive projection 259 and the second chip contact 246.Similarly, the first chip contact 226 can electrically connect by conductive projection 259 and carrier plate contacts 208.Then, just screen 254 is removed.Its ensuing processing procedure is as described in first preferred embodiment, just repeat no more at this.It should be noted that the reference symbol of each assembly among Fig. 4,5,6,7,8 and 9 among the reference symbol of each assembly and Fig. 3 is corresponding.
The specific embodiment that is proposed in the detailed description of present embodiment is only in order to be easy to illustrate technology contents of the present invention, and be not with narrow sense of the present invention be limited to this embodiment, therefore, in the situation that does not exceed spirit of the present invention and following claim, can make many variations and implement.

Claims (31)

1. the multichip package structure of a bridged-style is characterized in that, comprises:
One support plate, this support plate has a upper surface and a lower surface;
One first chip, it has one first active surface, one first back side and a first side wall, this first active surface has at least one first contact and this first side wall connects this first active surface and this first back side, this first chip disposes with the upper surface of this first back side towards this encapsulating carrier plate, and electrically connects with this support plate;
One second chip, it has one second active surface, one second back side and one second sidewall, this second active surface has at least one second contact and this second sidewall connects this second active surface and this second back side, this second chip disposes with the upper surface of this second back side towards this encapsulating carrier plate, and electrically connects with this support plate; And
At least one first conductive projection, this conductive projection are attached on first active surface of this first chip and on second active surface of second chip and extend, and make the electric connection of this first chip and this second chip.
2. the multichip package structure of bridged-style as claimed in claim 1 wherein more comprises an encapsulating material, and it coats this first chip, this second chip, this upper surface of said carrier plate and this first conductive projection.
3. the multichip package structure of bridged-style as claimed in claim 1 wherein more comprises a plurality of conductive components, and this conductive component is arranged on the lower surface of this support plate.
4. the multichip package structure of bridged-style as claimed in claim 3, wherein said conductive component is a soldered ball.
5. the multichip package structure of bridged-style as claimed in claim 1, first contact to the small part that wherein said first chip has is positioned on the edge of this first chip.
6. the multichip package structure of bridged-style as claimed in claim 1, second contact to the small part that wherein said second chip has is positioned on the edge of this second chip.
7. the multichip package structure of bridged-style as claimed in claim 1, wherein said first conductive projection is a leypewter.
8. the multichip package structure of bridged-style as claimed in claim 1, the unleaded electric conducting material of wherein said first conductive projection.
9. the multichip package structure of bridged-style as claimed in claim 1, first contact of wherein said first chip abuts against the next door of second contact of this second chip.
10. the multichip package structure of bridged-style as claimed in claim 1, wherein said first conductive projection is a conducting resinl.
11. the multichip package structure of bridged-style as claimed in claim 1, second sidewall of wherein said second chip is in close proximity to the first side wall of described first chip.
12. the multichip package structure of bridged-style as claimed in claim 1, second contact that wherein said second chip has is in close proximity to first joint configuration that described first chip has.
13. the multichip package structure of bridged-style as claimed in claim 1, the active surface of the active surface of wherein said second chip and described first chip is coplanar configuration.
14. the multichip package structure of bridged-style as claimed in claim 1 more comprises many conductor wires, wherein first chip electrically connects by described conductor wire and this support plate.
15. the multichip package structure of bridged-style as claimed in claim 1 also comprises many conductor wires, wherein second chip electrically connects by described conductor wire and this support plate.
16. the multichip package structure of bridged-style as claimed in claim 13, between second sidewall of the first side wall of wherein said first chip and described second chip one obturator is set, this obturator has a upper surface, and this upper surface is a copline with the active surface of first chip and the active surface of second chip simultaneously.
17. the multichip package structure of bridged-style as claimed in claim 1, wherein this support plate also has an opening, and described first chip and described second chip are placed in this opening.
18. the multichip package structure of bridged-style as claimed in claim 17 wherein also comprises a fin, described fin is arranged at the lower surface of this support plate.
19. the multichip package structure of bridged-style as claimed in claim 18 wherein also comprises a plurality of soldered balls, described soldered ball is arranged at this upper surface of said carrier plate.
20. the multichip package structure of bridged-style as claimed in claim 17, wherein said open interior has a perisporium, this first chip and this second chip also have the 3rd sidewall and one the 4th sidewall respectively, and the 3rd sidewall and the 4th sidewall are close to this perisporium respectively.
21. the multichip package structure of bridged-style as claimed in claim 17, the active surface of the active surface of wherein said second chip, described first chip and described upper surface of said carrier plate are coplanar configuration.
22. the multichip package structure of bridged-style as claimed in claim 20 wherein also comprises a fin, this fin is arranged at the lower surface of this support plate.
23. the multichip package structure of bridged-style as claimed in claim 21 wherein also comprises a fin, this fin is arranged at the lower surface of this support plate.
24. the multichip package structure of bridged-style as claimed in claim 22 wherein also comprises a plurality of soldered balls, described soldered ball is arranged on this upper surface of said carrier plate.
25. the multichip package structure of bridged-style as claimed in claim 23 wherein also comprises a plurality of soldered balls, described soldered ball is arranged on this upper surface of said carrier plate.
26. the multichip package structure of bridged-style as claimed in claim 17 also comprises many conductor wires, wherein first chip electrically connects by described conductor wire and this support plate.
27. the multichip package structure of bridged-style as claimed in claim 17 also comprises many conductor wires, wherein second chip electrically connects by described conductor wire and this support plate.
28. the multichip package structure of bridged-style as claimed in claim 20 also comprises at least one second conductive projection, wherein first chip electrically connects by described second conductive projection and this support plate.
29. the multichip package structure of bridged-style as claimed in claim 20 also comprises at least one second conductive projection, wherein second chip electrically connects by described second conductive projection and this support plate.
30. the multichip package structure of bridged-style as claimed in claim 21 also comprises at least one second conductive projection, wherein first chip electrically connects by described second conductive projection and this support plate.
31. the multichip package structure of bridged-style as claimed in claim 21 also comprises at least one second conductive projection, wherein second chip electrically connects by described second conductive projection and this support plate.
CNB031562701A 2003-09-02 2003-09-02 Bridging multi-chip packaging structure Expired - Lifetime CN100474581C (en)

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EP4064337A4 (en) * 2019-12-13 2022-12-07 Huawei Technologies Co., Ltd. Electronic component, circuit board having same, and electronic device
CN111491489B (en) * 2020-04-10 2022-11-15 深圳国人无线通信有限公司 Printed board assembly

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