CN100472952C - Current-controlled CMOS delay cell with variable bandwidth - Google Patents
Current-controlled CMOS delay cell with variable bandwidth Download PDFInfo
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Abstract
Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.
Description
Technical field
The present invention relates to communication equipment field, more particularly, relate to a kind of delay cell of in communication equipment, realizing.
Background technology
Data communication system has experienced sustainable development for many years.In a lot of broadband data communication system applies, used the variable delay cell.And in these are used, control when requiring between different elements accommodometer often.The so a kind of application that postpones cell is in delay phase-locked loop (DLL).The universal method of a kind of DLL of design is to use a lot of delay blocks.And in the former technical matters, each independently delay block all can bring higher energy consumption.Design a kind of more energy-conservation time-delay piece and be worth expectation.
For the different elements in the communication system is carried out suitable location and control, require to take some safeguards usually, regulate wherein different signals by these measures, to guarantee suitable location and timing.Equally, the demand of how better effective measures is also existed always and will exist,, postpone in can be in communication system and the such communication system different communication equipment of cell accomplished by these measures.
Various C3MOS circuit engineerings are 09/484 in Application No., 856, existing U.S. Patent number is 6,424, in 194 B1, the patent of invention people more detailed description is arranged, for the full text of the described document of above-mentioned purpose is contained in this as a reference for A.Hairapetian by name " the CMOS logic family of Current Control (Current Controlled CMOS Logic Family) ".
Other technology also is developed to increase the gain bandwidth product of cmos circuit.For example, shunt peaking promptly is a kind of method that can improve gain band width product.Shunt peaking relates to the bandwidth of inductance with expanded circuit of contacting on output resistance.The induction wide frequency technology of this C3MOS of being combined with circuit is 09/610 in Application No., 905, existing U.S. Patent number is 6,340, in 899 B1, the patent documentation of invention people more detailed description is arranged, for the full text of the described document of above-mentioned purpose is contained in this as a reference for M.Green by name " the current-controlled cmos circuit (Current-Controlled CMOS Circuitswith Inductive Broadbanding) that the inductive bandwidth increases ".
Application No. is 10/028,806, existing U.S. Patent number 6,624,699 B2, in the patent documentation of inventor for Guangming Yin by name and Jun Cao " the CMOS wideband data amplifier circuit of Current Control (Current-controlled CMOS wideband data amplifier circuit) " by name, current-controlled cmos wideband data amplifier circuit with spread bandwidth disclosed herein is designed to be implemented in the purpose that has level and smooth frequency response in the very wide frequency range, wherein by using the series inductance peaking and the shunt inductance peaking that have Miller (Miller) electric capacity technology for eliminating to realize the maximum bandwidth expansion in CMOS (C3MOS or current-controlled cmos wideband data amplifier circuit) circuit, the document is quoted in full in this as reference.
Fig. 1 shows the embodiment 100 of current-controlled cmos (C3MOS) wideband data amplifying circuit.The biased current offset of current source transistor, thus at current source transistor from having produced constant electric current between the drain-to-source.Two independently difference transistor composition broadband difference transistor is right.First difference transistor links to each other the negative pole of its grid with the first polyphone peaking inductance L1, and positive differential input signal INP is connected on the positive pole of the first polyphone peaking inductance L1 simultaneously.Similarly, second difference transistor links to each other the negative pole of its grid with the second polyphone peaking inductance L2, and Fu differential input signal INN is connected on the positive pole of the second polyphone peaking inductance L2 simultaneously.
Suppose that first and second difference transistors are identical, the first and second polyphone peaking inductance L1 also have the same inductance with L2 so.The first output resistance R3 links to each other the drain electrode of its negative pole with first difference transistor, and the negative pole of its positive pole with the first shunt peaking inductance L 3 linked to each other.The second output resistance R4 links to each other the drain electrode of its negative pole with second difference transistor, and the negative pole of its positive pole with the second shunt peaking inductance L 4 linked to each other.The positive pole of the first and second shunt peaking inductance L 3 and L4 all links to each other (as V with positive voltage
CCShown in).
More suitably, the first and second output resistance R3 have the same resistance value R with R4, and the first and second shunt peaking inductance L 3 also have the same inductance with L4.First capacitor C 1 (can be counted as first Miller and eliminate capacitor C 1) links to each other the drain electrode of its positive pole with second difference transistor, and the grid of its negative pole with first difference transistor linked to each other.Second capacitor C 2 (can be counted as second Miller and eliminate capacitor C 2) links to each other the drain electrode of its positive pole with first difference transistor, and the grid of its negative pole with second difference transistor linked to each other.Drain electrode at second difference transistor obtains the first output signal OUTP, the drain electrode of first difference transistor to the second output signal OUTN.
Input serial resistance (L1 and L2) can enlarge the bandwidth of amplifier at high band generation resonance thus with the electric capacity of differential pair input.In addition, at high band, inductance (L1 and L2) is as the high impedance choke effect between terminal resistance (shown in 50 Ω resistance of two polyphones) and the electric capacity, so also improved the input reflection of the C3MOS wideband data amplifying circuit of this embodiment 100.
Fig. 2 shows the embodiment 200 of variable delay cell.As previously mentioned, the application of a lot of broadband data communications all needs to postpone the cell technology.Simultaneously, the variable delay cell postpones cell than fixed delay type can provide greater flexibility and adaptability.This embodiment 200 shows the basic building module in the data synchronization circuit.Input data (DIN) are by trigger (FF) reclocking that is driven by clock signal (CLK).For FF is run well, input data (DIN) and clock (CLK) must satisfy one or more specific clocking requirements.Often will insert the delay cell between input data (DIN) and FF, the timing relation between FF input clock (CLK) and data (DINN) of making like this can be adjusted to and can compensate any because process, supply voltage or temperature (PVT) change input signal phase change or the circuit delay variation that causes.Because input data (DINN) need more and more higher bandwidth to keep the signal integrity of input data according to the continuous speed input that increases forever so postpone cell.
Fig. 3 shows the embodiment 300 of another variable delay cell.This embodiment 300 is another kind of examples that use the variable delay cell.Embodiment 300 is 5 rank finite impulse response (FIR) (FIR) filters, and making up this filter is in order to handle input data (DIN).For making the FIR filter can be according to the design operate as normal, each postpone cell (such as, postpone cell 310,320,330 and 340) must have the same time delay, the common and data transfer rate of this time delay is inversely proportional to.Similar to embodiment 200 shown in Figure 2, require the variable delay cell can compensate any because PVT changes the circuit delay variation that causes.In addition, if the input data variation, postponing cell also needs to provide corresponding delay to change.Because a plurality of delay cells (such as, postpone cell 310,320,330 and 340) link to each other before and after normally, be very important for data transfer rate so the delay cell has higher relatively bandwidth.
In the variable delay cell embodiment 300 that has used 5 rank FIR filters, target is to produce a kind ofly to have equal-delay (such as, Δ t between each heterogeneity of data flow
n) data flow.In embodiment 300, data flow has comprised 5 compositions.Typically, this delay (such as, Δ t
n) be identical, and the delay of each is all regulated together in these delay cells 310,320,330 and 340.
Another can realize that the embodiment of variable delay cell is that output at routine data buffer (such as, differential pair) adds variable capacitive loads.Yet there is basic restriction in such mode.The circuit of these small-signal transfer functions can realize that its bandwidth and delay are contacted directly together by monopole response is approximate.For example, the lifting/lowering time of 10%-90% response input step equals 0.35/BW (BW refers to circuit small-signal response-three dB bandwidth) here.Retardation is big more, and bandwidth is more little.As a result, if adopted such circuit, the minimum bandwidth that postpones cell requires just to have produced the retardation upper limit.On the other hand, retardation is more little, and the bandwidth that circuit need have is just big more, this often means that if adopted simple one pole buffer, postpones cell and need have bigger energy and bigger area.
Fig. 4 shows the embodiment 400 that the adjustable high bandwidth of two pass postpones cell.This embodiment 400 for the input The data two separate data channels.One of them data channel has transmission delay (being expressed as the buffer 410 with little delay) relatively in a small amount, and another data channel has the transmission delay (being expressed as the buffer 420 with big delay) of relatively large amount.Next signal combines at summing stage by two different passages.The relative intensity of two passages can be conditioned (using control module 430), thereby makes total data channel have variable delay.In order to realize slow path, can contact several fast buffer, in the inhibit signal integrality, to produce enough big transmission delay.
For 10Gbps (gigabit/sec) or higher transmission rate, because technology is limit, the cmos data buffer will consume sizable energy usually.In the variable delay cell binary channels embodiment 400 of Fig. 4, at least three high-speed modules need power up, and comprise summer.Summer is consumed energy especially, because it has two pairs of full rate data input pins, this can increase sizable parasitic load to high-speed data channel.In addition, the input data are connected to express passway and slow path simultaneously.If this merges the output that input is connected to prebuffer, this configuration will significantly increase the load of previous stage, thereby reduces the total bandwidth of data channel.Be directly connected on the input pad of chip if this merges input, can make coupling serious degradation between receiver input and the printed circuit board trace owing to excessive capacitive load.The integrality that this can produce a large amount of reflections and significantly reduce the input data.Another potential problems that binary channels is used are signals through two different channel transfer when being merged together at the summer place, if the delay between two passages is significantly different, will produce extra shake.Very wishing to have to increase the high bandwidth of energy and load request variable delay cell in extensive use.
Summary of the invention
The present invention relates to plurality of devices and operation method thereof, further description is arranged in following brief description, embodiment and claim.
According to an aspect of the present invention, provide a kind of current-controlled cmos (C3MOS) delay cell with variable bandwidth, this circuit comprises:
First difference transistor comprises first source electrode, first grid, first drain electrode;
Second difference transistor comprises second source electrode, second grid, second drain electrode;
First current source is connected to first source electrode of first difference transistor and second source electrode of second difference transistor;
First input impedance is connected between the first grid of first differential input end of C3MOS delay cell with variable bandwidth and first difference transistor;
Second input impedance is connected between the second grid of second differential input end of C3MOS delay cell with variable bandwidth and second difference transistor;
First output impedance comprises first output resistance connected in series and the first shunt peaking inductance, and first output impedance is connected between first drain electrode and supply voltage of first difference transistor;
Second output impedance comprises second output resistance connected in series and the second shunt peaking inductance, and second output impedance is connected between second drain electrode and supply voltage of second difference transistor;
The 3rd difference transistor comprises the 3rd source electrode, the 3rd grid and the 3rd drain electrode;
The 4th difference transistor comprises the 4th source electrode, the 4th grid and the 4th drain electrode;
Second current source is connected to the 3rd source electrode of the 3rd difference transistor and the 4th source electrode of the 4th difference transistor;
Wherein first of first difference transistor drain electrode is connected with the second grid of second difference transistor, and second drain electrode of second difference transistor is connected with the first grid of first difference transistor;
Wherein the 3rd drain electrode of first of first difference transistor drain electrode, the 3rd difference transistor and the 4th grid of the 4th difference transistor can connect communicatedly;
Wherein the 4th drain electrode of second of second difference transistor drain electrode, the 4th difference transistor and the 3rd grid of the 3rd difference transistor can connect communicatedly.
Preferably, this circuit also comprises:
First electric capacity is connected between first drain electrode and the second grid of second difference transistor of first difference transistor;
Second electric capacity is connected between second drain electrode and the first grid of first difference transistor of second difference transistor.
Preferably, first input impedance comprises the first polyphone inductance; Second input impedance comprises the second polyphone inductance.
Preferably, first output resistance of first output impedance is connected between first drain electrode and the first shunt peaking inductance of first output impedance of first difference transistor; And
The first shunt peaking inductance of first output resistance is connected between first output resistance and supply voltage of first output impedance.
Preferably, first current source is first current source transistor;
Second current source is second current source transistor; And
First difference transistor, second difference transistor, the 3rd difference transistor, the 4th difference transistor, first current source transistor and second current source transistor are NMOS (N NMOS N-channel MOS N) transistors.
Preferably, first current source is first current source transistor;
Second current source is second current source transistor; And
First difference transistor, second difference transistor, the 3rd difference transistor, the 4th difference transistor, first current source transistor and second current source transistor are PMOS (P-channel metal-oxide-semiconductor) transistors.
Preferably, first current source is first variable current source;
Second current source is second variable current source; And
In first electric current by regulating first variable current source and second electric current of second variable current source at least one, the variable delay of control C3MOS delay cell with variable bandwidth.
Preferably, the delay of C3MOS delay cell with variable bandwidth is the function of the ratio that obtains divided by the second current source sum of first electric current of first current source and second current source of first electric current of first current source.
Preferably, the C3MOS delay cell with variable bandwidth is one that is applied in a plurality of delay cells of n rank finite impulse response (FIR) (FIR) filter.
According to an aspect of the present invention, provide a kind of current-controlled cmos (C3MOS) delay cell with variable bandwidth, this circuit comprises:
The broadband difference transistor is right, comprises the input of first difference, the input of second difference, the output of first difference, the output of second difference;
First current source, be used for into the broadband difference transistor to the power supply;
The commissure difference transistor is right, comprises the input of the 3rd difference, the input of the 4th difference, the output of the 3rd difference and the output of the 4th difference;
Second current source, be used for into the commissure difference transistor to the power supply;
First input impedance can be connected to right first difference input of broadband difference transistor communicatedly with first differential input signal;
Second input impedance can be connected to right second difference input of broadband difference transistor communicatedly with second differential input signal;
First output impedance, first difference output that the broadband difference transistor is right can be connected to supply voltage communicatedly;
Second output impedance, second difference output that the broadband difference transistor is right can be connected to supply voltage communicatedly;
Wherein, right the 3rd difference output can be connected right right the 3rd difference input of the output of second difference, commissure difference transistor of broadband difference transistor communicatedly with the commissure difference transistor;
Wherein, right the 4th difference output can be connected right right the 4th difference input of the output of first difference, commissure difference transistor of broadband difference transistor communicatedly with the commissure difference transistor;
Wherein, in first electric current by regulating first current source and second electric current of second current source at least one, the variable delay of control C3MOS delay cell with variable bandwidth.
Preferably, the delay of C3MOS delay cell with variable bandwidth is the function of the ratio that obtains divided by the second current source sum of first electric current of first current source and second current source of first electric current of first current source.
Preferably, the broadband difference transistor is to comprising:
First difference transistor comprises first source electrode, comprises the first grid of right first difference input of broadband difference transistor and comprises first of right second difference output of broadband difference transistor draining;
Second difference transistor comprises second source electrode, comprises the second grid of right second difference input of broadband difference transistor and comprises second of right first difference output of broadband difference transistor draining; And
First current source is connected to first source electrode of first difference transistor and second source electrode of second difference transistor;
The commissure difference transistor is to comprising:
The 3rd difference transistor comprises the 3rd source electrode, the 3rd grid and the 3rd drain electrode;
The 4th difference transistor comprises the 4th source electrode, the 4th grid and the 4th drain electrode;
Second current source is connected to the 3rd source electrode of the 3rd difference transistor and the 4th source electrode of the 4th difference transistor;
First drain electrode of first difference transistor, the 3rd drain electrode of the 3rd difference transistor can be connected communicatedly with the 4th grid of the 4th difference transistor;
Second drain electrode of second difference transistor, the 3rd drain electrode of the 3rd difference transistor can be connected communicatedly with the 4th grid of the 4th difference transistor.
Preferably, first electric capacity is connected between first difference output that the first right difference of broadband difference transistor is imported and the broadband difference transistor is right;
Second electric capacity is connected between the second right difference output end of the second right differential input end of broadband difference transistor and broadband difference transistor.
Preferably,
First input impedance comprises the first polyphone inductance; And
Second input impedance comprises the second polyphone inductance.
Preferably,
First output impedance comprises first output resistance and the first shunt peaking inductance of polyphone;
Second output impedance comprises second output resistance and the second shunt peaking inductance of series connection.
According to an aspect of the present invention, provide a kind of current-controlled cmos (C3MOS) delay cell with variable bandwidth, having comprised:
First difference transistor comprises first source electrode, first grid and first drain electrode;
Second difference transistor comprises second source electrode, second grid and second drain electrode;
First current source is connected to first source electrode of first difference transistor and second source electrode of second difference transistor;
First series inductance is connected between the first grid of first difference input of C3MOS delay cell with variable bandwidth and first difference transistor;
Second series inductance is connected between the second grid of second difference input of C3MOS delay cell with variable bandwidth and second difference transistor;
First output impedance, first output resistance and the first shunt peaking inductance that comprise series connection, first output resistance is connected between the drain electrode and the first shunt peaking inductance of first difference transistor, and the first shunt peaking inductance is connected between first output resistance and the supply voltage;
Second output impedance, second output resistance and the second shunt peaking inductance that comprise series connection, second output resistance is connected between the drain electrode and the second shunt peaking inductance of second difference transistor, and the second shunt peaking inductance is connected between second output resistance and the supply voltage;
First electric capacity is connected between the grid of the drain electrode of first difference transistor and second difference transistor;
Second electric capacity is connected between the grid of the drain electrode of second difference transistor and first difference transistor;
The 3rd difference transistor comprises the 3rd source electrode, the 3rd grid and the 3rd drain electrode;
The 4th difference transistor comprises the 4th source electrode, the 4th grid and the 4th drain electrode;
Second current source is connected to the 3rd source electrode of the 3rd difference transistor and the 4th source electrode of the 4th difference transistor;
Wherein, the 3rd drain electrode of first of first difference transistor drain electrode, the 3rd difference transistor can be connected communicatedly with the 4th grid of the 4th difference transistor; And
Wherein, the 4th drain electrode of second of second difference transistor drain electrode, the 4th difference transistor can be connected communicatedly with the 3rd grid of the 3rd difference transistor.
Preferably,
First current source is first variable current source;
Second current source is second variable current source; And
In first electric current by regulating first variable current source and second electric current of second variable current source at least one, the variable delay of control C3MOS delay cell with variable bandwidth.
Preferably, the delay of C3MOS delay cell with variable bandwidth is the function of the ratio that obtains divided by the second electric current sum of first electric current of first current source and second current source of first electric current of first current source.
Preferably, the C3MOS delay cell with variable bandwidth is the delay cell that is applied in a plurality of delay cells of N rank finite impulse response (FIR) (FIR) filter.
Preferably,
First current source is first current source transistor;
Second current source is second current source transistor; And
First difference transistor, second difference transistor, the 3rd difference transistor, the 4th difference transistor, first current source transistor and second current source transistor comprise NMOS (N NMOS N-channel MOS N) transistor or PMOS (P-channel metal-oxide-semiconductor) transistor.
By below the present invention with reference to the detailed description of accompanying drawing, it is clearer that other features and advantages of the present invention will become.
Description of drawings
Fig. 1 shows the embodiment of current-controlled cmos (C3MOS) broadband signal amplifying circuit.
Fig. 2 shows the embodiment of variable delay cell.
Fig. 3 has represented the embodiment of another variable delay cell.
Fig. 4 shows the embodiment that the adjustable high bandwidth of two pass postpones cell.
Fig. 5 shows the embodiment that variable bandwidth postpones cell.
The differential pair (standardization) that Fig. 6 shows by mutual connection produces the embodiment of delay to the current response of buffer stage (standardization).
Invention specifies
Various embodiments of the present invention relate to the System speed logic circuit that is applied in complementary metal oxide semiconductor (CMOS) treatment technology.Distinguish term " CMOS process technology " and " CMOS logic " at this.Generally be meant various mature C MOS manufacture processes in this used CMOS process technology, it constructs the field-effect transistor that has grid lead wire on silicon chip, described grid lead wire is placed on insulating material such as the silicon dioxide by polycrystalline silicon material usually and makes.On the other hand, the CMOS logic is meant with complementary cmos transistor (N raceway groove and P raceway groove) and constitutes various logic gates and complicated logic circuits more that wherein the quiescent current of Xiao Haoing is zero.Various embodiments of the present invention use Current Control mechanism to develop the very fast current-controlled cmos of a series of speed (C3MOS or C
3MOS
TM) logic, it can be made with various traditional CMOS process technologies, but can not consume quiescent current as traditional CMOS logic.C3MOS logic OR Current Control metal oxide semiconductor field effect tube (MOSFET) logic can be exchanged use here.
Fig. 5 shows the embodiment 500 that variable bandwidth postpones cell.In this embodiment 500, signal input part is connected to embodiment 100 current-controlled cmos similar, that enlarged bandwidth (C3MOS) the wideband data amplifying circuits to Fig. 1.This running that enlarges bandwidth wideband data amplifying circuit, Application No. is 10/028,806, existing U.S. Patent number 6, in 624,699 B2, the patent documentation of invention people explanation is arranged also for Guangming Yin and Jun Cao " the CMOS wideband data amplifier circuit of Current Control (Current-controlled CMOS wideband data amplifier circuit) " by name.In this C3MOS wideband data amplifying circuit that has enlarged bandwidth,, realize the maximum bandwidth expansion by in current-controlled cmos (C3MOS or C3MOS) circuit, using series inductance peaking and the shunt inductance peaking that has the miller capacitance technology for eliminating.
Be connected to the wideband data buffer output end of having expanded bandwidth and (comprised that difference transistor is to M1 and M2, just, the broadband difference transistor to) be as the data reproduction level the commissure differential pair (comprise difference transistor to M3 and M4, just, the commissure difference transistor to).In this embodiment 500, thereby there are two very fast modules [(1) wideband data buffer and (2) commissure differential pair] of running to turn round, postpone the function of cell to realize the variable bandwidth that is suitable for broadband application collaborative.
In order to change delay, can regulate buffer stage and commissure differential pair level electric current (such as, use control module 530).When the electric current of all electric currents by buffer stage and commissure differential pair level current source is closed, circuit just as front explanation and the expansion of quoting the wideband data amplifier of bandwidth (just, the embodiment 100 of Fig. 1 and United States Patent (USP) 6,624 are among the 699B2).The high bandwidth that relies on multiple designing technique to realize can become very little by the delay that postpones cell.In order to increase delay, reduce electric current, and equivalent increases the electric current by commissure differential pair level by buffer stage.Partially full for output signal is realized, it need so just increase delay by being in the regenerative process of the commissure differential pair that will amplify.Based on two step approximation methods, can realize first analysis of the embodiment 500 of this variable delay cell is expressed as follows.
Because the buffer stage of variable delay cell has very high bandwidth, so the delay of this grade from the input to the output is very little.Have reason to suppose that the delay by buffer stage is that relative constant is (with T
bExpression); The delay variation that postpones cell mainly produces (with T in the regenerative process of commissure differential pair level
rExpression).In two step approximation methods, be divided into for two steps by the signal that postpones cell.In the first step, signal V
InBe cushioned in input stage, and postponing T
0After appear at output, its value is for V
mV
mEqual electric current (I by buffer stage
b) multiply by load resistance (R).In second step, be in the signal V of commissure differential pair input
mPositive feedback by the commissure differential pair also obtains regeneration, until postponing T
rAfter reach V
0Voltage V
0Be fixed value, by total current (I
0=I
b+ I
r) and load resistance (V
0=RI
0) decision.
If suppose I
b=xI
0, I so
r=(1-x) I
0The value of X can change between 1 and 0, and x=1 just means that all electric currents are passing through buffer stage.At output, also be simultaneously that the input of commissure differential pair (comprises that difference transistor is to M
3And M
4), postponing T
0After, v
m=xI
0R.The output voltage that it should be noted that regeneration commissure differential pair is along with the time is exponential increase, and is directly proportional with initial voltage, is expressed as follows.
V(t)＝V
m·e
(t/τ)
Here τ is the characteristic time constant of commissure differential pair, is inversely proportional to the gain of commissure differential pair.To the CMOS transistor, its gain is directly proportional with the square root of first bias current, is expressed as follows.
Figure
6 show the embodiment 600 of response buffering level electric current (standardization) by the delay (standardization) of commissure differential pair.This embodiment 600 show by
The normalized delay of commissure differential pair level,
, as buffer stage standardization electric current
Function.Obviously, when the electrorheological by buffer stage hour, the delay by commissure differential pair level becomes big.Total delay by the delay cell is T=T
b+ T
rThereby by changing the electric current distribution (just, comprising the value that changes x) between buffer stage (comprising that difference transistor is to M1 and M2) and the commissure differential pair level (comprising that difference transistor is to M3 and M4), control lag amount at an easy rate.
To two electric current I
bAnd I
rAnd the control of correlation, can use control module (such as, the control module 530 among the embodiment 500 of Fig. 5) to carry out.It should be noted that the total current (I that requires among the embodiment 500
0=I
b+ I
r) keep constant, but have only two electric current I
bAnd I
rBetween relation controlled, thereby control total delay.For example, the variable delay of delay cell with variable can be by regulating first electric current I of first variable current source
bSecond electric current I with second variable current source
rIn at least one control.The variable delay of this controlled delay cell with variable can be counted as first electric current I of first variable current source
bDivided by the second electric current sum of first electric current and second current source of first current source (such as, total current (I
0=I
b+ I
r)) function of the ratio that obtains.In addition, because this total current (I
0=I
b+ I
r) remain unchanged, so the direct current level of the delay cell that is produced by load resistance also remains unchanged.
When the value of x levels off to 1 the time, the total delay of variable delay cell (such as, the embodiment 500 among Fig. 5) levels off to the delay of (comprising that difference transistor is to M1 and M2) of wideband data buffer.When the value of x levels off to 0 the time, the total delay of variable delay cell (such as, the embodiment 500 among Fig. 5) levels off to and has comprised that wideband data buffer (comprising that difference transistor is to M1 and M2) and commissure difference transistor postpone the equipment maximum possible of two kinds of delays of (comprise difference transistor to M3 and M4).
Here the of the present invention various embodiment that illustrate be a large amount of imminent delays (these postpone according in the multiple application any one to require be also to be variable optionally) provide the signal quality of minimum to reduce (such as, intersymbol interference minimum or do not have intersymbol interference).
One of numerous advantages of this novel designs are that all above-mentioned, relevant with the wideband data amplifying circuit that has enlarged bandwidth bandwidth expansion techniques can both easily be applied to the variable delay cell.In the embodiment 500 of Fig. 5, series connection input inductance L1 and L2, shunt peaking inductance L 3 and L4, negative miller capacitance C1 and C2 are coupled with, and make like this to have comprised that difference transistor can be with the minimum increase realization high bandwidth of energy to this one-level of M1 and M2.Along with the bandwidth increase of buffer stage, the lower limit of length of delay reduces, thereby the variable delay scope increases but can not influence signal integrity.In addition, along with buffer stage becomes faster than commissure differential pair level, the prediction of two step approximation methods becomes more accurate.
By removing binary channels (as described in the embodiment 400 of Fig. 4), the embodiment 500 of Fig. 5 shows the comprehensive delay cell that does not need summing stage thereby significantly reduced energy.At input, there is not extra capacitive load to be added on the high-speed channel.Because the additional capacitor of the drain electrode of the commissure differential pair transistors of output can easily be compensated by shunt inductance.As a result, can not influence signal integrity among the data channel or reduce impedance matching with regard to easier full stage is attached to.
Can know from the embodiment 500 of Fig. 5 and to see, can continue to change retardation by two current sources being implemented Sustainable Control (just, using control module 530).Also can pass through two current source (I
bAnd I
r) substituting the easily programmable delay cell of realization with the less current source of one group of series connection, each can both carry out switch with digital control signal in these series current sources.
In a word, having showed here the broadband integrated postpones the fully differential current-controlled cmos (C3MOS) of cell.In buffer stage, bandwidth expansion technique can easily be used such as shunt peaking, series inductance peaking, to increase the scope of level and smooth frequency domain response.Commissure differential pair level has been added in the output of buffer, with by being connected the right regeneration process of commissure difference transistor in a kind of positive feedback configuration, increases the delay from the input to the output.Delay can distribute by the electric current that changes buffer stage and commissure differential pair level to be regulated.Integrated delay cell can provide a large amount of delays, simultaneously for data channel keeps high bandwidth, and can not increase load to input, also can not increase energy consumption.
It should be noted that, the method of in former figures, describing also can any suitable system and/or device design (communication system, communications transmitter, communication sink, communication transceiver and (or) wherein illustrated functional) in realize, and can't depart from scope and spirit of the present invention.
Because above detailed description of the invention and accompanying drawing, it is obvious that other modifications and variations will become.In addition, can make this other modifications and variations, and not depart from scope and spirit of the present invention.
Claims (8)
1, a kind of current-controlled cmos delay cell with variable bandwidth is characterized in that, comprising:
First difference transistor comprises first source electrode, first grid, first drain electrode;
Second difference transistor comprises second source electrode, second grid, second drain electrode;
First current source is connected to first source electrode of first difference transistor and second source electrode of second difference transistor;
First input impedance is connected between the first grid of first differential input end of current-controlled cmos delay cell with variable bandwidth and first difference transistor;
Second input impedance is connected between the second grid of second differential input end of current-controlled cmos delay cell with variable bandwidth and second difference transistor;
First output impedance comprises first output resistance connected in series and the first shunt peaking inductance, and first output impedance is connected between first drain electrode and supply voltage of first difference transistor;
Second output impedance comprises second output resistance connected in series and the second shunt peaking inductance, and second output impedance is connected between second drain electrode and supply voltage of second difference transistor;
The 3rd difference transistor comprises the 3rd source electrode, the 3rd grid and the 3rd drain electrode;
The 4th difference transistor comprises the 4th source electrode, the 4th grid and the 4th drain electrode;
Second current source is connected to the 3rd source electrode of the 3rd difference transistor and the 4th source electrode of the 4th difference transistor;
Wherein first of first difference transistor drain electrode is connected with the second grid of second difference transistor, and second drain electrode of second difference transistor is connected with the first grid of first difference transistor;
Wherein the 3rd drain electrode of first of first difference transistor drain electrode, the 3rd difference transistor and the 4th grid of the 4th difference transistor can connect communicatedly;
Wherein the 4th drain electrode of second of second difference transistor drain electrode, the 4th difference transistor and the 3rd grid of the 3rd difference transistor can connect communicatedly.
2, circuit according to claim 1 is characterized in that, also comprises:
First electric capacity is connected between first drain electrode and the second grid of second difference transistor of first difference transistor; And
Second electric capacity is connected between second drain electrode and the first grid of first difference transistor of second difference transistor.
3, circuit according to claim 1 is characterized in that, first input impedance comprises the first polyphone inductance; Second input impedance comprises the second polyphone inductance.
4, circuit according to claim 1 is characterized in that, first output resistance of first output impedance is connected between first drain electrode and the first shunt peaking inductance of first output impedance of first difference transistor; And
The first shunt peaking inductance of first output resistance is connected between first output resistance and supply voltage of first output impedance.
5, circuit according to claim 1 is characterized in that, first current source is first current source transistor;
Second current source is second current source transistor; And
First difference transistor, second difference transistor, the 3rd difference transistor, the 4th difference transistor, first current source transistor and second current source transistor are the N channel metal oxide semiconductor transistors.
6, circuit according to claim 1 is characterized in that, first current source is first current source transistor;
Second current source is second current source transistor; And
First difference transistor, second difference transistor, the 3rd difference transistor, the 4th difference transistor, first current source transistor and second current source transistor are the P-channel metal-oxide-semiconductor transistors.
7, a kind of current-controlled cmos delay cell with variable bandwidth is characterized in that, comprising:
First difference transistor comprises first source electrode, first grid and first drain electrode;
Second difference transistor comprises second source electrode, second grid and second drain electrode;
First current source is connected to first source electrode of first difference transistor and second source electrode of second difference transistor;
First series inductance is connected between the first grid of first difference input of current-controlled cmos delay cell with variable bandwidth and first difference transistor;
Second series inductance is connected between the second grid of second difference input of current-controlled cmos delay cell with variable bandwidth and second difference transistor;
First output impedance, first output resistance and the first shunt peaking inductance that comprise series connection, first output resistance is connected between the drain electrode and the first shunt peaking inductance of first difference transistor, and the first shunt peaking inductance is connected between first output resistance and the supply voltage;
Second output impedance, second output resistance and the second shunt peaking inductance that comprise series connection, second output resistance is connected between the drain electrode and the second shunt peaking inductance of second difference transistor, and the second shunt peaking inductance is connected between second output resistance and the supply voltage;
First electric capacity is connected between the grid of the drain electrode of first difference transistor and second difference transistor;
Second electric capacity is connected between the grid of the drain electrode of second difference transistor and first difference transistor;
The 3rd difference transistor comprises the 3rd source electrode, the 3rd grid and the 3rd drain electrode;
The 4th difference transistor comprises the 4th source electrode, the 4th grid and the 4th drain electrode;
Second current source is connected to the 3rd source electrode of the 3rd difference transistor and the 4th source electrode of the 4th difference transistor;
Wherein, the 3rd drain electrode of first of first difference transistor drain electrode, the 3rd difference transistor can be connected communicatedly with the 4th grid of the 4th difference transistor; And
Wherein, the 4th drain electrode of second of second difference transistor drain electrode, the 4th difference transistor can be connected communicatedly with the 3rd grid of the 3rd difference transistor.
8, circuit according to claim 7 is characterized in that, first current source is first variable current source;
Second current source is second variable current source; And
In first electric current by regulating first variable current source and second electric current of second variable current source at least one, the variable delay of Control current control CMOS delay cell with variable bandwidth.
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| Application Number | Priority Date | Filing Date | Title |
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| US71481405P | 2005-09-06 | 2005-09-06 | |
| US60/714,814 | 2005-09-06 | ||
| US11/320,401 | 2005-12-28 |
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| US10313165B2 (en) * | 2017-03-08 | 2019-06-04 | Credo Technology Group Limited | Finite impulse response analog receive filter with amplifier-based delay chain |
| CN111342835A (en) * | 2020-02-27 | 2020-06-26 | 成都泰格微电子研究所有限责任公司 | SERDES module for JESD204B interface |
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