CN100468970C - Output driver impedance controller and its integrated circuits and control method - Google Patents
Output driver impedance controller and its integrated circuits and control method Download PDFInfo
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Abstract
An output driver impedance controller for controlling pull-down impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one output driver coupled to a corresponding output, and an impedance matching controller. The programmable reference impedance generator develops a reference impedance controlled by a reference impedance control input. Each output driver includes a programmable output impedance generator coupled to an output and controlled by an output impedance control input. The impedance matching controller continually adjusts the reference impedance control input to match the reference impedance with the reference value within a predetermined tolerance and generates the output impedance control input based on the reference impedance control input. Each of the programmable generators may be implemented with a binary array of matched impedance devices. The reference value may be an externally coupled resistor and/or an internal reference resistor.
Description
Technical field
The present invention is relevant for a kind of integrated circuit (IC) output driving circuit, especially refer to a kind of impedance controller relevant for output driver (output driver impedance controller) and integrated circuit and control method, it can accurately be used for the pull-down impedance of the output of control IC.
Background technology
In integrated circuit (IC) design early, the CMOS output driver is configured to push-pull type (push-pull) element.Therefore, the noise of being seen on the output bus can respond various factors (comprise on circuit temperature, supply voltage, preparation technology's difference, the bus component number etc.) and change significantly.In recent years, because technical development has caused dwindle (scaling) of component size and level, thus forced the designer to handle noise problem on the external bus energetically, so that the running speed of intrasystem circuit reaches maximum.
It is the differential receiver configuration from push-pull type output configuration change that a viewpoint in the nearest output driver settling mode has made industry.In the differential receiver configuration, a side of differential receiver is supplied with a reference voltage, and opposite side is driven by an open drain N pass element.This open drain N pass element is positioned on the chip, and (termination) generally is positioned at the outside and draw terminal impedance on the bus, is usually located on system host board or the similar thing.Will on when drawing terminal impedance to be positioned at can to make on the motherboard system designer to handle not treatable so far bus noise problem, have elasticity to a certain degree.
In industry, it is very in vogue that the pattern of above-mentioned output driver has become.A kind of significant especially example during this kind is in vogue is shown by Pentium II x86 microprocessor (product of Intel company).Pentium II uses open drain N passage output element, drives the 1.5V bus with 1.0 volts of (V) critical reference voltages.About the motherboard of this processor generally can use 56 ohm on draw terminal impedance.Though also do not specify specific pull-down impedance, used the open drain output driver, switch and the sequential specification to meet bus.Yet, preparation technology, voltage and variations in temperature are not compensated, can make any place of the aisle resistance of an open drain N passage output driver change to 80 ohm from 4 ohm approximately.And because the designer of microprocessor can only consider the tolerance interval of preparation technology, voltage and temperature change in advance, be added to output signal line so forced the design of the compatible motherboard of Pentium-II that the rate of change (slew rate) of 2-3 nanosecond (ns) grade is controlled, to reduce the noise on the output bus.
In Pentium-III, Intel introduces a kind of mechanism, can provide the reference impedance of the impedance that can be used to set the output driver on the bus to the designer by this mechanism.Pin (being called NCHCTRL) in the processor encapsulation is connected to bus voltage (being called VTT) via 14 Ohmic resistances (maximum appointment resistance value is 16 ohm) of a precision.Precision resistance is external in microprocessor chip, therefore with chip on output driver temperature and the change in voltage seen irrelevant.
Summary of the invention
Goal of the invention of the present invention provides accurately impedance controller and the integrated circuit and the control method of the output driver of the pull-down impedance of the output of control IC.
One embodiment of the invention has disclosed a kind of impedance controller of output driver, and it controls the pull-down impedance of at least one output based on a reference value.This controller comprises a programmable reference impedance generator, at least one output driver, and it is coupled to the output and an impedance matching controller of a correspondence.This programmable reference impedance generator for generating one reference impedance, this reference impedance is controlled by reference impedance control input.Each output driver comprises a programmable impedance output generator, and this programmable impedance output generator is coupled to an output, and is controlled by output impedance control input.This impedance matching controller is imported in order to continue adjusting this reference impedance control, so that the reference values match in this reference impedance and the predetermined nargin, and can control input and produce this output impedance based on this reference impedance control input.This impedance matching controller comprises a voltage-sensor and logic impedance controller.This voltage-sensor is in order to the reference voltage of sensing based on an input bus voltage, and the voltage differences between the voltage of this programmable reference impedance generator, and can make an error signal activation of its demonstration.This logic impedance controller is adjusted this reference impedance control input based on this error signal.
In another embodiment, programmable reference impedance generator and each programmable impedance output generator include a binary array of mutual impedance for matching element, as the N pass element of mutual coupling.In this embodiment, this reference value is a reference resistance of connecting with this programmable reference impedance generator, and input bus voltage can apply and is connected across on this tandem compound.
Another feature of the present invention provides logic bias voltage adjuster, in order to a bias amount is combined with this reference impedance control input, imports and produce this output impedance control.Also can comprise logic output bias device, in order to produce this bias amount, as programmable fuse or similar elements.
A feature more of the present invention is that this impedance matching controller can comprise one first controller and one second controller.This first controller is coupled to an external reference resistance, in order to produce one first reference value.This second controller comprises an internal reference resistance, in order to produce one second reference value.In this case, this first controller also can comprise the logic detection device, and whether this logic detection device couples to judge this first reference value, and if do not couple this first reference value, then can make this second controller activation in order to monitor this reference impedance control input.
One embodiment of the invention has disclosed a kind of integrated circuit (IC) of impedance controller of output driver, it comprise one first with reference to pin in order to receive a reference voltage, at least one output connecting pin, at least one output driver and logic impedance matching box.Each output driver comprises a programmable impedance output generator.This programmable impedance output generator is controlled by output impedance control input, and couples in order to drive the output connecting pin of a correspondence.This logic impedance matching box comprises a programmable reference impedance generator, logic comparator and logic follower.This programmable reference impedance generator is controlled by reference impedance control input; This logic comparator is in order to continue adjusting this reference impedance control input, so that in a predetermined nargin, is coupled to this and first equates with reference to the value in the reference resistance of pin and this programmable reference impedance generator.This logic follower is controlled this output impedance control input based on this reference impedance control input.This logic comparator comprises a voltage-sensor and logic impedance controller.This voltage-sensor is coupled to this first with reference to pin and this programmable reference impedance generator, in order to detecting the voltage of this reference resistance of cross-over connection and this programmable reference impedance generator, and can make an error signal activation of its demonstration.This logic impedance controller is adjusted this reference impedance control input based on this error signal.
Another feature of the present invention is that this reference voltage can apply in the series connection coupling that is connected across this reference resistance and this programmable reference impedance generator.In this case, this logic comparator attempts to make the voltage in the predetermined voltage nargin to equate.This IC also can comprise one second with reference to pin, and this second is coupled to this programmable reference impedance generator with reference to pin one end, and the other end is coupled to an end of an external reference resistance, and the other end of this external reference resistance is coupled to this first with reference to pin.
Another feature of the present invention is to be that its IC also can comprise an internal reference resistance.This programmable reference impedance generator can comprise by one first reference impedance control input controls and is coupled to this second one first programmable reference impedance generator with reference to pin, and the one second programmable reference impedance generator of being controlled and be coupled to second end of this internal reference resistance by one second reference impedance control input.In this case, this logic comparator can comprise first logic comparator and second logic comparator.First logic comparator in order to adjusting this first reference impedance control input, equates to attempt to make this external reference resistance in one first nargin and the voltage of this first programmable reference impedance generator.Second logic comparator in order to adjusting this second reference impedance control input, equates to attempt to make this internal reference resistance in one second nargin and the voltage of this second programmable reference impedance generator.This IC also can comprise the logic detection device, and this logic detection device is in order to monitoring this first reference impedance control input, in order to detecting the existence of this external reference resistance, and can produce an activation signal of its demonstration.This logic follower is selected in this first reference impedance control input and this second reference impedance control input one based on this enable signal, to produce this output impedance control input.
Another this IC that is characterised in that of the present invention also can comprise logic output bias device, in order to produce an adjusted value, wherein this logic follower comprises logic bias voltage adjuster, in order to this reference impedance control input is combined with this adjusted value, imports and produce this output impedance control.
The present invention also can provide a kind of method of controlling the pull-down impedance of at least one output driver, it comprises and applies a reference voltage to a reference resistance, and a reference impedance generator with reference impedance input, periodically adjust this reference impedance input, so that the impedance of this reference impedance generator equates with this reference resistance of being scheduled in the nargin, and control the output impedance input of at least one output impedance generator based on this reference impedance input, wherein each output impedance generator is coupled to a corresponding output driver.
Above-mentioned method provided by the invention also can comprise this reference impedance generator of sensing and this reference resistance of connecting with this reference voltage one connect the voltage of face jointly, and will connect the voltage of face jointly and half of this reference voltage compares.The method also can comprise provides an internal reference resistance, detects an external reference resistance and produces the enable signal of its demonstration, and based on enable signal, select and do one between this internal reference resistance and this external reference resistance.Periodically adjusting this reference impedance input can implement digital value increase or reduction by during the selection cycle of a clock signal.
Above-mentioned method provided by the invention also can comprise bias voltage adjusted value programming, wherein controls output impedance input and comprises this bias voltage adjusted value is combined with the input of this reference impedance.The method also can comprise based on an output enable signal, and make each output driver activation or forbidden energy.The method also can comprise based on this reference impedance input, and make several selected binary array activations in the mutual matched impedance element of reference impedance generator, and based on this output impedance input, and make several selected binary array activations in the mutual matched impedance element of each output impedance generator.
The impedance controller of output driver of the present invention and integrated circuit thereof, control method are insensitive for the change of variation of temperature, voltage, making technology etc., thereby can be used for the output of accurate control IC.
Description of drawings
Fig. 1 is the simplification calcspar according to an integrated circuit (IC) of the impedance controller that comprises an output driver of one example of the present invention embodiment;
Fig. 2 is the more detailed calcspar according to the logic impedance matching box among Fig. 1 of one example of the present invention embodiment;
Fig. 3 is the schematic diagram of the impedance generator 300 implemented according to one example of the present invention embodiment, its can be used to be used as in the impedance generator of Fig. 2 any or the two;
Fig. 4 is the schematic diagram according to an exemplary embodiment of each output driver among Fig. 1 of the present invention; And
Fig. 5 is the flow chart according to the method for the pull-down impedance of at least one output driver of control of one example of the present invention embodiment.
Wherein, description of reference numerals is as follows:
101: integrated circuit (IC) 103: logic impedance matching box
105:6 position internal bus 107: a plurality of output drivers
109: logic output bias device 110: fuse
201:R controller 203:NR controller
205,211: voltage-sensor 207,213,300: impedance generator
209,215: logic impedance controller 210: the logical zero detector
217: logic bias voltage adjuster
301,401: the second array groups
303,403: the tri-array groups
305,405: the four array groups
307,407: the five array groups
309,409: the six array groups
311: buffer
411: buffer 413,415,417,419,421,423: with door
501,503,505,507,509,511,513,515,517: step
Embodiment
Below explanation will make those skilled in the art can finish and use the present invention, be provided in this paper as application-specific and demand thereof.Yet, to those skilled in the art, will be to belong to conspicuous to the various modifications of preferred embodiment, and can be applicable to other embodiment in this defined rule.Therefore, the present invention is not intended to be subject to the specific embodiment of and explanation shown at this, but meets the principle that discloses at this and the widest scope of novelty.
The present inventor has known from experience and has recognized relevant accurate bus pull-down impedance, and the market demand of reference of using external coupling resistance to be used as to set the pull-down impedance of open drain N passage output driver.Therefore, it has developed the impedance controller (output driver impedance controller) that a kind of meeting offers impedance the output driver of bus, its change for temperature, voltage, manufacturing variation etc. is insensitive, and existing 1-5 in conjunction with the accompanying drawings is further described.
See also the simplification calcspar of an integrated circuit (IC) 101 of the impedance controller that comprises an output driver according to one example of the present invention embodiment shown in Figure 1.Wherein IC 101 comprises many external I/O (I/O) pins that can be used for, comprise bus voltage input pin VTT, N passage control pin NCHCTRL and be shown as OUT1, OUT2 ..., a plurality of output connecting pins of OUTN, wherein N is a positive integer.Being positioned on the pin VTT in order to the external voltage signal VTT that produces a reference bus level, for example is 1.5 volts (V).In one embodiment, a selectable external reference resistance R EXT who shows with dotted line is coupled between pin VTT and the NCHCTRL.If resistance R EXT is not provided, then can use an internal resistance RINT to replace, be used as preset reference resistance, as further instruction hereinafter.In a specific embodiment, resistance R EXT is 14 ohm, and can be a precision resistance or similar resistance (for example, 1% resistance).In this specific embodiment, resistance R INT also is 14 ohm a precision resistance.
This IC 101 comprises logic impedance matching box 103, and it is in order to the reference resistance of monitoring selection and the impedance of internal driving generator.In shown embodiment, logic impedance matching box 103 is in order to the level of monitoring pin VTT and NCHCTRL.103 meetings of logic impedance matching box are with 6 bit digital value OSUM[5:0 on 6 internal buss 105] be sent to a plurality of output drivers 107 that are positioned on the IC 101, wherein output driver 107 can individually be numbered from 1 to N.Each other output driver 107 can be coupled to a corresponding output connecting pin, individually be shown as OUT1, OUT2 ..., OUTN.In each output driver 107, OSUM[5:0] each meeting in the value makes has the common drain point, and be used for driving the array activation/forbidden energy of the N pass element that a group of the correspondence of corresponding OUTx pin (wherein " x " for from 1 to the N of the specific output connecting pin of representative number) mates mutually.OSUM[5:0] value is to limit by the output enable signal OEN with state of setting according to the output state of the hope of output driver.The OEN signal is to produce by element logic (not shown), in order to set the output state signal of corresponding output connecting pin OUTx, wherein output signal is identical with the title hypothesis of output connecting pin, that is, output connecting pin OUT1 can show output signal OUT1 separately, and output connecting pin OUT2 can show output signal OUT2 etc.When the OUT of correspondence signal is logic low, OSUM[5:0] be worth and can specify in each output driver 107, be about to the number of the open drain N pass element of unlatching (activation).In one embodiment, 6 buses 105 can be with the steps of 64 equal intervals, and can adjust the impedance of output driver.
In when running, logic impedance matching box 103 can keep a partial binary array of the N pass element of coupling mutually, and it is identical with binary array in each output driver 107 in fact.Each array can dispose or be divided into the binary system group that is used for digital output impedance control, as further instruction hereinafter.Can continue to monitor the impedance of the partial binary array in the logic impedance matching box 103, and can increase or downgrade OSUM[5:0] value, so that the voltage of cross-over connection local array is positioned at the predetermined tolerance that the voltage of reference resistance (it is resistance R EXT or resistance R INT) is selected in cross-over connection.In one embodiment, predetermined tolerance is the error voltage of about 50 millivolts (mV).If do not connect resistance R EXT, so that cross-over connection do not exist in the voltage of pin VTT and NHCTRL, and then logic impedance matching box 103 can use resistance R INT to replace, and is used as the reference of the impedance of setting output driver 107.In one embodiment, per two cycles of a bus clock (INT BCLK) can determine the optimum impedance of output driver 107, and obviously can upgrade output driver 107.
Logic output bias device 109 usefulness are so that be positioned at OSUM[5:0 on the bus 105] value adds or deducts bias voltage.Be sent to one 4 place value ADD[3:0 of logic impedance matching box 103 from logic output bias device 109] in order to identification OSUM[5:0] the value quantity that will add or deduct.A control signal SUBEN who is sent to logic impedance matching box 103 by logic output bias device 109 can determine whether will add (when not activation of SUBEN) or deduct this quantity (when the SUBEN activation).In one embodiment, OSUM[5:0] value can directly will add (for example, when SUBEN be logical zero or not activation) or directly deduct (for example, when SUBEN be logical one or activation) ADD[3:0] value.In another embodiment, OSUM[5:0] value can be according to ADD[3:0] value and signal SUBEN and increase proportionally or reduce.For example, if ADD[3:0] be set in 1000b (binary system) and not activation of signal SUBEN, then OSUM[5:0] can increase with 50 percent.
In a specific embodiment, logic output bias device 109 comprises, or programmes by the one group of fuse 110 that is contained on the IC 101.For example, the programming state of this group fuse 110 decides by test program or similar program based on one one one one.This group in fuse 110 almost each corresponding to OSUM[5:0] value than low level.In this way, the fuse that blows selection can make the designer increase or reduce OSUM[5:0] value.Therefore, if want, logic output bias device 109 can change the controlling mechanism of output level for a kind of designer of making.In one embodiment, logic output bias device 109 is used for the output of correspondence is produced more or less noise immunity.
Fig. 2 is the more detailed calcspar according to the logic impedance matching box 103 of one example of the present invention embodiment.Logic impedance matching box 103 comprises R controller 201 and NR controller 203, and its two controller is similar in fact.R controller 201 and NR controller 203 all have the INT of reception BCLK signal.R controller 201 comprises a voltage-sensor 205, and in order to the voltage of monitoring pin VTT and NCHCTRL, wherein NCHCTRL is shown as signal INPA partly.Signal INPA can be sent to the impedance generator 207 that is referenced to earth terminal, and impedance generator 207 is based on an input controlling value RSUM[5:0] and impedance between shows signal INPA and the earth terminal.Voltage-sensor 205 can be effectively with the voltage between pin VTT and the NCHCTRL, compare to the voltage of earth terminal with pin NCHCTRL, and produce signal HI and the LO deliver to logic impedance controller 209, equate with level in the predetermined tolerance attempting.Logic impedance controller 209 meeting increase/reduction RSUM[5:0] value, with the impedance of control group generator 207, the INPA in VTT-INPA=predictive error voltage (or so that the voltage of signal INPA is half of voltage VTT).In other words, suppose that resistance R EXT is external, voltage-sensor 205 and logic impedance controller 209 can cooperate, and equates with the voltage of the resistance R EXT in the voltage of attempting to make transimpedance controller 207 and the cross-over connection predictive error voltage.
As resistance R EXT when being external, VTT source voltage is dividing potential drop by the impedance of resistance R EXT and impedance generator 207, and the corresponding voltage on the signal INPA is provided.If the voltage of signal INPA too high (impedance too high (or greater than REXT) of expression impedance generator 207), then voltage-sensor 205 can make the activation of HI signal, and makes the LO invalidating signal.Logic impedance controller 209 can be by increasing RSUM[5:0] value responds, with the value of reduction impedance generator 207.When the impedance of impedance generator 207 was too low, voltage-sensor 205 can make the activation of LO signal, and can make the HI invalidating signal.Logic impedance controller 209 can be by reducing RSUM[5:0] value responds, with the increase resistance value.In the embodiment of shown and explanation, though also consider proportionate relationship, RSUM[5:0] impedance of value and impedance generator 207 is inversely proportional to.
In one embodiment, voltage-sensor 205 comprises a pair of sensing amplifier (not shown), and it has the Voltage Reference device that is separated by the predictive error voltage relevant with the half voltage of voltage VTT.In this case, high sensing amplifier is set half that is about above the error voltage of 1/2VTT, and in order to control HI signal, low sensing amplifier is set at half of the error voltage that is lower than 1/2VTT, in order to control LO signal.Each sensing amplifier can be relatively more relevant with its set point the voltage of signal INPA.If the voltage of signal INPA rises to above error voltage half, then can make the HI activation, if the voltage of signal INPA drops to half that is lower than error voltage, then can make the LO activation, and if the voltage of signal INPA is positioned at half of error voltage of 1/2VTT, then can not make HI or LO activation, and can not take action.One more in the certain embodiments, predictive error voltage is about 50mV, be about above 1/2VTT25mV so that high sensing amplifier is set, and low sensing amplifier is set to be about and is lower than 1/2VTT25mV.The strict tolerance that is used for higher accuracy can be set in the gap of error voltage, or is set at quite wide tolerance, to save power.
In one embodiment, the digital circuit of logic impedance controller 209 for being controlled by signal INT BCLK, and during the selection cycle of signal INT BCLK (as each clock cycle or every a clock cycle etc.) can adjust (for example, increase or reduce) RSUM[5:0] value.
R controller 201 also comprises logical zero detector 210, and it is in order to receive RSUM[5:0] value, and provide a signal NR EN to logic bias voltage adjuster 217 and NR controller 203.When logical zero detector 210 detects RSUM[5:0] value representation when not placing resistance R EXT, then signal NR EN can activation, and makes 203 activations of NR controller.In this shown embodiment, if do not connect resistance R EXT, then signal NCHCTRL can be tending towards the suspension joint low level near the earth terminal level, and makes voltage-sensor 205 continue to make the activation of LO signal.Logic impedance controller 209 is by repeatedly reducing RSUM[5:0] value, to attempt to increase the impedance of impedance generator 207, to increase the voltage of signal INPA.And because signal INPA still tends to zero, so RSUM[5:0] value can reduce to zero and (for example, 000000b), and make logical zero detector 210 with signal NR EN activation, and make 203 activations of NR controller effectively, and make R controller 201 forbidden energy.
NR controller 203 comprises voltage-sensor 211, impedance generator 213 and logic impedance controller 215, and it is identical with voltage-sensor 205, impedance generator 207 and logic impedance controller 209 in fact, and running in fact in an identical manner.Yet in this case, pin VTT can be connected to an end of voltage-sensor 211 and resistance R INT (it has the other end of a signal INPB of delivering to the other end of voltage-sensor 211 in order to generation).Logic impedance controller 215 can produce a controlling value NRSUM[5:0], and deliver to impedance generator 213.In this case, voltage-sensor 211 and logic impedance controller 215 can cooperate, and attempting with as R controller 201 described similar manners, and the voltage of the interior resistance R INT of the voltage that makes transimpedance generator 213 and cross-over connection predictive error voltage equates.
RSUM[5:0] value, NRSUM[5:0] value and signal NR EN can be sent to the RSUM[5:0 of logic bias voltage adjuster 217 respectively], NRSUM[5:0] and SEL NR input.Signal INT BCLK and SUBEN and ADD[5:0] value also can be sent to logic bias voltage adjuster 217.Signal NR EN can indicate logic bias voltage adjuster 217, uses 6 summations (SUM) value come from R controller 201 (for example, RSUM[5:0]) or comes from 6 total value (for example, NRSUM[5:0]) of NR controller 203.During the selection cycle of clock signal INT BCLK (as every a clock cycle or similar clock cycle), logic bias voltage adjuster 217 also can be based on ADD[3:0] value and control signal SUBEN adjust the value of the total value that (for example, increase or reduce) select.As discussed previously, in one embodiment, the total value of selection can add or deduct ADD[3:0] value, and in another embodiment, the total value of selection can be according to ADD[3:0] value and increase proportionally or reduce.Final result can come activation by logic bias voltage adjuster 217, and is used as the OSUM[5:0 on the bus 105 of IC 101] value.In this way, OSUM[5:0] value is RSUM[5:0] and NSUM[5:0] be worth both one of a bias voltage adjust form.
Fig. 3 is the schematic diagram of the impedance generator 300 implemented according to one example of the present invention embodiment, its can be used to be used as in the impedance generator 207,213 any or the two.Impedance generator 300 comprises the binary array of 63 N pass element N1-N63 (or N63:N1).In one embodiment, each N pass element N63:N1 is coupling mutually, so that the impedance of drain-to-source in fact can be identical.The source electrode of each element N63:N1 is coupled to earth terminal, and its drain electrode is coupled to a signal INP, and signal INP represents the signal INPA of impedance generator 207 or the signal INPB of impedance generator 213.Element N63:N1 is binary system ground grouping, with corresponding binary system resistance value SUM[5:0] in six positions of (its representative comes from the RSUM[5:0 of impedance generator 207] be worth or come from the NRSUM[5:0 of impedance generator 213] value) each.One first array group is single element N1, it has in order to receive the grid of a signal NS0, one second array group 301 comprises two element N2 and N3 (N3:N2), each element has in order to receive the grid of a signal NS1, one tri-array group 303 comprises four element N4-N7 (N7:N4), each element has in order to receive the grid of a signal NS2, one the 4th array group 305 comprises eight element N8-N15 (N15:N8), each element has in order to receive the grid of a signal NS3, one the 5th array group 307 comprises 16 element N16-N31 (N31:N16), each element has in order to receive the grid of a signal NS4, and one the 6th array group 309 comprise 32 element N32-N63 (N63:N32), each element has in order to receive the grid of a signal NS5.
Signal NS5-NS0 can constitute the binary value NS[5:0 by buffer 311 (it is in order to receive SUM[5:0] value) institute's activation].NS[5:0] each position in the value be SUM[5:0] the buffering form of correspondence in the value.For example, buffering SUM5 position, and produce the NS5 position; Buffering SUM4 position, and produce NS4 position or the like.Therefore, as SUM[5:0] when being worth lifting or increase, the impedance meeting of signal INP reduces, and vice versa.For example, the SUM[5:0 of 100000b] value can make 309 activations of array group, half element (or 32) of array group these a plurality of N pass elements of 30 coupled in parallel, and the SUM[5:0 of 100001b] value can make N1 of array group and 309 activations, 33 elements in these a plurality of N pass elements of N1 of array group and 309 coupled in parallel, and the SUM[5:0 of 100010b] value can make array group 301 and 309 activations, in array group 301 and the 309 coupled in parallel N pass elements 34, by that analogy.The SUM[5:0 of 000000b] value can close all N pass elements and be a high impedance status, and the value of 111111b can make all 63 N pass elements activations and be a lowest impedance level.In one embodiment, the array of element N63:N1 can be arranged and grouping by size, and the generation scope is from about 4 to 24 ohm pull-down impedance, with reserving margin so that the preparation technology of operating temperature and bus voltage situation and consideration in advance changes in the scope of expection.
Fig. 4 is the schematic diagram according to an exemplary embodiment of each output driver 107 of the present invention.Output driver 107 comprises the array of 63 N pass element N63:N1, and it is implemented in the mode identical with the element N63:N1 of each impedance generator 207 and 213 in fact and the grouping of binary system ground.N pass element N63:N1 is coupling mutually, and each element comprises the source electrode that is coupled to earth terminal, and the drain electrode that is coupled to an output signal OUT (any among the output connecting pin OUT1-OUTN of corresponding output driver 1-N implemented in its representative).As shown in Figure 4, one first array group comprises element N1, one second array group 401 comprises two element N3:N2, one tri-array group 403 comprises four element N7:N4, one the 4th array group 405 comprises eight element N15:N8, one the 5th array group 407 comprises 16 element N31:N16, and one the 6th array group 309 comprises 32 element N63:N32.
OSUM[5:0 on the bus 105] value can be sent to each output driver of the output driver 107 on the IC 101, and be positioned at each output driver 107, and be sent to buffer 411.Buffer 411 disposes in the mode identical with buffer 311 in fact, and can output valve S[5:0], wherein come from the S[5:0 of buffer 411] each position of value is OSUM[5:0] the buffering form of correspondence in the value.Each signal in the signal of S0-S5 position can be sent to an input of two inputs and door 413,415,417,419,421 and 423 corresponding array respectively.With among the door 413-423 each can received signal OEN with another input of door.Be coupled to the grid of element N1 with the output of door 413, be coupled to the grid of element N3:N2 with the output of door 415, be coupled to the grid of element N7:N4 with the output of door 417, be coupled to the grid of element N15:N8 with the output of door 419, be coupled to the grid of element N31:N16 with the output of door 421, and be coupled to the grid of element N63:N32 with the output of door 423.
When the activation of signal OEN low level is logical zero, because all N pass elements are for closing, so the signal OUT of the output of output driver 107 can be in high impedance status.When the activation of signal OEN high level was logical one, then output driver 107 can operate in the mode identical with impedance generator 300 in fact.In this kind situation, the number of the N pass element of coupled in parallel can respond the OSUM[5:0 of reduction (or increase)] value and reduce (or increasing), like this, can effectively increase the impedance that (or reduction) puts on signal OUT.
Sum up and with reference to logic impedance matching box 103 shown among the figure 2, when resistance R EXT was external between pin NCHCTRL and the VTT, then R controller 201 can be adjusted RSUM[5:0] value, the impedance that has the resistance value that is about resistance R EXT up to impedance generator 207.Logic bias voltage adjuster 217 is by signal SUBEN and ADD[3:0] the shown quantity of value adjusts RSUM[5:0] value, and the OSUM[5:0 that bias voltage is adjusted] the value activation.In addition, if do not connect resistance R EXT, then NR controller 203 can be adjusted NRSUM[5:0] value, the impedance that has the resistance value that is about resistance R INT up to impedance generator 213.Logic bias voltage adjuster 217 is by signal SUBEN and ADD[3:0] the shown quantity of value adjusts NRSUM[5:0] value, and the OSUM[5:0 that bias voltage is adjusted] the value activation.Refer back to IC shown among Fig. 1 101, OSUM[5:0] value is distributed in all output drivers 107, and wherein each output driver 107 is with in fact with the impedance generator 207 of N pass element and 213 same way as and the coupling N pass element that binary system ground distributes disposes.Therefore, the impedance that puts on each OUTN signal equates with reference resistance REXT or RINT approximately.
Fig. 5 is the flow chart of expression according to the method for the pull-down impedance of at least one output driver of control of one example of the present invention embodiment.At first square 501, the expression meeting is with the bias voltage adjusted value programming of selecting for use.In specific IC embodiment as discussed previously, the fuse that blows the selection that is contained in IC 101 can produce a kind of controlling mechanism, compensates the variation that spreads all over IC 101 preparation technology everywhere.At next square 503, represent that an internal reference resistance can be used to be used as some embodiment, or in the situation that external reference resistance is not provided or want to provide a preset reference of design alternative.Detect external reference resistance if provide internal reference resistance, the method to comprise, and between internal resistance and non-essential resistance, do one and select (for example,, can select internal resistance) if do not detect non-essential resistance.
At next square 505, represent that a reference voltage can be applied to the reference resistance of selection, and the reference impedance generator with reference impedance input.In shown embodiment, this reference voltage is a bus voltage, and it can apply on the series coupled that is connected across this reference resistance and the input of this reference impedance.At next square 507, expression can periodically (for example, be adjusted this reference impedance input, so that the impedance of reference impedance generator equates with a reference resistance of being scheduled in the tolerance constantly).In shown embodiment, the face that connects jointly between reference resistance and reference impedance generator can sense a voltage, and this voltage can (for example, VTT) half compares with input bus voltage.At next square 509, several selected binary arraies of the mutual matched impedance element of expression reference impedance generator can be imported and activation based on reference impedance.In shown embodiment, this reference impedance is input as a digital value, and wherein each meeting makes the selected group activation in the array of mutual coupling N pass element.
At next square 511, expression is delivered to the output impedance input of each output impedance generator and is controlled based on this reference impedance input.At next square 513, if expression is with bias voltage adjusted value programming, and this bias voltage adjusted value can combine with this reference impedance input, to adjust this output impedance input.In shown embodiment, logic bias voltage adjuster 217 can be with ADD[5:0] value incorporates the SUM[5:0 that (addition, subtract each other or in conjunction with) selected into] value, and the OSUM[5:0 of each output driver 107 is delivered in generation] value.At next square 515, several selected binary arraies of the mutual matched impedance element of expression output impedance generator can be based on this output impedance input and activation.As discussed previously, each output driver 107 comprises the mutual coupling N pass element (as in the reference impedance generator 207,213 any) of identical configuration, so that this output impedance meeting is based on this reference impedance and any output bias adjustment.At last, at last square 517, expression can be used an output enable signal, and makes this output enable or forbidden energy.
The impedance controller of an output driver can continue the impedance of each output driver of adjustment one IC in the mode of easy understanding during operating according to an embodiment of the invention.Impedance is monitored and adjusted to meeting constantly in the mode of the basic running of easy understanding circuit, comes compensation temperature, voltage and preparation technology's variation.Because changing is to occur with signal INPA or the proportional mode of INPB, so the change of signal VTT can not influence the impedance of output driver.Use resistance R EXT can produce an advantage of using resistance R INT not have, meeting variations in temperature complete and IC 101 is irrelevant when using resistance R EXT.
Though the present invention has cooperated its some preferred versions, and quite explains, other form and variation are feasible and can consider.For example, can consider to make the method for the various variations that programmable resistance generator 207,213 equates with reference resistance, as present technology or similar techniques.In addition, though considering, the present invention use metal-oxide-semiconductor (MOS) (MOS) pattern element (to comprise complementary MOS element and like, for example be NMOS and PMOS transistor) a kind of execution mode, but also can be applied to the technology or the topology of difference or simulation pattern in a similar fashion, as two-carrier element or like.
At last, what those skilled in the art should recognize is, do not breaking away under defined spirit of the present invention of accompanying Claim and the scope, in order to carry out the purpose identical with the present invention, it can use the notion and the certain embodiments of announcement immediately, the basis of being used as design or revising other structure.
Claims (16)
1. the impedance controller of an output driver, it controls the pull-down impedance of at least one output based on a reference value, includes:
One programmable reference impedance generator is in order to produce a reference impedance of being controlled by reference impedance control input;
At least one output driver, each output driver comprise a programmable impedance output generator, and it is coupled to a corresponding output, and are controlled by output impedance control input; And
One impedance matching controller is imported in order to continue adjusting this reference impedance control, so that this reference values match in this reference impedance and the predetermined nargin, and, control input and produce this output impedance based on this reference impedance control input,
Wherein, this impedance matching controller includes:
One voltage-sensor in order to the reference voltage of sensing based on an input bus voltage, and the voltage differences between the voltage of this programmable reference impedance generator, and can make an error signal activation of its demonstration; And
The logic impedance controller, it adjusts this reference impedance control input based on this error signal.
2. the impedance controller of output driver as claimed in claim 1, wherein each the programmable impedance output generator in this programmable reference impedance generator and this at least one programmable impedance output generator comprises a binary array of mutual matched impedance element.
3. the impedance controller of output driver as claimed in claim 1, wherein this reference value comprises a reference resistance, and wherein this input bus voltage applies on the series coupled that is connected across this reference resistance and this programmable reference impedance generator; This logic impedance controller is in order to receiving a clock signal, and during the selection cycle of this clock signal, can make this reference impedance control input increase or reduce.
4. the impedance controller of output driver as claimed in claim 1 wherein also comprises:
Logic bias voltage adjuster in order to a bias amount is combined with this reference impedance control input, is imported and produce this output impedance control;
Logic output bias device, it can be programmed and produce this bias amount.
5. the impedance controller of output driver as claimed in claim 1, wherein this impedance matching controller includes:
One first controller, be coupled to an external reference resistance, in order to produce one first reference value, this first controller also comprises the logic detection device, in order to monitor this reference impedance control input, judging whether this first reference value couples, and, then can make this second controller activation if do not couple this first reference value; And
One second controller comprises an internal reference resistance, in order to produce one second reference value.
6. the integrated circuit of the impedance controller of an output driver includes:
A plurality of pins, comprise in order to receive a reference voltage one first with reference to pin, and at least one output connecting pin;
At least one output driver, each output driver comprise a programmable impedance output generator, and it is controlled by output impedance control input, and couples in order to drive a corresponding output connecting pin of this at least one output connecting pin; And
The logic impedance matching box comprises: a programmable reference impedance generator, and it is controlled by reference impedance control input; Logic comparator, it is in order to continue adjusting this reference impedance control input, so that in a predetermined nargin, is coupled to this and first equates with reference to the value in the reference resistance of pin and this programmable reference impedance generator; And the logic follower, it controls this output impedance control input based on this reference impedance control input,
Wherein this logic comparator includes:
One voltage-sensor is coupled to this first with reference to pin and this programmable reference impedance generator, in order to detecting the voltage of this reference resistance of cross-over connection and this programmable reference impedance generator, and can make an error signal activation of its demonstration; And
The logic impedance controller, it adjusts this reference impedance control input based on this error signal.
7. integrated circuit as claimed in claim 6, wherein this reference voltage applies in the series connection coupling that is connected across this reference resistance and this programmable reference impedance generator, and wherein this logic comparator attempts to make the voltage in the predetermined voltage nargin to equate.
8. integrated circuit as claimed in claim 6, wherein also comprise one second with reference to pin, it is coupled to this programmable reference impedance generator, and an end that is coupled to this reference resistance, this reference resistance comprises an external reference resistance, and its other end is coupled to this first with reference to pin.
9. integrated circuit as claimed in claim 8, wherein this logic impedance matching box includes:
One internal reference resistance has and is coupled to this first end with reference to pin, and one second end; And
This programmable reference impedance generator comprises by one first reference impedance control input controls and is coupled to this second one first programmable reference impedance generator with reference to pin, and the one second programmable reference impedance generator of being controlled and be coupled to this second end of this internal reference resistance by one second reference impedance control input;
This logic comparator comprises first logic comparator, in order to adjust this first reference impedance control input, equate with the voltage of attempting to make this external reference resistance in one first nargin and this first programmable reference impedance generator, and second logic comparator, in order to adjusting this second reference impedance control input, equate to attempt to make this internal reference resistance in one second nargin and the voltage of this second programmable reference impedance generator;
The logic detection device in order to monitoring this first reference impedance control input, in order to detecting the existence of this external reference resistance, and can produce an activation signal of its demonstration; And
This logic follower is selected in this first reference impedance control input and this second reference impedance control input based on this enable signal, to produce this output impedance control input.
10. integrated circuit as claimed in claim 9 wherein also includes:
Logic output bias device is in order to produce an adjusted value; And
This logic follower comprises logic bias voltage adjuster, in order to this reference impedance control input is combined with this adjusted value, imports and produce this output impedance control.
11. integrated circuit as claimed in claim 6, wherein this reference impedance control input includes a digital value, wherein this logic impedance controller is in order to receiving a clock signal, and can respond the selection cycle of this clock signal, and makes this reference impedance control input increase or reduce.
12. the method for the pull-down impedance of at least one output driver of control comprises:
One reference voltage is applied to a reference resistance, and the reference impedance generator with reference impedance input;
Periodically adjust this reference impedance input, so that the impedance of this reference impedance generator equates with this reference resistance of being scheduled in the nargin; And
Control an output impedance of at least one output impedance generator based on this reference impedance input and import, each output impedance generator is coupled to a corresponding output driver.
13. the method as claim 12 wherein also includes:
This reference impedance generator of sensing, and a voltage that connects face jointly of this reference resistance of connecting with this reference voltage; And
This is periodically adjusted and comprises and this is connect the voltage of face jointly and a half voltage of this reference voltage compares.
14. the method as claim 12 wherein also comprises:
One internal reference resistance is provided;
Detect an external reference resistance and produce an activation signal of its demonstration; And
Based on this enable signal, select and between this internal reference resistance and this external reference resistance, do one.
15. the method as claim 12 wherein also comprises:
One bias voltage adjusted value is programmed; And
This is controlled output impedance input and comprises this bias voltage adjusted value is combined with the input of this reference impedance.
16. the method as claim 12 wherein also comprises:
Based on the input of this reference impedance, and make several selected binary array activations of the mutual matched impedance element of this reference impedance generator; And
Based on this output impedance input, and make several selected binary array activations of the mutual matched impedance element of each output impedance generator.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/730,389 US6998875B2 (en) | 2002-12-10 | 2003-12-05 | Output driver impedance controller |
| US10/730,389 | 2003-12-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553570A CN1553570A (en) | 2004-12-08 |
| CN100468970C true CN100468970C (en) | 2009-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100617953A Expired - Lifetime CN100468970C (en) | 2003-12-05 | 2004-06-30 | Output driver impedance controller and its integrated circuits and control method |
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| Country | Link |
|---|---|
| CN (1) | CN100468970C (en) |
| TW (1) | TWI242703B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI451094B (en) * | 2012-08-30 | 2014-09-01 | Hycon Technology Corp | Compensating circuit having programmable capacitance array for measuring ac voltage |
| TWI559682B (en) * | 2015-01-14 | 2016-11-21 | 智原科技股份有限公司 | Driving circuit, driving apparatus, and method for adjusting output impedance to match transmission line impedance by current adjusting |
| US9548734B1 (en) * | 2015-12-26 | 2017-01-17 | Intel Corporation | Smart impedance matching for high-speed I/O |
| CN116107384A (en) * | 2021-11-11 | 2023-05-12 | 瑞昱半导体股份有限公司 | Integrated circuit with self-referenced impedance |
-
2004
- 2004-03-19 TW TW93107374A patent/TWI242703B/en not_active IP Right Cessation
- 2004-06-30 CN CNB2004100617953A patent/CN100468970C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| TW200519559A (en) | 2005-06-16 |
| TWI242703B (en) | 2005-11-01 |
| CN1553570A (en) | 2004-12-08 |
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