CN100468738C - Semiconductor equipemnt with capacitor and its mfg. method - Google Patents
Semiconductor equipemnt with capacitor and its mfg. method Download PDFInfo
- Publication number
- CN100468738C CN100468738C CNB031478204A CN03147820A CN100468738C CN 100468738 C CN100468738 C CN 100468738C CN B031478204 A CNB031478204 A CN B031478204A CN 03147820 A CN03147820 A CN 03147820A CN 100468738 C CN100468738 C CN 100468738C
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- China
- Prior art keywords
- memory node
- bond pad
- cup
- pad shapes
- vertical shaft
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- Expired - Lifetime
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
A semiconductor substrate cotains a semiconductor substrate and an inter-layer insulating film formed on the substrate. The inter-layer insulating film contains contact pads formed in the insulating film. Capacitor lower electrodes are connected electrically to the contact pads. The lower electrodes comprise the pad-shaped storage nodes electrically connected to the contact pads and the cup-shaped storage nodes arrayed on the storage nodes. According to such a method, a capacitance can be increased, reducing not-open contacts, and the leanings of the storage nodes can also be decreased.
Description
Technical field
The present invention relates to semiconductor equipment, particularly capacitor arrangement and manufacture method thereof.
Background technology
Many latest integrated all need to use capacitor.For example, in dynamic random access memory (DRAM) equipment, capacitor has been brought into play vital data storage function.Because DRAM and the integrated degree of other memory devices become more and more higher, need new manufacturing process to increase the memory capacity of these capacitors.Yet seek out the capacitance that needs and but become more and more difficult.Enough capacitances keep, refresh effect and the so distinctive device characteristics of constant operating characteristic such as data for obtaining, and are crucial.
For improving capacitance, semicon industry is thrown in focus to have on the electrode for capacitors of three-dimensional structure in development.This is because the capacitance size of capacitor directly becomes positive example with the surface area of electrode for capacitors.In view of the above, manufacturing process is by increasing the height of cell capaciator electrode or memory node, to reach the purpose that increases effective surface area.For example, Fig. 1 shows the height of memory node and the design rule formulated according to prior art between relation.As shown in Figure 1, in the prior art, when design rule reduced, the height of memory node can increase.
Yet the height that increases regrettably, memory node can cause many problems.For example, the height of memory node then is difficult to the conductive layer of composition as memory node greater than about 10,000 dusts if desired.And when the height of memory node increased, the possibility of run-off the straight memory node also can significantly increase.The inclination memory node can cause producing electric bridge between adjacent memory node.This situation is partly shown in Fig. 2 and Fig. 3.When Fig. 2 signal increased when the height of memory node, the CD of bottom storage node (critical dimension) will reduce.Fig. 3 is a photos, and it has been showed in the conventional capacitor arrangement in the prior art, the situation that each memory node tilts to adjacent memory node.
Except that problem shown in above-mentioned, when design rule reduced, the probability of the problem that comes in contact between the memory node that adjoins also can increase.Fig. 4 is a photos, and it has showed the contact of the memory node that adjoins, and shows a kind of " not opening (not open) " phenomenon, and this phenomenon occurs in the conventional array of capacitors of the semiconductor memory devices of making according to prior art.Because these and other problems, the demand of improving integrated-circuit capacitor and manufacture method thereof is still very important.
Summary of the invention
According to embodiments of the invention, a semiconductor equipment preferably includes Semiconductor substrate and the intermediate insulating layer on Semiconductor substrate.Intermediate insulating layer can comprise the storage node contacts pad therein.The bottom electrode of capacitor preferably is electrically connected with contact pad.Capacitor lower electrode may further include the memory node of bond pad shapes, and is electrically connected with the storage node contacts pad.The cup-shaped memory node preferably is placed on the memory node of bond pad shapes.Adopt the capacitor lower node structure of this novelty, make that increasing capacitance adjoins the possibility that becomes that contacts with reducing.Can significantly reduce the situation that memory node tilts equally.
The present invention has considered simultaneously under the situation that does not increase electrode height, increases the additive method of electrode for capacitors surface area.For example, other can be used for increasing bond pad shapes memory node surface area equally, and do not deviate from the method for principle of the present invention and spirit.Strengthening bond pad shapes memory node width is one of method that reaches this purpose.Changing the shape of bond pad shapes memory node, increasing its surface area, thereby is to increase the another kind of method that electrode height reaches increases the capacitance purpose.
Description of drawings
Other purposes of the present invention, characteristic and advantage will be by becoming more clear for DETAILED DESCRIPTION OF THE PREFERRED, wherein with reference to the accompanying drawings:
Fig. 1 show according to prior art at the height of memory node and the graph of a relation between the design rule.
Fig. 2 shows according to prior art at the bottom critical dimension (CD) of memory node and the graph of a relation between the memory node height.
Fig. 3 shows the sectional view according to a semiconductor equipment of existent technique, and situation about tilting has taken place the memory node of the capacitor arrangement of this equipment.
Fig. 4 shows the vertical view according to the capacitor arrangement of a semiconductor equipment of existent technique, and the contact between the memory node of (non-opening) has taken place to adjoin this equipment.
Fig. 5 to Figure 16 shows the schematic sectional view of semiconductor equipment, and it shows a kind of according to an embodiment of the invention method of making the capacitor arrangement of integrated circuit memory equipment.In Fig. 5 to Figure 16, the figure of odd number represents the sectional view of bit line direction, and the figure of even number represents the sectional view of word-line direction.And
Figure 17 shows the plane graph according to the capacitor lower electrode that comprises dish type memory node and cup-shaped memory node of the embodiments of the invention shown in Figure 15.In Fig. 5 to Figure 16, the figure of odd number represents the sectional view of bit line direction, and the figure of even number represents the sectional view of word-line direction.
Embodiment
According to Fig. 5 to Figure 16, a kind of embodiment of the present invention will be explained below, and to provide a kind of of principle of the present invention is understood more completely.Yet those skilled in the art are appreciated that the present invention can pass through implemented in many forms.In addition, for the sake of simplicity, omitted description to well-known structure and technology at this.
At first with reference to Figure 15, the semiconductor equipment of realizing according to embodiment of the present invention preferably includes the intermediate insulating layer 102 that is positioned on the Semiconductor substrate 100.The preferably embedded storage node contacts pad 104 of intermediate insulating layer 102.Capacitor lower electrode 106 can place on the contact pad 104, and is electrically connected with it.Capacitor lower electrode 106 comprises the memory node 40 of bond pad shapes, and this node is electrically connected with storage node contacts pad 104; And place cup-shaped memory node 70 on the bond pad shapes memory node 40.
Bond pad shapes memory node 40 can comprise any suitable shape to support cup-shaped memory node 70, for example, the box-like memory node of four edges or the cylindric node of solid (non-hollow) is arranged.Cup-shaped memory node 70 can comprise " single cylinder is stacked " (OCS) structure.The capacitance of cup-shaped memory node 70 is than the about twice of the capacity of simple stacked capacitor arrangement, because surface, the inside of cup-shaped memory node and outer surface can be used as effective capacitor regions.
Figure 17 shows the plane graph according to the capacitor lower electrode 106 of the preferred embodiments of the present invention shown in Figure 15, and capacitor lower electrode 106 comprises bond pad shapes memory node 40, and is covered in the cup-shaped memory node 70 on the storage node contacts pad 104.With reference to Figure 17, be foursquare shape substantially though cup-shaped memory node 70 is shown as, in plane graph, it still can be such as circular, ellipse, rhombus or other any suitable shapes.
Fig. 5 to Figure 16 is a sectional view, show according to a further aspect in the invention manufacturing such as the manufacture method of Figure 15 and integrated circuit memory equipment shown in Figure 17.With reference to figure 5 and Fig. 6, a kind of low structure (lower structure), for example gate stack 112 or bit line (not shown) preferably place on the Semiconductor substrate 100.On the structure that obtains is intermediate insulating layer 102, and it is subsequently by constituting such as the such dielectric material of oxide.
Next, be arranged in the storage node contacts pad 104 of intermediate insulating layer 102, can be electrically connected with the active area of Semiconductor substrate 100.The etch stop layer 10 and first sacrifice layer 20 preferably order are formed on storage node contacts pad 104 and the intermediate insulating layer 102.These layers can be by the common process manufacturing.
Relative first sacrifice layer 20, etch stop layer 10 preferably has higher etching selectivity.Etch stop layer 10 can be made by silicon nitride, to reach for example thickness between 500 to 1000 dusts.In etching stripping technology subsequently, etch stop layer 10 is preferably as the terminal point of etch processes, and this etch processes is in order to remove first sacrifice layer 20, and the second and the 3rd sacrifice layer formed thereon afterwards.
With reference now to Fig. 7 and Fig. 8,, the first memory node opening 30 preferably is formed among first sacrifice layer 20, is to make by the photoetching process and the etch process of routine, and with etch stop layer 10 as etched terminal point.The etch stop layer that remains in the first memory node opening 30 preferably is removed.
With reference to figure 9 and Figure 10, the memory node 40 of bond pad shapes (also can be such as other box-like shapes) can be formed among the first memory node opening 30 by LPCVD and CMP process.Electric conducting material such as doped polycrystalline silicon, platinum (Pt), ruthenium (Ru) or TiN (titanium nitride) can be filled in the said structure that is arranged in the first memory node opening 30, and complanation forms the memory node 40 of bond pad shapes.
With reference to Figure 11 and Figure 12, second sacrifice layer 60 is formed on first sacrifice layer 20 and the bond pad shapes memory node 40 then.Second sacrifice layer 60 is preferably formed by the oxide of thickness between 10000 to 30000 dusts.Those skilled in the art will find that other suitable dielectric materials equally can be as forming first and second sacrifice layers 20,60.
With reference to Figure 13 and Figure 14, the second memory node opening 80 preferably by conventional photoetching process and etch process, is formed among first and second sacrifice layers 20,60.The routine techniques of use such as LPCVD technology is filled in the electric conducting material such as doped polycrystalline silicon in the second memory node opening 80, can form cup-shaped memory node 70.
The 3rd sacrifice layer 90 can be formed on the cup-shaped memory node 70, by the routine techniques such as LPCVD technology, and is made of the material of oxide and so on.The 3rd sacrifice layer 90 is preferably by the dielectric material of thickness between 3000 to 5000 dusts, makes such as the silicate glass of doped dielectric (USG) layer not.
Final structure optimization ground is formed cup-shaped memory node 70 by complanation subsequently, separates between the cup-shaped node 70 that adjoins.Therefore, each cup-shaped memory node 70 (for example memory node of OCS type) all can be formed among the second memory node opening 80 that is covered on the bond pad shapes memory node 40.Can adopt the conventional planarization technology such as CMP technology or deep etch to isolate each storage organization (capacitor lower electrode) 106.
With reference to Figure 15 and Figure 16, according to embodiments of the invention, first, second, third sacrifice layer 20,60,90 can be removed to form novel capacitor lower electrode 106 simultaneously by the stripping technology of routine.Therefore, capacitor lower electrode of the present invention preferably is made of two continuous laps.First comprises the memory node 40 of bond pad shapes (for example box-like).Second portion comprises cup-shaped (for example OCS square) memory node 70, and it is stacked on the bond pad shapes memory node 40.The memory node 40 of bond pad shapes and the aspect ratio between the cup-shaped memory node 70 are about 0.9:1.Therefore, the height of cup-shaped memory node is a little less than the height of conventional OCS memory node.As a result, the probability of memory node run-off the straight situation will significantly reduce, and meanwhile the capacitance of capacitor gets a promotion.
Therefore, principle of the present invention is exactly to adopt a kind of new storage capacitor structures and manufacture method thereof, so that reliable more firm memory node to be provided.With respect to prior art, owing to the sacrifice layer that only need remove among cup-shaped memory node or OCS memory node still less, preferred embodiment of the present invention further provides a kind of simpler stripping technology.In addition, because can there be enough photoetching edges at the edge of cup-shaped memory node opening, also can significantly reduce the probability that non-open contact phenomena takes place.Further, with respect to prior art, the width of capacitor lower electrode bottom can increase, and prevents the generation of tilt phenomenon, meanwhile uses cup-shaped memory node or OCS memory node, has increased the capacitance of capacitor arrangement.
According to embodiments of the invention, principle of the present invention has been described, under the situation that does not deviate from these principles, can make amendment to arrangement of the present invention and detail section.Therefore, all are not deviated from the scope of following claim and the modifications and variations of spirit, we have right to it at statement.
Claims (35)
1. semiconductor capacitor bottom electrode comprises:
The bond pad shapes memory node is electrically connected with the storage node contacts pad;
The cup-shaped memory node is positioned on the bond pad shapes memory node.
2. semiconductor capacitor bottom electrode as claimed in claim 1 is characterized in that the cup-shaped memory node is single cylindrical layer stack capacitor.
3. semiconductor capacitor bottom electrode as claimed in claim 1, it is square, circular or oval to it is characterized in that the cup-shaped memory node can be in plane graph.
4. semiconductor capacitor bottom electrode as claimed in claim 1 is characterized in that the aspect ratio between bond pad shapes memory node and the cup-shaped memory node is 0.9:1.
5. semiconductor capacitor bottom electrode as claimed in claim 1 is characterized in that the bond pad shapes memory node comprises box-like memory node.
6. semiconductor capacitor bottom electrode as claimed in claim 1 is characterized in that the bond pad shapes memory node comprises filled circles column memory node.
7. semiconductor equipment comprises:
Semiconductor substrate;
Be positioned at the intermediate insulating layer on the Semiconductor substrate, and have the storage node contacts pad in this intermediate insulating layer;
Capacitor lower electrode is electrically connected with the storage node contacts pad, and capacitor lower electrode comprises:
The bond pad shapes memory node that is electrically connected with the storage node contacts pad; And
Be positioned at the cup-shaped memory node on the bond pad shapes memory node.
8. semiconductor equipment as claimed in claim 7 is characterized in that the bond pad shapes memory node is box-like memory node or filled circles column memory node.
9. semiconductor equipment as claimed in claim 7 is characterized in that the bond pad shapes memory node is made of polysilicon.
10. make process for semiconductor devices for one kind, comprising:
Form intermediate insulating layer on Semiconductor substrate, intermediate insulating layer comprises contact pad;
On contact pad, form the bond pad shapes memory node;
On the bond pad shapes memory node, form the cup-shaped memory node to constitute capacitor lower electrode.
11. method as claimed in claim 10, it is characterized in that, the memory node that forms bond pad shapes comprises: form the etch stop layer and first sacrifice layer on contact pad, in first sacrifice layer, form the first memory node opening, in the first memory node opening, form the bond pad shapes memory node.
12. method as claimed in claim 11, it is characterized in that, forming the bond pad shapes memory node in the first memory node opening comprises: make electric conducting material fill the final structure that is arranged in the first memory node opening, and the complanation electric conducting material is to form the bond pad shapes memory node.
13. method as claimed in claim 12, it is characterized in that, forming the cup-shaped memory node comprises: form second sacrifice layer on first sacrifice layer and bond pad shapes memory node, in second sacrifice layer, form the second memory node opening, in the second memory node opening, form the cup-shaped memory node.
14. method as claimed in claim 13 also comprises: on the cup-shaped memory node, form the 3rd sacrifice layer.
15. method as claimed in claim 13 also comprises: other capacitor lower electrodes of capacitor lower electrode and semiconductor equipment are separated.
16. make process for semiconductor devices, comprising for one kind:
Formation is positioned at the intermediate insulating layer on the Semiconductor substrate, and comprises contact pad in this intermediate insulating layer;
On intermediate insulating layer, form etch stop layer;
On etch stop layer, form first sacrifice layer;
Among first sacrifice layer, form the first memory node opening;
In opening, form the bond pad shapes memory node;
On bond pad shapes memory node and etch stop layer, form second sacrifice layer;
Form the second memory node opening at second sacrifice layer that is arranged on the bond pad shapes memory node;
In the second memory node opening, form the cup-shaped memory node;
Remove first and second sacrifice layers to form capacitor lower electrode.
17. method as claimed in claim 16 is characterized in that, forms in the process of the first memory node opening in first sacrifice layer, etch stop layer plays the effect of etch-stop.
18. method as claimed in claim 16 is characterized in that, the bond pad shapes memory node is box-like memory node.
19. method as claimed in claim 16 is characterized in that, the cup-shaped memory node can comprise square, circle, or elliptic cross-section.
20. method as claimed in claim 16 is characterized in that: remove first and second sacrifice layers and comprise to form capacitor lower electrode: and use complanation or deep etch technology so that capacitor lower electrode and other capacitor lower electrodes are separated.
21. a semiconductor capacitor bottom electrode comprises:
The memory node of bond pad shapes has first central vertical shaft and is electrically connected to the storage node contacts pad with second central vertical shaft, and wherein second central vertical shaft is separated with first central vertical shaft; And
The cup-shaped memory node has the 3rd central vertical shaft and is arranged on the memory node of bond pad shapes, and wherein the 3rd central vertical shaft is separated with first central vertical shaft.
22. capacitor lower electrode as claimed in claim 21, wherein the cup-shaped memory node is single cylindrical layer stack capacitor.
23. capacitor lower electrode as claimed in claim 21, wherein the cup-shaped memory node is square, circular or oval in the plane.
24. capacitor lower electrode as claimed in claim 21, wherein the height of the memory node of bond pad shapes is 0.9:1 with the ratio of the height of cup-shaped memory node.
25. capacitor lower electrode as claimed in claim 21, wherein the memory node of bond pad shapes comprises box-like memory node.
26. capacitor lower electrode as claimed in claim 21, wherein the memory node of bond pad shapes comprises solid cylinder type memory node.
27. a semiconductor equipment comprises:
Semiconductor substrate;
Be formed on the intermediate insulating layer on the Semiconductor substrate, wherein this intermediate insulating layer is included in the storage node contacts pad that wherein has second central vertical shaft; And
Be electrically connected to the capacitor lower electrode of storage node contacts pad, this capacitor lower electrode comprises:
The memory node of bond pad shapes has first central vertical shaft and is electrically connected to the storage node contacts pad, and wherein second central vertical shaft is separated with first central vertical shaft; And
The cup-shaped memory node has the 3rd central vertical shaft and is arranged on the memory node of bond pad shapes, and wherein the 3rd central vertical shaft is separated with first central vertical shaft.
28. semiconductor equipment as claimed in claim 27, wherein the memory node of bond pad shapes is box-like memory node or solid cylinder type memory node.
29. semiconductor equipment as claimed in claim 27, wherein the memory node of bond pad shapes is formed by polysilicon.
30. one kind forms process for semiconductor devices, this method comprises:
Form intermediate insulating layer on Semiconductor substrate, wherein this intermediate insulating layer is included in the contact pad that wherein has second central vertical shaft;
Form the memory node of bond pad shapes, it has first central vertical shaft on contact pad, and wherein second central vertical shaft is separated with first central vertical shaft; And
Be formed on the cup-shaped memory node that has the 3rd central vertical shaft on the memory node of bond pad shapes, form capacitor lower electrode with the memory node together with bond pad shapes, wherein the 3rd central vertical shaft is separated with first central vertical shaft.
31. method as claimed in claim 30, the memory node that wherein forms bond pad shapes is included in and forms the etch stop layer and first sacrifice layer on the contact pad, in first sacrifice layer, form the first memory node opening, and in the first memory node opening, form the memory node of bond pad shapes.
32. method as claimed in claim 31, the memory node that wherein forms bond pad shapes in the first memory node opening is included in depositing conductive material on the resulting structures in the first memory node opening, and this electric conducting material of leveling is to form the memory node of bond pad shapes.
33. method as claimed in claim 32, wherein form and form second sacrifice layer on the memory node that the cup-shaped memory node is included in first sacrifice layer and bond pad shapes, in second sacrifice layer, form the second memory node opening, and in the second memory node opening, form the cup-shaped memory node.
34. method as claimed in claim 33 also is included in and forms the 3rd sacrifice layer on the cup-shaped memory node.
35. method as claimed in claim 33 also comprises other capacitor lower electrode of this capacitor lower electrode and semiconductor equipment isolated.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20989/2003 | 2003-04-03 | ||
| KR10-2003-0020989A KR100522544B1 (en) | 2003-04-03 | 2003-04-03 | Semiconductor device having a capacitor and method of fabricating same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1536669A CN1536669A (en) | 2004-10-13 |
| CN100468738C true CN100468738C (en) | 2009-03-11 |
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ID=29707778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031478204A Expired - Lifetime CN100468738C (en) | 2003-04-03 | 2003-06-25 | Semiconductor equipemnt with capacitor and its mfg. method |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP2004311918A (en) |
| KR (1) | KR100522544B1 (en) |
| CN (1) | CN100468738C (en) |
| DE (1) | DE10348200A1 (en) |
| GB (1) | GB2400236B (en) |
| TW (1) | TWI291231B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010034198A (en) | 2008-07-28 | 2010-02-12 | Elpida Memory Inc | Semiconductor device and method of manufacturing the same |
| JP5641681B2 (en) | 2008-08-08 | 2014-12-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Manufacturing method of semiconductor device |
| JP2011061067A (en) | 2009-09-11 | 2011-03-24 | Elpida Memory Inc | Method for manufacturing semiconductor device and semiconductor device |
| KR101877878B1 (en) | 2012-06-11 | 2018-07-13 | 에스케이하이닉스 주식회사 | Semiconductor device with multi―layered storage node and method for fabricating the same |
| US9252205B2 (en) | 2014-02-05 | 2016-02-02 | Coversant Intellectual Property Management Inc. | DRAM memory device with manufacturable capacitor |
| CN107845633B (en) * | 2017-10-30 | 2023-05-12 | 长鑫存储技术有限公司 | Memory and manufacturing method thereof |
| CN107887388B (en) * | 2017-11-27 | 2023-06-20 | 长鑫存储技术有限公司 | Transistor structure, memory cell, memory array and preparation method thereof |
| CN114188282B (en) * | 2020-09-14 | 2022-10-28 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4070919B2 (en) * | 1999-01-22 | 2008-04-02 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR100331568B1 (en) * | 2000-05-26 | 2002-04-06 | 윤종용 | Semiconductor memory device and method for fabricating the same |
| KR100375221B1 (en) * | 2000-07-10 | 2003-03-08 | 삼성전자주식회사 | Method of Forming Storage Node |
| KR100416601B1 (en) * | 2001-06-30 | 2004-02-05 | 삼성전자주식회사 | Semiconductor device having cylinder-type capacitor and fabricating method thereof |
| GB2386471B (en) * | 2001-12-11 | 2004-04-07 | Samsung Electronics Co Ltd | A method for fabricating a one-cylinder stack capacitor |
-
2003
- 2003-04-03 KR KR10-2003-0020989A patent/KR100522544B1/en active IP Right Grant
- 2003-06-19 TW TW092116678A patent/TWI291231B/en not_active IP Right Cessation
- 2003-06-25 CN CNB031478204A patent/CN100468738C/en not_active Expired - Lifetime
- 2003-06-30 JP JP2003188404A patent/JP2004311918A/en active Pending
- 2003-10-16 DE DE10348200A patent/DE10348200A1/en not_active Ceased
- 2003-10-21 GB GB0324534A patent/GB2400236B/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004311918A (en) | 2004-11-04 |
| KR100522544B1 (en) | 2005-10-19 |
| GB2400236A (en) | 2004-10-06 |
| GB2400236B (en) | 2005-09-14 |
| CN1536669A (en) | 2004-10-13 |
| KR20040086649A (en) | 2004-10-12 |
| GB0324534D0 (en) | 2003-11-26 |
| TW200421609A (en) | 2004-10-16 |
| TWI291231B (en) | 2007-12-11 |
| DE10348200A1 (en) | 2004-11-04 |
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