CN100466236C - Structure of semiconductor element - Google Patents
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- CN100466236C CN100466236C CNB2003101242847A CN200310124284A CN100466236C CN 100466236 C CN100466236 C CN 100466236C CN B2003101242847 A CNB2003101242847 A CN B2003101242847A CN 200310124284 A CN200310124284 A CN 200310124284A CN 100466236 C CN100466236 C CN 100466236C
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Abstract
A semiconductor component structure, which utilizes its special through hole pattern to separate metal intermetallic dielectric layer (ILD) into plurality of independent blocks for restricting crack resulting from lead bonding so as to reduce crack rate. The use of single layer through hole pattern can effectively reduce welding pad crack occurrence, and the use of two layers through hole pattern can completely avoid the welding pad crack occurrence.
Description
Technical field
The structure of the relevant a kind of semiconductor element of the present invention, and particularly relevant a kind of structure that causes element fracture can effectively reduce or avoid chip the time because of the package lead bonding.
Background technology
Modern electronic product moves towards under the compact trend gradually, connects on the plate that (Chip On Board COB) has become a kind of general encapsulation technology.The key technology of COB is that line links (being commonly called as the lead-in wire bonding, Wire Bonding) and sizing shaped (Molding), is meant exposed integrated circuit (IC) chip (ICChip) is encapsulated, and the technology of formation electronic component.Wherein integrated circuit welds technology such as (Tape Automatic Bonding are called for short TAB) automatically by lead-in wire bonding (WireBonding), flip-chip (Flip Chip) or carrier band, and its I/O is extended out through the circuit of packaging body.
When going between bonding, the strength of its lead-in wire bonding can cause damage to traditional semiconductor element.Please refer to Figure 1A, it illustrates a kind of generalized section of traditional part semiconductor element.For clearly demonstrating tradition and technical characterictic of the present invention, all diagrams of the present invention are only drawn related elements.Among Figure 1A, below metal level, semiconductor element 100 has base material 102, field oxide 104 and interlayer dielectric layer 106.By the mode of diffuse dopants or ion injection, form n type or P type semiconductor districts (being called N trap or P trap) on part base material 102 surfaces, or comprise both two traps designs.In addition, a complete integrated circuit normally is made up of thousands of MOS transistor.For the transistor that prevents to face mutually is short-circuited, must between adjacent transistors, (not be shown in Figure 1A) and add the dielectric layer of an isolation usefulness, be field oxide (Field Oxide is called for short FOX) 104.Interlayer dielectric layer (Inter-Layer Dielectric Layer) 106 then is to be used for isolating metal line and MOS element, its material for example is the lower boron-phosphorosilicate glass (Borophosphosilicate glass is hereinafter to be referred as BPSG) of glass transformation temperature (Glass Transition Temperature).(ChemicalVapor Deposition, CVD) method is deposited on BPSG base material 102 tops and covers field oxide 104 can to utilize chemical vapour deposition (CVD).Then, can carry out follow-up layer metal deposition.
The deposition of metal level can be a single or multiple lift, decides on process requirements.Figure 1A does explanation with the three-layer metal layer, is respectively the first metal layer (First Metallic Layer) 108, the second metal levels 114 and the 3rd metal level 120.And the metal intermetallic dielectric layer (Inter-MetalDielectric Layer, IMD Layer) of isolating usefulness is arranged between the metal level in twos, be connected the through hole (Via Hole) of usefulness with metal.Also be filled with in the through hole metal such as tungsten (Tungsten, W).
Therefore, among Figure 1A, between the first metal layer 108 and second metal level 114 one first metal intermetallic dielectric layer 110 is arranged, and a plurality of first through holes 112.Between second metal level 114 and the 3rd metal level 120 one second metal intermetallic dielectric layer 116 is arranged, and a plurality of second through holes 118.Wherein, all be filled with tungsten in first through hole 112 and second through hole 118, to link each layer metal level.And first metal intermetallic dielectric layer 110 and second metal intermetallic dielectric layer 116 of isolation usefulness, optional usefulness is for example with plasma activated chemical vapour deposition (Plasma-Enhanced CVD, PECVD) or high density plasma CVD (High-Density-Plasma CVD, HDP CVD) method deposits silica (Silicon Oxide, the SiO that forms
2).
Figure 1B illustrates the top view of the through hole of Figure 1A.Fig. 1 C illustrates the schematic perspective view of going up two metal layers, metal intermetallic dielectric layer and through hole among Figure 1A.Shown in Figure 1B, 1C, second through hole 118 is distributed in second metal intermetallic dielectric layer 116 as needle-bar.When carrying out the binding of COB line, strength (shown in the arrow F of Fig. 1 C) when reaching second metal intermetallic dielectric layer 116 of the 3rd metal level 120 and below when the lead-in wire bonding, because the material (tungsten) of filling in the through hole 118 is different with the material (as silica) of dielectric layer 116, therefore, both interfaces are easy to produce dislocation, and the formation crack, this is called weld pad slight crack (PadCrack), shown in the crack among Fig. 1 C 171,172,173.
In addition, owing to be distributed in the interlayer dielectric layer as through hole such as the needle-bar, so the dielectric material of metal intermetallic dielectric layer (as silica) can be considered continuous state.When the interface of tungsten and silica produces dislocation because of the impact of lead-in wire bonding, the weld pad slight crack that is caused will extend till the interface that runs into another place's tungsten and silica, as among Fig. 1 C than shown in the crack 171 and 173 of length.
If installing has the integrated circuit (IC) chip (IC Chip) of above-mentioned flaw (weld pad slight crack) in the application product, the problem that may cause some to use, for example IC electric leakage makes battery be positioned over that the short time does not just have in the product.Therefore, how effectively to reduce even to avoid fully the problem of weld pad slight crack, make integrated circuit (IC) chip have good performance, real is research staff's one important research target.
Summary of the invention
In view of this, purpose of the present invention is exactly the structure that is to provide a kind of semiconductor element, utilizes special via hole image, and metal intermetallic dielectric layer is divided into a plurality of autonomous blocks, reducing even to avoid fully the generation of weld pad slight crack effectively, and then promote the product yield.
According to first purpose of the present invention, a kind of structure of semiconductor element is proposed, break (the wire bonding crack) that causes because of the lead-in wire bonding in the time of can effectively reducing Chip Packaging.The structure of semiconductor element comprises: a base material; One interlayer dielectric layer (ILD) is formed on the base material; The multiple layer metal layer is formed at the interlayer dielectric layer top successively; And dielectric layer (IMD) between multiple layer metal, be formed at respectively between two metal levels, wherein each metal intermetallic dielectric layer has a plurality of through holes (Via Hole).Wherein, have those through holes of dielectric layer between layer of metal at least, its metal intermetallic dielectric layer can be separated into a plurality of independently dielectric material pieces.And those through holes preferably can link the metal level of the most close weld pad (Bonding Pad).
According to second purpose of the present invention, a kind of structure of semiconductor element is proposed, in the time of can avoiding Chip Packaging fully because of breaking of causing of lead-in wire bonding.The structure of semiconductor element comprises: a base material; One interlayer dielectric layer is formed on the base material; The multiple layer metal layer is formed at the interlayer dielectric layer top successively; And dielectric layer between multiple layer metal, be formed at respectively between two metal levels, wherein each metal intermetallic dielectric layer has a plurality of through holes that metal connects usefulness, is filled with metal in the described through hole.Wherein, have the through hole of dielectric layer between double layer of metal at least, its metal intermetallic dielectric layer can be separated into a plurality of independently dielectric material pieces.The described position mutual dislocation of the through hole of the position of the through hole of one deck and another layer in the dielectric layer between double layer of metal at least.And preferably, wherein between layer of metal the through hole of dielectric layer can link the metal level of close weld pad.
According to the 3rd purpose of the present invention, a kind of structure of semiconductor element is proposed, because of breaking that the lead-in wire bonding causes, wherein, the structure of this semiconductor element comprises: a base material in the time of can eliminating Chip Packaging; One interlayer dielectric layer is formed on this base material; One the first metal layer is formed on this interlayer dielectric layer; One second metal level is positioned at this first metal layer top, and between this first metal layer and this second metal level one first metal intermetallic dielectric layer is arranged, and this first metal intermetallic dielectric layer has metal to connect a plurality of first through holes of usefulness; And one the 3rd metal level, be positioned at this second metal level top, and one second metal intermetallic dielectric layer is arranged between this second metal level and the 3rd metal level, and this second metal intermetallic dielectric layer there are a plurality of second through holes of metal connection usefulness; Wherein, those first through holes separate this first metal intermetallic dielectric layer and are a plurality of independently first dielectric material pieces, and those second through holes separate this second metal intermetallic dielectric layer and are a plurality of independently second dielectric material pieces, and the position mutual dislocation of the position of those second through holes and those first through holes, wherein, be filled with metal in described first through hole and second through hole.
Preferably, the upper surface of those first through holes forms one first special graph, and the upper surface of those second through holes forms one second special graph.
Preferably, this first special graph is identical with this second special graph.
Preferably, this first special graph and this second special graph are a chessboard pattern, a Back Word line figure, a ripples line figure or a cobweb figure.
According to the 4th purpose of the present invention, a kind of structure of semiconductor element is proposed, because of breaking that the lead-in wire bonding causes, wherein, the structure of this semiconductor element comprises in the time of can avoiding Chip Packaging:
One base material;
One interlayer dielectric layer is formed on this base material;
The multiple layer metal layer is formed at this interlayer dielectric layer top successively; And
Dielectric layer between multiple layer metal is formed at respectively between two metal levels, and wherein each metal intermetallic dielectric layer has a plurality of through holes that metal connects usefulness, is filled with metal in the described through hole;
Have that dielectric layer has a plurality of independently dielectric material pieces between double layer of metal at least, and wherein those through holes of dielectric layer can link this metal level of the most close weld pad between layer of metal, and lay respectively at the described dielectric material piece independently of those in the dielectric layer between double layer of metal at least, its position is for staggering slightly mutually up and down.
Description of drawings
Figure 1A illustrates a kind of generalized section of traditional part semiconductor element;
Figure 1B illustrates the top view of the through hole of Figure 1A;
Fig. 1 C illustrates the schematic perspective view of going up two metal layers, metal intermetallic dielectric layer and through hole among Figure 1A;
Fig. 2 illustrates the schematic perspective view according to the part semiconductor element of first embodiment of the invention;
Fig. 3 illustrates the schematic perspective view according to the part semiconductor element of second embodiment of the invention; And
Fig. 4 A～4L illustrates the top view of the pairing through hole of sample number of experiment 2 and 3.
Description of reference numerals
100,200,300: semiconductor element
102,202: base material
104,204: field oxide (FOX)
106:206: interlayer dielectric layer (ILD)
108,208: the first metal layer
110,210: the first metal intermetallic dielectric layer (First IMD)
112,212,312: the first through holes
114,214: the second metal levels
116,216: the second metal intermetallic dielectric layer
118,218,318: the second through holes
120,220: the three metal levels
171,172,173: weld pad slight crack (Pad Crack)
Embodiment
The present invention is the through-hole structure that changes semiconductor element, utilizes the through hole (Via Hole) of special pattern that metal intermetallic dielectric layer (IMD) is separated and is a plurality of independently dielectric material pieces, the extension everywhere of weld pad slight crack when avoiding going between bonding.Below promptly be described in detail with two preferred embodiments.First embodiment system utilizes the particular via of the present invention of individual layer and the structure of metal intermetallic dielectric layer, and reaches the purpose of effective minimizing weld pad slight crack.Second embodiment utilizes double-deck particular via of the present invention and the structure of metal intermetallic dielectric layer, and reaches the purpose of avoiding the weld pad slight crack fully.In addition, for clearly demonstrating technical characterictic of the present invention, only illustrate related elements among the figure.
First embodiment
Please refer to Fig. 2, it illustrates the schematic perspective view according to the part semiconductor element of first embodiment of the invention.Among Fig. 2, below metal level, semiconductor element 200 has base material 202, field oxide 204 and interlayer dielectric layer 206.The mode of utilizing diffuse dopants or ion to inject, the surface of part base material 202 may form n type or P type semiconductor district (being called N trap or P trap), or comprises both two trap designs.204 of field oxides (Field Oxide, be called for short FOX) are one to be used for isolating and to face the dielectric layer of transistor (not being shown in Fig. 2) mutually.And interlayer dielectric layer (Inter-Layer Dielectric Layer, ILDLayer) 206 is to be used for isolating metal line and MOS element, its material for example is the lower boron-phosphorosilicate glass (Borophosphosilicate glass is hereinafter to be referred as BPSG) of glass transformation temperature (Glass Transition Temperature).(Chemical Vapor Deposition, CVD) method is deposited on BPSG base material 202 tops and covers field oxide 204 can to utilize chemical vapour deposition (CVD).Then, can carry out follow-up layer metal deposition.
The deposition of metal level can be a single or multiple lift, decides on process requirements.Do explanation with the three-layer metal layer in this embodiment, be respectively the first metal layer (First Metallic Layer) 208, the second metal levels 214 and the 3rd metal level 220.And isolate the metal intermetallic dielectric layer (Inter-Metal Dielectric Layer, IMD Layer) of usefulness in twos between the metal level in addition, be connected the through hole (Via Hole) of usefulness with metal.Also be filled with in the through hole metal such as tungsten (Tungsten, W).
Among Fig. 2, between the first metal layer 208 and second metal level 214 one first metal intermetallic dielectric layer 210 is arranged, and a plurality of first through holes 212.Between second metal level 214 and the 3rd metal level 220 one second metal intermetallic dielectric layer 216 is arranged, and a plurality of second through holes 218.Wherein, all be filled with tungsten in first through hole 212 and second through hole 218, to link each layer metal level.And first metal intermetallic dielectric layer 210 and second metal intermetallic dielectric layer 216 of isolation usefulness, optional usefulness is for example with plasma activated chemical vapour deposition (Plasma-Enhanced CVD, PECVD) or high density plasma CVD (High-Density-Plasma CVD, HDP CVD) method deposits silica (Silicon Oxide, the SiO that forms
2).
In first embodiment, the through hole that designs with tool special graph in the dielectric layer between layer of metal explains.Wherein, the position of this layer metal dielectric layer is again with the closer to lead-in wire bonding place, and its effect that prevents weld pad slight crack (Pad Crack) is good more, at this, is to explain with second through hole 218 in second metal intermetallic dielectric layer 216.
As shown in Figure 2, the upper surface of second through hole 218 forms as a tessellated special graph, is a plurality of independently dielectric material pieces and second metal intermetallic dielectric layer 216 separated.Confirm through experimental result, when the strength of lead-in wire bonding reaches second metal intermetallic dielectric layer 216, even at the interface of second through hole 218 of unlike material (in be filled with tungsten) with dielectric layer 216 (silica), produce dislocation because of material is different, also can be limited in independently dielectric material piece of a certain fritter, can not extend the weld pad slight crack that is caused in the time of therefore can reducing the lead-in wire bonding effectively everywhere.
Certainly, via hole image of the present invention is not restricted to chessboard pattern as shown in Figure 2, for example Back Word line, ripples line, cobweb figures also can, as long as metal intermetallic dielectric layer can be separated figure, technical characterictic all according to the invention into a plurality of independently dielectric material pieces.
Second embodiment
The semiconductor component structure of second embodiment and first embodiment is roughly the same, is the structure of using two-layer particular via of the present invention and metal intermetallic dielectric layer except second embodiment.And confirm that through experimental result second embodiment can reach the purpose of avoiding the weld pad slight crack fully.
Please refer to Fig. 3, it illustrates the schematic perspective view according to the part semiconductor element of second embodiment of the invention.Wherein, identical with Fig. 2 part is then used same Reference numeral.The metal level below, semiconductor element 300 has base material 202, field oxide 204 and interlayer dielectric layer 206 equally.Interlayer dielectric layer 206 for example is the boron-phosphorosilicate glass (BPSG) with chemical vapor deposition (CVD) method deposition.The deposition of metal level can be a single or multiple lift, decides on process requirements.Also do explanation in this embodiment, be respectively the first metal layer 208, the second metal levels 214 and the 3rd metal level 220 with the three-layer metal layer.
First metal intermetallic dielectric layer (First IMDlayer) 210 is arranged between the first metal layer 208 and second metal level 214, and a plurality of first through holes 312.One second metal intermetallic dielectric layer (Second IMD layer) 216 is arranged between second metal level 214 and the 3rd metal level 220, and a plurality of second through holes 318.Wherein, all be filled with tungsten in first through hole 312 and second through hole 318, to link each layer metal level.And first metal intermetallic dielectric layer 210 and second metal intermetallic dielectric layer 216 of isolation usefulness, the optional silica (SiO that forms in order to plasma activated chemical vapour deposition (PECVD) or high density plasma CVD (HDP CVD) method deposition
2).
In a second embodiment, the via hole image with the Back Word line explains.And up and down between double layer of metal dielectric layer all be separated into a plurality of independently dielectric material pieces, the stress area when therefore having increased the lead-in wire bonding, and then reduced the pressure that dielectric material bore (stress).And experimental result more confirms: have the through hole of two-layer special pattern, can avoid the generation of weld pad slight crack fully.
Certainly, the present invention is not exceeded with the Back Word line figure of Fig. 3, and for example gridiron pattern, ripples line, the cobweb figures of Fig. 2 also can for other.As long as metal intermetallic dielectric layer can be separated figure, technical characterictic all according to the invention into a plurality of independently dielectric material pieces.
In addition, when practical application, more than three layers of the number of metal level possibility that is to say more than two layers of metal intermetallic dielectric layer possibility.Yet,, can avoid the weld pad slight crack fully as long as between near the double layer of metal at lead-in wire bonding place, form the through hole of tool special graph in the dielectric layer.
In addition, first through hole 312 can be identical with the formed figure of the upper surface of second through hole 318, also can be different.And the position of two figures can be alignment or not line up (as staggering slightly) up and down.As long as both can both separate the metal intermetallic dielectric layer of this layer of place to a plurality of independently dielectric material pieces, all can avoid the weld pad slight crack fully.
Lead-in wire bonding experiment (Wire-Bonding Experiment)
Experiment one:The through hole (control group) that two-layer traditional needle-like is arranged
To the bonding experiment that goes between of the conventional semiconductors element with two-layer through hole of arranging as needle-like.Component structure is shown in Figure 1A～1C.Whether this experiment is the conditional parameter that utilizes when changing the lead-in wire bonding, observe the weld pad slight crack and reduce.Experimental result as shown in Table 1.
Table one
*: the standard parameter value of the bonding that goes between at present
Learn from experimental result: lead-in wire bonding strength increases can produce more slight cracks, and lead-in wire bonding strength reduces can make slight crack reduce, but has the side effect that binding is not gone up.Therefore, simple change lead-in wire bonding parameter can't improve the situation of weld pad slight crack.
Experiment two:The through hole of one deck tool special pattern of the present invention
To the bonding experiment that goes between of the semiconductor element of through hole with one deck tool special pattern of the present invention.Component structure please refer to Fig. 2.Whether this experiment is to utilize the individual layer via hole image that metal intermetallic dielectric layer is divided into a plurality of autonomous blocks, observe the weld pad slight crack and reduce.Experimental result as shown in Table 2.Wherein, pattern 1 (Pat.1) in the sample number～pattern 12 (Pat.12) is corresponding with Fig. 4 A～4L, represents the top view of the superiors' through hole.Among Fig. 4 A～4L, dark part representative is filled with the through hole of tungsten, and the white portion typical example is the metal intermetallic dielectric layer of oxide in this way.And the via hole image of Fig. 4 B～4F is the chessboard trellis, except the width of independently dielectric block and through hole different.
Table two
Sample number Pat.2:A=0.6 μ m, B=2 μ m
Sample number Pat.3:A=1 μ m, B=2 μ m
Sample number Pat.4:A=2 μ m, B=2 μ m
Sample number Pat.5:A=0.6 μ m, B=1 μ m
Sample number Pat.6:A=1 μ m, B=1 μ m
*: the standard parameter value of the bonding that goes between at present.
Experimental result is with (crackled weld pad number/total weld pad number) expression.
Learn from experimental result: when using individual layer to have via hole image of the present invention, can effectively reduce the slight crack in its metal intermetallic dielectric layer really.
Experiment three:The through hole of two-layer tool special pattern of the present invention
To the bonding experiment that goes between of the semiconductor element of through hole with two-layer tool special pattern of the present invention.Component structure please refer to Fig. 3.This experiment is the through hole that utilizes the identical special graph of double-deck tool, observes the situation of weld pad slight crack, and experimental result as shown in Table 3.Same, pattern 1 (Pat.1) in the sample number～pattern 12 (Pat.12) is corresponding with Fig. 4 A～4L, represents the top view of through hole.Among Fig. 4 A～4L, dark part representative is filled with the through hole of tungsten, and the white portion typical example is the metal intermetallic dielectric layer of oxide in this way.And the via hole image of Fig. 4 B～4F is the chessboard trellis, except the width of independently dielectric block and through hole different.
Table three
Sample number Pat.2:A=0.6 μ m, B=2 μ m
Sample number Pat.3:A=1 μ m, B=2 μ m
Sample number Pat.4:A=2 μ m, B=2 μ m
Sample number Pat.5:A=0.6 μ m, B=1 μ m
Sample number Pat.6:A=1 μ m, B=1 μ m
*: the standard parameter value of the bonding that goes between at present.
Experimental result is with (crackled weld pad number/total weld pad number) expression.
Learn from experimental result: pattern 2,3,5,6,9,11 via hole images that metal intermetallic dielectric layer can be divided into a plurality of autonomous blocks all according to the invention behind its process lead-in wire bonding, do not have any slight crack and produce.Therefore, when using bilayer to have via hole image of the present invention, can avoid the slight crack in its metal intermetallic dielectric layer fully.
From the above, the present invention utilizes special via hole image, and metal intermetallic dielectric layer is divided into a plurality of autonomous blocks, so that because of the lead-in wire slight crack that bonding caused is restricted, and reduce the probability that slight crack produces.And use simple layer via hole image of the present invention, particularly, can reduce the generation of weld pad slight crack effectively when the position of this through hole the closer to upper strata lead-in wire bonding.If utilize two-layer via hole image of the present invention, then can avoid the generation of weld pad slight crack fully.Therefore, use the yield that the present invention can promote semiconductor element greatly.
In sum; though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; when can doing various changes and retouching, thus protection scope of the present invention appended claim is determined to be as the criterion when looking.
Claims (30)
1. the structure of a semiconductor element, because of breaking that the lead-in wire bonding causes, wherein, the structure of this semiconductor element comprises in the time of can eliminating Chip Packaging:
One base material;
One interlayer dielectric layer is formed on this base material;
One the first metal layer is formed on this interlayer dielectric layer;
One second metal level is positioned at this first metal layer top, and between this first metal layer and this second metal level one first metal intermetallic dielectric layer is arranged, and this first metal intermetallic dielectric layer has metal to connect a plurality of first through holes of usefulness; And
One the 3rd metal level is positioned at this second metal level top, and one second metal intermetallic dielectric layer is arranged between this second metal level and the 3rd metal level, and this second metal intermetallic dielectric layer has metal to connect a plurality of second through holes of usefulness;
Wherein, those first through holes separate this first metal intermetallic dielectric layer and are a plurality of independently first dielectric material pieces, and those second through holes separate this second metal intermetallic dielectric layer and are a plurality of independently second dielectric material pieces, and the position mutual dislocation of the position of those second through holes and those first through holes
Wherein, be filled with metal in described first through hole and second through hole.
2. structure as claimed in claim 1, wherein the upper surface of those first through holes forms one first special graph, and the upper surface of those second through holes forms one second special graph.
3. structure as claimed in claim 2, wherein this first special graph is identical with this second special graph.
4. structure as claimed in claim 3, wherein this first special graph and this second special graph are a chessboard pattern.
5. structure as claimed in claim 3, wherein this first special graph and this second special graph are a Back Word line figure.
6. structure as claimed in claim 3, wherein this first special graph and this second special graph are a ripples line figure.
7. structure as claimed in claim 3, wherein this first special graph and this second special graph are a cobweb figure.
8. structure as claimed in claim 1, wherein this base material is a silicon substrate, this interlayer dielectric layer is a boron-phosphorosilicate glass.
9. structure as claimed in claim 1 wherein has a field oxide between this base material and this interlayer dielectric layer.
10. structure as claimed in claim 1, wherein the material of this first metal intermetallic dielectric layer and this second metal intermetallic dielectric layer is silica.
11. structure as claimed in claim 1, wherein the metal of filling in those first through holes and those second through holes is a tungsten.
12. the structure of a semiconductor element, because of breaking that the lead-in wire bonding causes, wherein, the structure of this semiconductor element comprises in the time of can avoiding Chip Packaging:
One base material;
One interlayer dielectric layer is formed on this base material;
The multiple layer metal layer is formed at this interlayer dielectric layer top successively; And
Dielectric layer between multiple layer metal is formed at respectively between two metal levels, and wherein each metal intermetallic dielectric layer has a plurality of through holes that metal connects usefulness, is filled with metal in the described through hole;
Those through holes that have dielectric layer between double layer of metal at least can separate into its metal intermetallic dielectric layer a plurality of independently dielectric material pieces, and the described position mutual dislocation of the through hole of the position of the through hole of one deck and another layer in the dielectric layer between double layer of metal at least.
13. structure as claimed in claim 12, the wherein a plurality of n layer through hole and the n-1 layer through hole of a n layer and a n-1 layer metal intermetallic dielectric layer, its metal intermetallic dielectric layer can be separated into a plurality of independently dielectric material pieces, and the upper surface of those n layer through holes and n-1 layer through hole forms one first via hole image and one second via hole image respectively, wherein n is a positive integer, n 〉=2.
14. structure as claimed in claim 13, wherein the position mutual dislocation of the position of those n layer through holes and those n-1 layer through holes.
15. structure as claimed in claim 13, wherein this first via hole image is identical with this second via hole image.
16. structure as claimed in claim 15, wherein this first via hole image and this second via hole image are a chessboard pattern.
17. structure as claimed in claim 15, wherein this first via hole image and this second via hole image are a Back Word line figure.
18. structure as claimed in claim 15, wherein this first via hole image and this second via hole image are a ripples line figure.
19. structure as claimed in claim 15, wherein this first via hole image and this second via hole image are a cobweb figure.
20. structure as claimed in claim 12, wherein this interlayer dielectric layer is a boron-phosphorosilicate glass, and between this base material and this interlayer dielectric layer field oxide is arranged.
21. structure as claimed in claim 12, wherein the material of those metal intermetallic dielectric layer is a silica, and the metal of filling in those through holes is a tungsten.
22. the structure of a semiconductor element, because of breaking that the lead-in wire bonding causes, wherein, the structure of this semiconductor element comprises in the time of can avoiding Chip Packaging:
One base material;
One interlayer dielectric layer is formed on this base material;
The multiple layer metal layer is formed at this interlayer dielectric layer top successively; And
Dielectric layer between multiple layer metal is formed at respectively between two metal levels, and wherein each metal intermetallic dielectric layer has a plurality of through holes that metal connects usefulness, is filled with metal in the described through hole;
Have that dielectric layer has a plurality of independently dielectric material pieces between double layer of metal at least, and wherein those through holes of dielectric layer can link this metal level of the most close weld pad between layer of metal, and lay respectively at the described dielectric material piece independently of those in the dielectric layer between double layer of metal at least, its position is for staggering slightly mutually up and down.
23. structure as claimed in claim 22 wherein is positioned at a plurality of independently dielectric material pieces of dielectric layer between double layer of metal at least, its upper surface forms one first dielectric regime block graphics and one second dielectric regime block graphics respectively.
24. structure as claimed in claim 23, wherein this first dielectric regime block graphics is identical with this second dielectric regime block graphics.
25. structure as claimed in claim 24, wherein this first dielectric regime block graphics and this second dielectric regime block graphics comprise a plurality of independently rectangles.
26. structure as claimed in claim 24, wherein this first dielectric regime block graphics and this second dielectric regime block graphics comprise a plurality of independently concentric rectangles.
27. structure as claimed in claim 24, wherein this first dielectric regime block graphics and this second dielectric regime block graphics comprise a plurality of independently concentric rings.
28. structure as claimed in claim 24, wherein this first dielectric regime block graphics and this second dielectric regime block graphics comprise a plurality of independently cellular surfaces.
29. structure as claimed in claim 22, wherein this interlayer dielectric layer is a boron-phosphorosilicate glass, and between this base material and this interlayer dielectric layer field oxide is arranged.
30. structure as claimed in claim 22, wherein the material of those metal intermetallic dielectric layer is a silica, and the metal of filling in those through holes is a tungsten.
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| CN103579033B (en) * | 2012-07-26 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of weld pad for wafer acceptability test |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
| JP2001085465A (en) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | Semiconductor device |
| US20010045669A1 (en) * | 2000-04-12 | 2001-11-29 | Zhongning Liang | Semiconductor device |
| US6365970B1 (en) * | 1999-12-10 | 2002-04-02 | Silicon Integrated Systems Corporation | Bond pad structure and its method of fabricating |
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2003
- 2003-12-29 CN CNB2003101242847A patent/CN100466236C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
| JP2001085465A (en) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | Semiconductor device |
| US6365970B1 (en) * | 1999-12-10 | 2002-04-02 | Silicon Integrated Systems Corporation | Bond pad structure and its method of fabricating |
| US20010045669A1 (en) * | 2000-04-12 | 2001-11-29 | Zhongning Liang | Semiconductor device |
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| CN1635633A (en) | 2005-07-06 |
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