CN100465927C - Internet exchange system able to smart realize CPU data transmission and method for realizing the same - Google Patents
Internet exchange system able to smart realize CPU data transmission and method for realizing the same Download PDFInfo
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- CN100465927C CN100465927C CNB2005101193869A CN200510119386A CN100465927C CN 100465927 C CN100465927 C CN 100465927C CN B2005101193869 A CNB2005101193869 A CN B2005101193869A CN 200510119386 A CN200510119386 A CN 200510119386A CN 100465927 C CN100465927 C CN 100465927C
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Abstract
A network change-over system used for realizing CPU data transmission is prepared as arranging a transmission-process unit in special chip, connecting system CPU with special chip through change-over chip and using connected CPU and chip to transmit data, reading out data packet from CPU transmission queue by transmission-process unit and transmitting said data packet to system CPU after data packet is added with MAC address for making system CPU and special chip be able to transmit data to each other directly without PCI bus. Its data transmitting method is also disclosed.
Description
Technical field
Content of the present invention relates to internet exchange system, particularly realize system CPU in the internet exchange system and the special chip (ASIC in the internet exchange system flexibly, Application SpecialIntegrated Circuit, the specific use integrated circuit, or be called the specific use special chip, be referred to as " special chip " in the present invention) between the internet exchange system and the method for data transmission.
Background technology
Usually, in an internet exchange system, for example in Ethernet switch system, have system CPU and several special chips.In general, the packet between special chip and the system CPU (Packet) transmission is by cpu bus, and for example pci bus is finished.But for a CPU, the transmittability of the pci bus that it can be supported is limited, and in fact such transmission mode has limited the data transmission capabilities between system CPU and special chip.
And, also there is band-limited problem in pci bus itself, and a lot of components and parts are all using pci bus to carry out communication with system CPU in the system, force special chip to be had to and other components and parts competition use pci buss, this has also limited the data transmission capabilities between system CPU and special chip.
Therefore, although special chip and system CPU all have than data-handling capacity and transmittability faster, but at present, the employed method of transmitting data by pci bus between system CPU and special chip of most systems has limited data transmission capabilities between the two, and this method is also very dumb.Therefore, be necessary to provide a kind of method and corresponding apparatus to realize faster, data transmission more flexibly between system CPU in the internet exchange system and the special chip.
Summary of the invention
The object of the present invention is to provide a kind of not by cpu bus, can realize the internet exchange system of data transmission between system CPU and the special chip flexibly, and the method for carrying out data transmission in these internet exchange systems, and the present invention supports to carry out between a plurality of CPU and a plurality of special chip method of data transmission.
Internet exchange system of the present invention comprises one or more system CPUs, an exchange chip, and one or more special chips, these special chips comprise a plurality of cpu data transmit queues and data processing unit, wherein, these special chips also comprise a transmission processing unit, and described exchange chip connects above-mentioned system CPU and above-mentioned special chip respectively.
Said system CPU is identical with system CPU of the prior art, and the whole network switch is played the master control effect, also possesses corresponding data processing function.
Above-mentioned exchange chip is used to finish the data transmission between above-mentioned one or more system CPU and the above-mentioned one or more special chip, guarantees can be sent to correct system CPU and also can be transferred into correct special chip by the packet that system CPU mails to special chip by the related data packets that special chip mails to system CPU.
Above-mentioned transmission processing unit is used for the packet of CPU transmit queue is read, and these packets is increased the MAC Address of system CPU; But also the MAC Address that will come from the system CPU that comprises in the packet of system CPU removes, and the packet after will handling sends next data processing unit of described special chip to.
Above-mentioned each CPU transmit queue has all comprised the MAC Address of a system CPU in initialization procedure, make this CPU transmit queue and specific system CPU set up corresponding relation by this MAC Address.At above-mentioned transmission processing unit from these CPU transmit queues after the read data packet, the MAC Address of the system CPU that these CPU transmit queues comprise, be increased in the destination address field of the packet that is read by above-mentioned transmission processing unit, these MAC Address determine which system CPU this packet is transferred into.
In internet exchange system, realize the method for cpu data transmission flexibly, comprise the method for special chip to system CPU transmission data, and system CPU is to the method for special chip transmission data, and wherein, special chip comprises the steps: to the method for system CPU transmission data
Described transmission processing unit in the above-mentioned internet exchange system reads next data to be transmitted bag from a CPU transmit queue;
Described transmission processing unit in the above-mentioned internet exchange system is increased to the MAC Address of the system CPU that above-mentioned CPU transmit queue is comprised in the destination address field of above-mentioned data to be transmitted bag, and the data packet transmission after will handling is given the described exchange chip in the above-mentioned internet exchange system;
Above-mentioned exchange chip is transferred to corresponding system CPU according to the MAC Address of the system CPU that comprises in the above-mentioned destination address with above-mentioned data to be transmitted bag.
In said process, described transmission processing unit is that the mode according to poll reads next data to be transmitted successively from described a plurality of CPU transmit queues.
In said process, described transmission processing unit is to read next data to be transmitted according to the priority decision of described a plurality of CPU transmit queues itself from which CPU transmit queue.Preferably, described transmission processing unit (33) is according to reading next data to be transmitted bag in the highest CPU transmit queue (32) of the priority of priority from described special chip (3).
Wherein, system CPU comprises the steps: to the method for special chip transmission data
System CPU forms the packet of giving special chip to be transmitted;
System CPU is transferred to above-mentioned exchange chip with above-mentioned data to be transmitted bag;
Above-mentioned exchange chip sends to the special chip corresponding with this destination address field in the above-mentioned internet exchange system according to the destination address field from the above-mentioned packet that system CPU receives with this packet;
The described transmission processing unit of above-mentioned special chip is removed the MAC Address of the system CPU that comprised in the source address field in the above-mentioned packet, and the packet after will handling sends next processing unit of above-mentioned special chip to.
In said process, the formed packet of giving special chip to be transmitted of system CPU obtains after being based on the packet that receives from special chip being handled, the source address field of the packet before system CPU will be handled this moment is as the destination address field of the packet after handling, and the destination address field of the packet before handling is as the source address field of the packet after handling.
In said process, the formed packet to special chip to be transmitted of system CPU is that system CPU produces voluntarily, rather than produce based on the data after the packet that comes from special chip is handled.
From system CPU to the process of special chip transmission data and in the opposite process, described exchange chip possesses automatic function of exchange above-mentioned, the packet that its assurance is transmitted according to the address transfer in its destination address field to correct equipment.
Provided by the present inventionly can realize the internet exchange system equipment of cpu data transmission flexibly and realize flexibly that in internet exchange system the method for cpu data transmission makes system CPU and special chip can directly carry out data transmission, do not need to re-use pci bus, thereby improved the efficient of data transmission, speed and transmission quality between the two greatly.This system and corresponding method can also be supported the data transmission between a plurality of CPU and a plurality of special chip, this also be traditional use pci bus solution can't be obtained.
Description of drawings
Fig. 1 is the system schematic that can realize the internet exchange system of cpu data transmission flexibly provided by the present invention.
Fig. 2 is the principle of work synoptic diagram that a system CPU and special chip carry out data transmission.
Fig. 3 is the principle of work synoptic diagram that a plurality of special chips transmit data in the internet exchange system provided by the present invention to a plurality of system CPUs.
Fig. 4 is the principle of work synoptic diagram that a plurality of system CPUs transmit data in the internet exchange system provided by the present invention to a plurality of special chips.
Label declaration
1, system CPU
2, exchange chip
3, special chip
31 data processing units, 32 CPU transmit queues, 33 transmission processing units
The data field of 4X, packet
The data of 41 source address fields, 42 destination address field 43 to CPU
41 ' source address field, 42 ' destination address field 43 ' from the data of CPU
Embodiment
Referring to Fig. 1, be the system schematic of embodiments of the invention one.In this embodiment, a plurality of system CPUs 1 are connected with exchange chip 2, and this exchange chip 2 is connected with a plurality of special chips 3 again.Special chip 3 comprises data processing unit 31, a plurality of CPU transmit queue 32 and a transmission processing unit 33.Wherein, described transmission processing unit 33 is used for the data to be transmitted of each CPU transmit queue 32 of special chip 3 inside is read, and the MAC Address of corresponding C PU transmit queue 32 incidental system CPUs 1 is increased in the destination address field of these packets, form new packet.Be transferred to corresponding system CPU 1 through the new packet after above-mentioned transmission processing unit 33 processing by exchange chip 2.Simultaneously, above-mentioned transmission processing unit 33 also will come from the MAC Address of the system CPU that is comprised in the packet of some system CPUs 1 to be removed, and the packet after handling through these is continued to handle by next processing unit of described special chip 2.
In the present embodiment, above-mentioned data processing unit 31 is general designations of one or more processing units, and it carries out conventional processing according to prior art to packet, and those skilled in the art all understands its purposes and implementation in conjunction with prior art.
In the present embodiment, each CPU transmit queue 32 has comprised the MAC Address of some system CPUs when initialization, and the packet in this CPU transmit queue promptly is sent in the system CPU of MAC Address correspondence of the subsidiary system CPU of this CPU transmit queue.
With present embodiment similarly among other embodiment, the MAC Address of the CPU that above-mentioned each CPU transmit queue 32 is comprised also can be dynamically to be changed by the control module in the special chip 32 in system's operational process, like this, then require the information bit of the MAC Address of tag system CPU dynamically to be changed.Such embodiment has more dirigibility.
Referring to Fig. 2, be embodiments of the invention two.Different with embodiment one is in the present embodiment, to have only a system CPU 1 and a special chip 3.Owing to have only a system CPU and a special chip, therefore, this special chip can directly be given system CPU by physical connection with data packet transmission, and vice versa.Therefore, with regard to the exchange chip 2 that no longer needs to comprise among the embodiment one, can realize system provided by the present invention and only this system CPU directly need be connected with this special chip.Correspondingly, owing to have only a system CPU 1, so the packet of each the CPU transmit queue 32 in the special chip 3 all can only send this system CPU to, therefore, in the present embodiment, the MAC Address of the system CPU that comprised of each CPU transmit queue 32 is the address of this system CPU 1.
Referring to Fig. 2, half part thereon, i.e. the part that indicates by from right to left arrow, it has described the process that special-purpose chip 3 is given data packet transmission system CPU 1 in the present embodiment.After handling through the data processing unit 31 of special chip 3 inside, the packet that is transferred to system CPU 1 by special chip 3 is sent to sequence number and is queuing in 6 the CPU transmit queue 32.Transmission processing units 33 in the special chip 3 are that the next data to be transmitted bag in 6 the CPU transmit queue 32 is read with sequence number, and the MAC Address of these CPU transmit queue 32 incidental system CPUs is increased to the destination address (DA of this packet, Destination Address) in the territory 42, this packet is transmitted to system CPU 1 according to the MAC Address of the CPU in this destination address field 42 then.As mentioned above, owing to have only a system CPU 1, the MAC Address of all CPU transmit queue 32 incidental CPU of special chip inside all is MAC Address of this system CPU.Therefore, this packet must be transferred to system CPU 1.At this moment, this special chip 3 is promptly indicated in source address (SA, the Source Address) territory 41 that is transmitted packet, and destination address field is promptly indicated this system CPU 1.
Data packet transmission is given in the process of system CPU 1 at above-mentioned special chip 3, special chip 3 initiatively reads the packet in each CPU transmit queues 32 of special chip 3 inside, and initiatively sends system CPU 1 to.Different by the pci bus reading of data in this point and the prior art by system CPU 1, can improve the efficient that data are transmitted greatly between system CPU and special chip.
Referring to Fig. 2, in its latter half, i.e. the part that indicates by from left to right arrow, it has described among the embodiment two system CPU 1 to the process of special chip 3 transmits data packets.After system CPU 1 forms the data to be transmitted bag, give special chip 3 with this data packet transmission.The source address field 42 of this packet ' in comprise the MAC Address of system CPU 1, the destination address field 41 of this packet ' promptly point to special chip 3.The transmission processing unit 33 of proprietary chip 3 at first with the source address field 42 of the packet that receives ' in the MAC Address of the system CPU 1 that comprises remove, and then it is handled in a conventional manner by data processing unit 31.
In said process, 31 pairs of data processing units are transmitted processing unit 33, and to remove the processing that the packet after the MAC Address of the system CPU that comprises in the packets carries out be a kind of processing of usual manner, be the common mode that the common special chip in the common internet exchange system is handled packet, those skilled in the art is appreciated that and can realizes the processing procedure of these usual manners in conjunction with prior art.
In conjunction with foregoing description as seen, can be interpreted as a special case of the present invention to embodiment two, i.e. the present invention exists n system CPU and m special chip, and in embodiment two, exactly the situation of " n=m=1 ".
With reference to figure 3, Fig. 4, it has been described among the embodiment shown in Figure 1 jointly by the process of a plurality of special chips 3 to a plurality of system CPU 1 transmits data packets, and a plurality of system CPU 1 is to the process of a plurality of special chip 3 transmits data packets.
With reference to figure 3, it has been described by the process of a plurality of special chips 3 to a plurality of system CPU 1 transmits data packets.As shown in Figure 1, comprise a plurality of special chips 3 and a plurality of system CPU 1 in the present embodiment, correspondingly have an exchange chip 2, be used to connect a plurality of special chips 3 and a plurality of system CPU 1.Transmission processing unit 33 in described the 0th～n special chip 3 is worked independently of one another, read next data to be transmitted bag in its each CPU transmit queue 32 from place special chip 3, MAC Address with this CPU transmit queue 32 incidental CPU is increased in the destination address field of this packet then, forms new packet; Then, the new packet after processed is sent to exchange chip 2 by the transmission processing unit 33 of special chip 3; Exchange chip 2 sends this packet to corresponding system CPU according to the MAC Address of the system CPU that comprises in the destination address field that comprises in the packet that receives.
At this moment, the destination address field that is transmitted packet is indicated a certain system CPU, and for example system CPU 3, and source address field is promptly indicated the special chip in packet source, for example ASIC1.
With embodiment illustrated in fig. 2 different be, the MAC Address of the incidental system CPU of CPU transmit queue in the special chip 3 is no longer identical, but corresponding different respectively system CPUs.In the present embodiment, have 2 system CPUs, 4 special chips, 8 CPU transmit queues are arranged in each special chip, the corresponding system CPU 1 of MAC Address that 0～3 CPU transmit queue of each special chip is subsidiary, the corresponding system CPU 2 of MAC Address that 4～7 CPU transmit queues of each special chip are subsidiary.And with present embodiment similarly among other embodiment, 3 system CPUs are then arranged, 8 special chips, the 0th～3 special chip has 4 CPU transmit queues, the 4th～7 special chip has 6 CPU transmit queues, and in this embodiment, the sequence number of the 0th～2 special chip is that the corresponding sequence number of 0 CPU transmit queue is 0 system CPU, sequence number is that the corresponding sequence number of 1 CPU transmit queue is 1 system CPU, and sequence number is that 2,3 the equal corresponding sequence number of CPU transmit queue is 2 system CPU; Is 0 system CPU and sequence number is preceding two CPU transmit queues of 3 special chip corresponding to sequence number, and latter two CPU transmit queue is 2 system CPU corresponding to sequence number; First three CPU transmit queue of the 4th～7 special chip is 0 system CPU corresponding to sequence number, and ensuing two CPU transmit queues are 1 system CPU corresponding to sequence number, and last CPU transmit queue is 2 system CPU corresponding to sequence number.Certain above-mentioned CPU transmit queue is corresponding to the system CPU of certain sequence number, and promptly the MAC Address of the system CPU that this CPU transmit queue comprised is the address of this system CPU.
With reference to figure 4, it has described the detailed process that a plurality of system CPUs 1 are given data packet transmission a plurality of special chips 3.Equally, each system CPU 1 works alone, and forms the packet that will be transferred to certain special chip 3; System CPU 1 is given exchange chip 2 with data packet transmission, and exchange chip 2 is given the pairing special chip 3 of these information according to the information in the destination address field that comprises in the packet that receives with data packet transmission; After these special chips 3 receive this packet, the MAC Address of the system CPU that comprises in the source address field in this packet is removed by the transmission processing unit in the special chip 3 33; Packet is after treatment continued to handle according to the conventional processing mode by the data processing unit in the special chip 3 33.
Similar with the process of describing at embodiment two, above-mentioned " processing in a conventional manner ", be the common mode that the common special chip in the common internet exchange system is handled packet, those skilled in the art is appreciated that and can realizes the processing procedure of these usual manners in conjunction with prior art.
In the foregoing description one, embodiment two, the source of the data to be transmitted bag that system CPU forms has dual mode.First, be after packet that system CPU will come from special chip is handled, result is transferred to special chip as the data to be transmitted bag, at this moment, the source address field of the packet before the information of the destination address field of data to be transmitted bag is promptly handled by system CPU, be the address of certain special chip, and the source address field of data to be transmitted bag is promptly handled the destination address field of preceding packet by system CPU, promptly comprise the information of the MAC Address of system CPU.This mode makes the result of packet can correctly be returned to the sender of this packet, is about to it and sends to that special chip of this system CPU.The second way, promptly system CPU forms a new packet and sends to special chip, and at this moment, the packet of the special chip that this packet and this system CPU institute once received and handled is not direct to be concerned.
In Fig. 3, embodiment one shown in Figure 4, because exchange chip 2 itself has automatic function of exchange, so it can be sent to corresponding target ground with this packet according to the destination address field in the packet.When packet by a plurality of system CPUs during to the transmission of a plurality of special chips, exchange chip 2 makes packet correctly to be sent to corresponding special chip, vice versa.
In the present invention, for exchange chip,, it promptly can be used in the specific embodiment as long as possessing automatic function of exchange.Such product has a lot, for example can select Marvell GalNet-2GT-48304 G.Link Crossbar, also can select Marvell Prestera-FX9210 12-PortCrossbar Switch Fabric or Broadcom BCM5675 or the like.
In other embodiments of the invention, above-mentioned exchange chip 2 can also be a plurality of, and at this moment, a plurality of exchange chips constitute a switching matrix, finish the function of the exchange chip among the embodiment one jointly.In one embodiment, have 2 exchange chips, then the part special chip is connected to the 1st exchange chip, and the residue special chip then is connected on the 2nd exchange chip, and similarly, each system CPU also is connected respectively on two exchange chips.With the similar transmission course of Fig. 3, Fig. 4 in, then two exchange chips are worked in coordination and are finished the automatic exchange of packet.In such embodiments, those skilled in the art can reference example one, embodiment two realizes present embodiments.Simultaneously, in the present embodiment, two exchange chips adopt the exchange chip of model of the same race, i.e. Marvell GalNet-2GT-48304 G.Link Crossbar; And with present embodiment similarly among other embodiment, two exchange chips adopt different models, promptly adopt Marvell Prestera-FX9210 12-PortCrossbar Switch Fabric and Broadcom BCM5675 respectively.With present embodiment similarly among other embodiment, the number reality of required exchange chip is decided according to the quantity of special chip and system CPU and the exchange capacity of exchange chip.Generally speaking, the situation of an exchange chip described in the embodiment one promptly can satisfy system's needs.
In other embodiments of the invention, there is the situation of having only a system CPU, a plurality of special chips.In this embodiment, still need one or more exchange chips, but the MAC Address of the system CPU that each the CPU transmit queue in each special chip is comprised being then similar with embodiment two, promptly all is addresses of this unique system CPU.System about present embodiment forms and data transmission procedure, and those skilled in the art can be achieved with reference to embodiment one, embodiment two, repeats no more.
At the transmission processing unit 33 of the special chip described in the various embodiments described above 3 from above-mentioned CPU transmit queue before the read data packet, these packets are write in the CPU transmit queue 32 by the data processing unit 31 of above-mentioned special chip 3, this process is consistent with the processing procedure that special chip carried out in the existing network exchange system, those skilled in the art all understands it and realizes principle and concrete processing mode, does not repeat them here.
In the present invention, for special chip, it is to obtain by the innovation and creation that the present invention makes on used usually special chip basis, and these " used special chips usually " are as long as possess certain function, and in described internet exchange system, need to use this function, it just can be used in native system so, thereby can be by the described transmission of finishing packet at itself and system CPU neatly of native system.
Although the present invention is illustrated with aforesaid preferred embodiment, but the foregoing description is not to be used for limiting the present invention, any technician that this field is familiar with, enlightenment according to design philosophy of the present invention, concrete summary of the invention and embodiment, should various changes and adjustment, and by these changes with adjust resulting new content and should be contained by content of the present invention.
Claims (10)
1. internet exchange system that is used to realize the cpu data transmission comprises:
One or more system CPUs (1),
One or more special chips (3) comprise a plurality of cpu data transmit queues (32) and data processing unit (31), and
One exchange chip (2) is used to finish the data transmission between above-mentioned one or more system CPU (1) and the above-mentioned one or more special chip (3),
It is characterized in that:
Described exchange chip (2) connects described system CPU (1) and described special chip (3) respectively, and
Described special chip (3) also comprises a transmission processing unit (33), and this unit (33) are read data packet from described CPU transmit queue (32), packet is increased the MAC Address of system CPU (1); This unit (33) also will come from the MAC Address of the system CPU (1) that comprises in the packet of system CPU and remove.
2. internet exchange system as claimed in claim 1 is characterized in that, each CPU transmit queue (32) of described special chip all comprises the MAC Address of a system CPU (1).
3. internet exchange system as claimed in claim 1, it is characterized in that, to the process of system CPU (1) transmission, described transmission processing unit (33) is increased to the MAC Address of the system CPU (1) that CPU transmit queue (32) is comprised in the destination address field of this packet packet from special chip (3).
4. internet exchange system as claimed in claim 1, it is characterized in that, to the process of special chip (3) transmission, described transmission processing unit (33) is removed the MAC Address of the system CPU (1) that comprised in the source address field in the packet to packet from system CPU (1).
5. internet exchange system as claimed in claim 1 is characterized in that, described exchange chip (2) can be a plurality of.
6. the method for employed realization cpu data transmission in the internet exchange system that claim 1 provided, comprise the method for special chip (3) to system CPU (1) transmission data, and system CPU (1) is to the method for special chip (3) transmission data, it is characterized in that described special chip (3) comprises the steps: to the method for system CPU (1) transmission data
Read next data to be transmitted bag in the CPU transmit queue (32) of transmission processing unit (33) in the described special chip (3) from described special chip (3);
Described transmission processing unit (33) is increased to the MAC Address of the system CPU (1) that described CPU transmit queue (32) is comprised in the destination address field of described data to be transmitted bag, and the data packet transmission after will handling is given the exchange chip (2) in the described internet exchange system;
Described exchange chip (2) is given corresponding system CPU (1) according to the MAC Address of the system CPU that destination address field comprised (1) in the described packet with described data packet transmission;
Its feature is that also system CPU (1) comprises the steps: to the method for special chip (3) transmission data
System CPU (1) forms the packet of giving special chip (3) to be transmitted;
System CPU (3) is transferred to above-mentioned exchange chip (2) with above-mentioned data to be transmitted bag;
Described exchange chip (2) sends to the special chip corresponding with this destination address field (3) according to the destination address field from the described packet that system CPU (1) receives with described packet;
The transmission processing unit (33) of described special chip (3) is removed the MAC Address of the system CPU that source address field comprised (1) of described packet, and the packet after will handling sends next processing unit of described special chip (3) to.
7. the method for realization cpu data as claimed in claim 6 transmission is characterized in that, the formed packet of giving special chip (3) to be transmitted of described system CPU (1) obtains after being based on the packet that receives from special chip (3) being handled.
8. the method for realization cpu data transmission as claimed in claim 6 is characterized in that, the formed packet to special chip (3) to be transmitted of described system CPU (1) is that system CPU (1) produces voluntarily.
9. the method for realization cpu data transmission as claimed in claim 6 is characterized in that described transmission processing unit (33) is according to reading next data to be transmitted bag in a plurality of CPU transmit queues (32) of polling mode from described special chip (3).
10. the method for realization cpu data transmission as claimed in claim 6, it is characterized in that described transmission processing unit (33) is according to reading next data to be transmitted bag in the highest CPU transmit queue (32) of the priority of priority from described special chip (3).
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| CNB2005101193869A CN100465927C (en) | 2005-11-02 | 2005-11-02 | Internet exchange system able to smart realize CPU data transmission and method for realizing the same |
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| CN100465927C true CN100465927C (en) | 2009-03-04 |
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| CN101110779B (en) * | 2007-07-13 | 2011-03-16 | 中兴通讯股份有限公司 | Method for transmitting data to Ethernet port through fast input/output port |
| CN102710451A (en) * | 2012-06-21 | 2012-10-03 | 迈普通信技术股份有限公司 | BASE-bus-based board card device and control method thereof |
| CN106559838B (en) * | 2015-09-24 | 2019-12-06 | 大唐移动通信设备有限公司 | business processing optimization method and device |
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| US20040022107A1 (en) * | 2000-01-20 | 2004-02-05 | Palmchip Corporation | Unidirectional bus architecture for SoC applications |
| CN1348131A (en) * | 2000-08-29 | 2002-05-08 | 上海中晶电脑有限公司 | Electronic white board |
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