CN100464241C - Pixel structure of liquid crystal display and manufacturing method thereof - Google Patents

Pixel structure of liquid crystal display and manufacturing method thereof Download PDF

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CN100464241C
CN100464241C CNB200710127222XA CN200710127222A CN100464241C CN 100464241 C CN100464241 C CN 100464241C CN B200710127222X A CNB200710127222X A CN B200710127222XA CN 200710127222 A CN200710127222 A CN 200710127222A CN 100464241 C CN100464241 C CN 100464241C
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CN101067705A (en
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郑逸圣
赵志伟
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AUO Corp
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AU Optronics Corp
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Abstract

本发明公开了一种液晶显示器的像素结构及其制造方法，在此像素结构中，由金属层/介电层/重掺杂硅层构成储存电容器的下电极/电容介电层/上电极，以增加其电容量。同时，在薄膜晶体管的底部形成金属遮光层以减少光漏电流的发生。采用本发明，在储存电容器的部分，其下电极是由金属所构成，其上电极由重掺杂的硅层所构成。因此，与由非掺杂硅层、栅介电层与金属层所构成的现有技术的储存电容器相较下，可大幅增加储存电容器的电容量。此外，薄膜晶体管的下方也多一层金属遮光层，以阻断光漏电流的产生。

Figure 200710127222

The invention discloses a pixel structure of a liquid crystal display and a manufacturing method thereof. In the pixel structure, the lower electrode/capacitance dielectric layer/upper electrode of a storage capacitor is composed of a metal layer/dielectric layer/heavily doped silicon layer, to increase its capacity. At the same time, a metal light-shielding layer is formed on the bottom of the thin film transistor to reduce the occurrence of light leakage current. According to the invention, in the part of the storage capacitor, the lower electrode is made of metal, and the upper electrode is made of heavily doped silicon layer. Therefore, compared with the prior art storage capacitor composed of the non-doped silicon layer, the gate dielectric layer and the metal layer, the capacitance of the storage capacitor can be greatly increased. In addition, there is an additional layer of metal light-shielding layer under the thin film transistor to block the generation of light leakage current.

Figure 200710127222

Description

The dot structure of LCD and manufacture method thereof
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, and relate in particular to a kind of dot structure and manufacture method thereof of LCD.
Background technology
In the dot structure of available liquid crystal display, if its thin film transistor (TFT) is the structure of top grid (top gate), then the silicon island of the bottom electrode of its reservior capacitor and thin film transistor (TFT) is usually by being constituted with one deck silicon layer, and the grid of the top electrode of reservior capacitor and thin film transistor (TFT) is usually by being constituted with one deck metal level.Cause when coming that with the grid and the mask that powers on very above-mentioned silicon layer carried out ion doping, because the top electrode of reservior capacitor covers in bottom electrode, therefore can't carry out effective ion doping to bottom electrode, cause the storage capacitors amount that can't effectively increase reservior capacitor.And thin film transistor (TFT) also produces leakage current because of irradiation easily.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of dot structure and manufacture method thereof that is applicable to LCD.
For achieving the above object, the invention provides a kind of dot structure, be applicable to a LCD, this dot structure comprises at least: a thin film transistor (TFT), be positioned on the active region of a substrate, this thin film transistor (TFT) comprises: an active storehouse, and this active storehouse has a metal light shield layer, a dielectric layer and a silicon island from the bottom to top in regular turn, and the two ends of this silicon island have a heavily doped one source pole district and a drain region; One gate dielectric layer is positioned on this active storehouse; And at least one grid, be positioned on this gate dielectric layer of this active storehouse top; One reservior capacitor, be positioned on the capacitive region of this substrate, this reservior capacitor has one first electrode, a capacitance dielectric layer and one second electrode from the bottom to top in regular turn, wherein this first electrode and this metal light shield layer are made of a discontinuous the first metal layer, this capacitance dielectric layer and this dielectric layer are made of discontinuous one first dielectric layer, this second electrode and this silicon island are made of a discontinuous silicon layer, and this second electrode is heavy doping and is electrically connected with this drain region; And a pixel electrode, be electrically connected with this second electrode.
And, for achieving the above object, the invention provides a kind of manufacture method of display picture element structure, at first, on substrate, form the first metal layer, first dielectric layer and silicon layer in regular turn, this metal level of patterning, first dielectric layer and silicon layer then form initiatively storehouse and electric capacity storehouse respectively on the active region of substrate and capacitive region, and the electric capacity line that is connected with the electric capacity storehouse of formation.Then, at substrate, initiatively form the gate dielectric layer and second metal level in regular turn on storehouse, electric capacity storehouse and the electric capacity line, patterning second metal level again, with at least one grid of formation above the active storehouse, and the sweep trace that links to each other with grid.With grid and sweep trace is the doping mask, and the silicon layer of active storehouse, electric capacity storehouse and electric capacity line is carried out heavy doping technology to form a plurality of heavily doped regions.Wherein, initiatively the heavily doped region at the silicon layer two ends of storehouse is respectively source area and drain region, and the first metal layer of electric capacity storehouse and heavily doped region are respectively first electrode and second electrode that constitutes reservior capacitor.
Then, form second dielectric layer on gate dielectric layer, grid and sweep trace, patterning second dielectric layer exposes source area, drain region and second electrode respectively to form first opening, second opening and the 3rd opening again.Then, form the 3rd metal level and be covered on second dielectric layer, patterning the 3rd metal level forms data line, electrically connects first lead of data line and source area and second lead that electrically connects the drain region and second electrode again.Then, form flatness layer on second dielectric layer, data line, first lead and second lead, the patterning flatness layer forms the 4th opening to expose second lead then.Then, forming transparency conducting layer on the flatness layer with among the 4th opening, patterned transparent conductive layer forms the pixel electrode that is electrically connected with second lead again.
Adopt the present invention, in the part of reservior capacitor, its bottom electrode (also being the first electrode 105b) is made of metal, and its top electrode (also being the second electrode 130c) is made of heavily doped silicon layer.Therefore, and compare down, can significantly increase the electric capacity of reservior capacitor by the reservior capacitor of the prior art that non-doped silicon layer, gate dielectric layer and metal level constituted.In addition, the below of thin film transistor (TFT) is many layer of metal light shield layer also, with the blocking-up photo leakage current.
Description of drawings
State with other purpose, feature, advantage and embodiment and can become apparent on the present invention for allowing, being described in detail as follows of appended accompanying drawing:
Please refer to Figure 1A-Fig. 6 B, it illustrates the manufacturing process synoptic diagram according to the dot structure of a kind of LCD of the single grid embodiment of the present invention.
Please refer to Fig. 7 A-Fig. 7 B, it illustrates the synoptic diagram according to the dot structure of a kind of LCD of bigrid embodiment of the present invention.
Wherein, Reference numeral:
100: substrate 105a: the metal light shield layer
105b: the first electrode 105c: the first terminal
110b: capacitance dielectric layer 110a: first dielectric layer
110d: the first dielectric layer 110c: first dielectric layer
115b: silicon layer 115a: silicon island
115d: silicon layer 115c: silicon layer
118b: electric capacity storehouse 118a: active storehouse
118d: electric capacity line 118c: terminal storehouse
125a: grid 120: gate dielectric layer
125c: the second terminal 125b: sweep trace
130b: drain region 130a: source area
130d: heavily doped region 130c: second electrode
130f: heavily doped region 130e: heavily doped region
Dielectric layer 135 in 140: the second: light doped region
145b: the second opening 145a: first opening
145d: the 4th opening 145c: the 3rd opening
150b: data line 150a: first lead
150d: the 3rd terminal 150c: second lead
160a: the 5th opening 155: flatness layer
165a: pixel electrode 160b: the 6th opening
165b: protective seam
Embodiment
Single grid embodiment:
Please refer to Figure 1A-Fig. 6 B, it illustrates the manufacturing process synoptic diagram according to the dot structure of a kind of LCD of the single grid embodiment of the present invention.
Please earlier with reference to Figure 1A-Figure 1B, Figure 1A is a vertical view, and Figure 1B is AA ', BB ', the CC ' cross-sectional view of Figure 1A.On substrate 100, form earlier the first metal layer, first dielectric layer and silicon layer in regular turn, patterning the first metal layer, first dielectric layer and silicon layer then, forms active storehouse 118a, electric capacity storehouse 118b and terminal storehouse 118c respectively in active region (profile line AA '), capacitive region (profile line BB ') and terminal region (profile line CC ') respectively, and the electric capacity line 118d that is connected with terminal storehouse 118c with electric capacity storehouse 118b.The material of above-mentioned silicon layer for example can be polysilicon or amorphous silicon, and the material of first dielectric layer for example can be monox.
Above-mentioned active storehouse 118a is formed by metal light shield layer 105a, the first dielectric layer 110a and silicon island 115a storehouse, and wherein metal light shield layer 105a is made of the first metal layer, and silicon island 115a is made of silicon layer.Electric capacity storehouse 118b is formed by the first electrode 105b, capacitance dielectric layer 110b and silicon layer 115b storehouse, and wherein the first electrode 105b is made of the first metal layer, and capacitance dielectric layer 110b is made of first dielectric layer.Terminal storehouse 118c is formed by the first terminal 105c, the first dielectric layer 110c and silicon layer 115c storehouse, and the first terminal 105c is made of the first metal layer.And above-mentioned electric capacity line 118d (Figure 1A), it is formed by the first metal layer, first dielectric layer and silicon layer storehouse, can only see the silicon layer 115d of the superiors at 1A figure.
Please earlier with reference to Fig. 2 A-Fig. 2 B, Fig. 2 A is a vertical view, and Fig. 2 B is AA ', BB ', the CC ' cross-sectional view of Fig. 2 A.On substrate 100, active storehouse 118a, electric capacity storehouse 118b, terminal storehouse 118c and electric capacity line 118d, form the gate dielectric layer 120 and second metal level in regular turn earlier, patterning second metal level then is to form grid 125a and the sweep trace 125b that links to each other with grid 125a and the second terminal 125c on active storehouse 118a.Then, being the doping mask with grid 125a carries out heavy doping technology to silicon island 115a and silicon layer 115b, 115c, 115d, to form heavily doped region.The heavily doped region that wherein is arranged in silicon island 115a is respectively as source area 130a and drain region 130b, and heavily doped silicon layer 115b is as the second electrode 130c, and the heavily doped region 130e that is arranged in silicon layer 115d.In addition, also have the heavily doped region 130d of position in silicon layer 115c.The first above-mentioned electrode 105b and the second electrode 130c form reservior capacitor.Above-mentioned gate dielectric layer 120 for example can be monox, silicon nitride or silicon oxynitride.
In addition, also optionally further isotropic etching grid 125a (and sweep trace 125b) is that the doping mask carries out light doping process to silicon island 115a with grid 125a again, forms light doped region 135.
Please refer to Fig. 3, on gate dielectric layer 120, grid 125a and sweep trace 125b and the second terminal 125c, form second dielectric layer 140 earlier.Then, patterning second dielectric layer 140 forms the first opening 145a, the second opening 145b, the 3rd opening 145c and the 4th opening 145d to expose source area 130a, drain region 130b, the second electrode 130c and heavily doped region 130d respectively among second dielectric layer 140.The material of the second above-mentioned dielectric layer 140 for example can be monox.
Please earlier with reference to Fig. 4 A-Fig. 4 B, Fig. 4 A is a vertical view, and Fig. 4 B is AA ', BB ', the CC ' cross-sectional view of Fig. 4 A.Forming the 3rd metal level on second dielectric layer 140 and among the first opening 145a, the second opening 145b, the 3rd opening 145c and the 4th opening 145d earlier.Then, patterning the 3rd metal level is with the 3rd terminal 150d that forms data line 150b, data line 150b end, connect the first lead 150a (via the first opening 145a) of data line 150b and source area 130a and be connected drain region 130b and the second lead 150c of the second electrode 130c (via the second opening 145b and the 3rd opening 145c).Simultaneously, also second metal level in the 4th opening 145d and the heavily doped region 130d that exposes are removed it, expose the first dielectric layer 110c.
Please refer to Fig. 5, then forming flatness layer 155 on second dielectric layer 140, data line 150b, the first lead 150a, the second lead 150c, the 3rd terminal 150d and among the 4th opening 145d.Then, patterning flatness layer 155 forms the 5th opening 160a and the 6th opening 160b in flatness layer 155.Wherein, the 5th opening 160a exposes the second lead 150c, and the 6th opening 160b then exposes the first terminal 105c.
Please earlier with reference to Fig. 6 A-Fig. 6 B, Fig. 6 A is a vertical view, and Fig. 6 B is AA ', BB ', the CC ' cross-sectional view of Fig. 6 A.Then, on flatness layer 155 and the interior formation transparency conducting layer of the 5th opening 160a, the 6th opening 160b.Patterned transparent conductive layer again is to form the protective seam 165b of pixel electrode 165a and the first terminal 105c.The material of above-mentioned transparency conducting layer for example can be tin indium oxide, indium zinc oxide or aluminum zinc oxide.
Bigrid embodiment:
Please refer to Fig. 7 A-Fig. 7 B, it illustrates the synoptic diagram according to the dot structure of a kind of LCD of bigrid embodiment of the present invention.Fig. 7 A is a vertical view, and Fig. 7 B is AA ', BB ', the CC ' cross-sectional view of Fig. 7 A.
Basically,, transistorized structure (is shown in profile line AA '), other basic structure identical (as profile line BB ' and profile line CC ') except being changed into the bigrid by single grid.Therefore the part of same structure all adopts the components identical label, repeats no more.In addition, because bigrid embodiment is also substantially the same with the manufacturing process of single grid embodiment, therefore also repeat no more.Below only narrated with regard to the part of thin-film transistor structure.
In Fig. 7 A, being shaped as of the active storehouse 118a of thin-film transistor structure is crooked, partly to overlap with grid 125a and sweep trace 125b, allows the part formation double-grid structure (125a, 125b) that overlaps.Section AA ' part in Fig. 7 B, grid 125a with as part of scanning line 125b, the source area 130a of grid, drain region 130b and heavily doped region 130f formation double-gate film transistor.In addition, also can be in manufacture process, be chosen in grid 125a and the both sides silicon layer and make light doped region 135 respectively as the part of scanning line 125b of grid.
From the above, in the part of reservior capacitor, its bottom electrode (also being the first electrode 105b) is made of metal, and its top electrode (also being the second electrode 130c) is made of heavily doped silicon layer.Therefore, and compare down, can significantly increase the electric capacity of reservior capacitor by the reservior capacitor of the prior art that non-doped silicon layer, gate dielectric layer and metal level constituted.In addition, the below of thin film transistor (TFT) is many layer of metal light shield layer also, with the blocking-up photo leakage current.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims (29)

1.一种像素结构的制造方法，适用于一液晶显示器，其特征在于，该制造方法包括：1. A manufacturing method of a pixel structure, applicable to a liquid crystal display, is characterized in that, the manufacturing method comprises: 依序形成一第一金属层、一第一介电层与一硅层于一基板上；sequentially forming a first metal layer, a first dielectric layer and a silicon layer on a substrate; 图案化该第一金属层、该第一介电层与该硅层，分别在该基板的一主动区与一电容区上形成一主动堆栈与一电容堆栈，以及形成与该电容堆栈连接的一电容线；patterning the first metal layer, the first dielectric layer and the silicon layer, respectively forming an active stack and a capacitor stack on an active region and a capacitor region of the substrate, and forming a capacitor connected to the capacitor stack capacitor line; 依序形成一栅介电层与一第二金属层于该基板、该主动堆栈、该电容堆栈与该电容线之上；sequentially forming a gate dielectric layer and a second metal layer on the substrate, the active stack, the capacitor stack and the capacitor line; 图案化该第二金属层，以在该主动堆栈上方形成至少一栅极，以及与该栅极相连的一扫描线；patterning the second metal layer to form at least one gate above the active stack and a scan line connected to the gate; 以该栅极与该扫描线为掺杂掩膜，对该主动堆栈的该硅层、该电容堆栈的该硅层与该电容线的该硅层进行一重掺杂工艺以形成多个重掺杂区，其中该主动堆栈的该硅层两端的两个重掺杂区分别为一源极区与一漏极区，而该电容堆栈的该第一金属层与该电容堆栈的重掺杂区分别为构成一储存电容器的一第一电极与一第二电极；Using the gate and the scan line as a doping mask, perform a heavy doping process on the silicon layer of the active stack, the silicon layer of the capacitor stack, and the silicon layer of the capacitor line to form a plurality of heavily doped region, wherein the two heavily doped regions at both ends of the silicon layer of the active stack are a source region and a drain region respectively, and the first metal layer of the capacitor stack and the heavily doped region of the capacitor stack are respectively a first electrode and a second electrode constituting a storage capacitor; 形成一第二介电层于该栅介电层、该栅极与该扫描线之上；forming a second dielectric layer on the gate dielectric layer, the gate and the scan line; 图案化该第二介电层，以形成一第一开口、一第二开口与一第三开口分别暴露出该源极区、该漏极区与该第二电极；patterning the second dielectric layer to form a first opening, a second opening and a third opening respectively exposing the source region, the drain region and the second electrode; 形成一第三金属层覆盖于该第二介电层之上以及该第一开口、该第二开口与该第三开口中；forming a third metal layer covering the second dielectric layer and in the first opening, the second opening and the third opening; 图案化该第三金属层，形成一数据线、电性连接该数据线与该源极区的一第一导线以及电性连接该漏极区与该第二电极的一第二导线；patterning the third metal layer to form a data line, a first wire electrically connecting the data line and the source region, and a second wire electrically connecting the drain region and the second electrode; 形成一平坦层于该第二介电层、该数据线、该第一导线与该第二导线之上；forming a flat layer on the second dielectric layer, the data line, the first conductive line and the second conductive line; 图案化该平坦层，形成一第五开口以暴露出该第二导线；patterning the planar layer to form a fifth opening to expose the second wire; 形成一透明导电层于该平坦层之上与该第五开口之中；以及forming a transparent conductive layer on the planar layer and in the fifth opening; and 图案化该透明导电层，形成与该第二导线电性相接的一像素电极。The transparent conductive layer is patterned to form a pixel electrode electrically connected to the second wire. 2.根据权利要求1所述的方法，其特征在于，在进行该重掺杂工艺与形成该第二介电层的步骤之间还包括：2. The method according to claim 1, further comprising: between performing the heavy doping process and forming the second dielectric layer: 等向性蚀刻该栅极，以缩减该栅极的尺寸；以及isotropically etching the gate to reduce the size of the gate; and 以蚀刻后的该栅极为掺杂掩膜，对该主动堆栈的该硅层进行一淡掺杂工艺，以在该源极区与该漏极区的内侧分别形成一淡掺杂区。Using the etched gate as a doping mask, a light doping process is performed on the actively stacked silicon layer to form lightly doped regions inside the source region and the drain region respectively. 3.根据权利要求1所述的方法，其特征在于，还包括在该电容线的末端形成一第一端子，该第一端子的形成方法包括：3. The method according to claim 1, further comprising forming a first terminal at the end of the capacitor line, the forming method of the first terminal comprising: 在图案化该第一金属层、该第一介电层与该硅层的步骤中，形成连接该电容线末端的一端子堆栈；during the step of patterning the first metal layer, the first dielectric layer and the silicon layer, forming a terminal stack connecting the ends of the capacitor line; 在图案化该第二介电层的步骤中，形成一第四开口于该第二介电层中暴露出该端子堆栈的该硅层；In the step of patterning the second dielectric layer, forming a fourth opening in the second dielectric layer exposing the silicon layer of the terminal stack; 在图案化该第三金属层的步骤中，除去该端子堆栈上的该第三金属层与该硅层；During the step of patterning the third metal layer, removing the third metal layer and the silicon layer on the terminal stack; 在图案化该平坦层的步骤中，除去该端子堆栈上的该平坦层与该第一介电层以暴露出该第一金属层，该端子堆栈的该第一金属层构成该第一端子；以及In the step of patterning the planar layer, removing the planar layer and the first dielectric layer on the terminal stack to expose the first metal layer, the first metal layer of the terminal stack constitutes the first terminal; as well as 在图案化该透明导电层的步骤中，形成一保护层于暴露出的该第一端子之上。In the step of patterning the transparent conductive layer, a protection layer is formed on the exposed first terminal. 4.根据权利要求1所述的方法，其特征在于，图案化该第二金属层的步骤中还包括形成一第二端子，电性连接于该扫描线的末端。4. The method according to claim 1, wherein the step of patterning the second metal layer further comprises forming a second terminal electrically connected to an end of the scan line. 5.根据权利要求1所述的方法，其特征在于，该图案化该第三金属层的步骤中还包括形成一第三端子，电性连接于该数据线的末端。5. The method according to claim 1, wherein the step of patterning the third metal layer further comprises forming a third terminal electrically connected to the end of the data line. 6.根据权利要求1所述的方法，其特征在于，部分的该扫描线位于该主动堆栈上方的该栅介电层上。6. The method of claim 1, wherein a part of the scan line is located on the gate dielectric layer above the active stack. 7.根据权利要求1所述的方法，其特征在于，该硅层的材料包括多晶硅或非晶硅。7. The method according to claim 1, wherein the material of the silicon layer comprises polysilicon or amorphous silicon. 8.根据权利要求1所述的方法，其特征在于，该第一介电层与该第二介电层的材料包括氧化硅。8. The method according to claim 1, wherein the material of the first dielectric layer and the second dielectric layer comprises silicon oxide. 9.根据权利要求1所述的方法，其特征在于，该栅介电层的材料包括氧化硅、氮化硅或氮氧化硅。9. The method according to claim 1, wherein the material of the gate dielectric layer comprises silicon oxide, silicon nitride or silicon oxynitride. 10.根据权利要求1所述的方法，其特征在于，该透明导电层的材料包括氧化铟锡、氧化铟锌或氧化铝锌。10. The method according to claim 1, wherein the material of the transparent conductive layer comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide. 11.一种像素结构，适用于一液晶显示器，其特征在于，该像素结构至少包括：11. A pixel structure suitable for a liquid crystal display, characterized in that the pixel structure at least includes: 一薄膜晶体管，位于一基板的一主动区上，该薄膜晶体管包括：A thin film transistor located on an active area of a substrate, the thin film transistor comprising: 一主动堆栈，该主动堆栈由下至上依序具有一金属遮光层、一介电层与一硅岛，该硅岛的两端具有重掺杂的一源极区与一漏极区；An active stack, the active stack has a metal light-shielding layer, a dielectric layer and a silicon island in sequence from bottom to top, and the two ends of the silicon island have a heavily doped source region and a drain region; 一栅介电层，位于该主动堆栈之上；以及a gate dielectric layer over the active stack; and 至少一栅极，位于该主动堆栈上方的该栅介电层上；at least one gate on the gate dielectric layer above the active stack; 一储存电容器，位于该基板的一电容区上，该储存电容器由下至上依序具有一第一电极、一电容介电层与一第二电极，其中该第一电极与该金属遮光层由不连续的一第一金属层所构成，该电容介电层与该介电层由不连续的一第一介电层所构成，该第二电极与该硅岛由不连续的一硅层所构成，该第二电极为重掺杂且与该漏极区电性相接；以及A storage capacitor, located on a capacitance area of the substrate, the storage capacitor has a first electrode, a capacitor dielectric layer and a second electrode in sequence from bottom to top, wherein the first electrode and the metal light-shielding layer are separated from each other The capacitor dielectric layer and the dielectric layer are formed by a discontinuous first dielectric layer, and the second electrode and the silicon island are formed by a discontinuous silicon layer , the second electrode is heavily doped and electrically connected to the drain region; and 一像素电极，与该第二电极电性相接。A pixel electrode is electrically connected with the second electrode. 12.根据权利要求11所述的像素结构，其特征在于，还包括二个淡掺杂区，分别位于该源极区与该漏极区的内侧。12. The pixel structure according to claim 11, further comprising two lightly doped regions located inside the source region and the drain region respectively. 13.根据权利要求11所述的像素结构，其特征在于，还包括：13. The pixel structure according to claim 11, further comprising: 一扫描线，电性连接于该至少一栅极；a scan line electrically connected to the at least one gate; 一第二介电层，位于该栅介电层、该至少一栅极与该扫描线之上；a second dielectric layer located on the gate dielectric layer, the at least one gate and the scan line; 一数据线，位于该第二介电层上；a data line located on the second dielectric layer; 一第一导线，位于该第二介电层上，电性连接该数据线与该源极区；以及a first wire, located on the second dielectric layer, electrically connecting the data line and the source region; and 一第二导线，位于该第二介电层上，电性连接该漏极区、该第二电极和该像素电极。A second wire, located on the second dielectric layer, electrically connects the drain region, the second electrode and the pixel electrode. 14.根据权利要求13所述的像素结构，其特征在于，还包括：14. The pixel structure according to claim 13, further comprising: 一电容线，电性连接于该储存电容器，该电容线的结构由下至上与该储存电容器相同；以及a capacitance line, electrically connected to the storage capacitor, the structure of the capacitance line is the same as that of the storage capacitor from bottom to top; and 一第一端子位于该电容线的末端，该第一端子由该第一金属层所构成，该第一端子之上具有一保护层，该保护层与该像素电极由同一透明导电层所构成。A first terminal is located at the end of the capacitance line. The first terminal is formed by the first metal layer. There is a protection layer on the first terminal. The protection layer and the pixel electrode are formed by the same transparent conductive layer. 15.根据权利要求14所述的像素结构，其特征在于，还包括一第二端子位于该扫描线的末端，以及一第三端子位于该数据线的末端。15. The pixel structure according to claim 14, further comprising a second terminal located at the end of the scan line, and a third terminal located at the end of the data line. 16.根据权利要求15所述的像素结构，其特征在于，该扫描线、该至少一栅极与该第二端子由一第二金属层所构成，以及该数据线、该第一导线、该第二导线与该第三端子由一第三金属层所构成。16. The pixel structure according to claim 15, wherein the scan line, the at least one gate and the second terminal are formed by a second metal layer, and the data line, the first wire, the The second wire and the third terminal are formed by a third metal layer. 17.根据权利要求13所述的像素结构，其特征在于，部分的该扫描线位于该主动堆栈上方的该栅介电层上。17. The pixel structure according to claim 13, wherein a part of the scan line is located on the gate dielectric layer above the active stack. 18.根据权利要求11所述的像素结构，其特征在于，该硅层的材料包括多晶硅或非晶硅。18. The pixel structure according to claim 11, wherein the material of the silicon layer comprises polysilicon or amorphous silicon. 19.根据权利要求11所述的像素结构，其特征在于，该栅介电层的材料包括氧化硅、氮化硅或氮氧化硅。19. The pixel structure according to claim 11, wherein the material of the gate dielectric layer comprises silicon oxide, silicon nitride or silicon oxynitride. 20.根据权利要求11所述的像素结构，其特征在于，该像素电极的材料包括氧化铟锡、氧化铟锌或氧化铝锌。20. The pixel structure according to claim 11, wherein the material of the pixel electrode comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide. 21.一种像素结构，适用于一液晶显示器，其特征在于，该像素结构包括：21. A pixel structure suitable for a liquid crystal display, characterized in that the pixel structure comprises: 一薄膜晶体管，位于一基板的一主动区上，该薄膜晶体管包括：A thin film transistor located on an active area of a substrate, the thin film transistor comprising: 一主动堆栈，该主动堆栈由下至上依序具有一金属遮光层、一介电层与一硅岛，该金属遮光层、该介电层与该硅岛具有相同的图案，且该硅岛的两端具有重掺杂的一源极区与一漏极区；An active stack, the active stack has a metal light-shielding layer, a dielectric layer and a silicon island in sequence from bottom to top, the metal light-shielding layer, the dielectric layer and the silicon island have the same pattern, and the silicon island a source region and a drain region with heavy doping at both ends; 一栅介电层，位于该主动堆栈之上；以及a gate dielectric layer over the active stack; and 至少一栅极，位于该主动堆栈上方的该栅介电层上；at least one gate on the gate dielectric layer above the active stack; 一储存电容器，位于该基板的一电容区上，该储存电容器由下至上依序具有一第一电极、一电容介电层与一第二电极，其中该第二电极为重掺杂的一硅层且与该漏极区电性相接；以及A storage capacitor, located on a capacitance region of the substrate, the storage capacitor has a first electrode, a capacitor dielectric layer and a second electrode in sequence from bottom to top, wherein the second electrode is a heavily doped silicon layer and is in electrical contact with the drain region; and 一扫描线，电性连接于该至少一栅极；a scan line electrically connected to the at least one gate; 一第二介电层，位于该栅介电层、该至少一栅极与该扫描线之上；a second dielectric layer located on the gate dielectric layer, the at least one gate and the scan line; 一数据线，位于该第二介电层上；a data line located on the second dielectric layer; 一第一导线，位于该第二介电层上，电性连接该数据线与该源极区；a first wire, located on the second dielectric layer, electrically connecting the data line and the source region; 一第二导线，位于该第二介电层上，电性连接该漏极区与该第二电极；以及a second wire, located on the second dielectric layer, electrically connecting the drain region and the second electrode; and 一像素电极，电性连接该第二导线。A pixel electrode is electrically connected to the second wire. 22.根据权利要求21所述的像素结构，其特征在于，还包括二个淡掺杂区，分别位于该源极区与该漏极区的内侧。22. The pixel structure according to claim 21, further comprising two lightly doped regions located inside the source region and the drain region respectively. 23.根据权利要求21所述的像素结构，其特征在于，还包括：23. The pixel structure according to claim 21, further comprising: 一电容线，电性连接于该储存电容器，该电容线的结构由下至上与该储存电容器相同；以及a capacitance line, electrically connected to the storage capacitor, the structure of the capacitance line is the same as that of the storage capacitor from bottom to top; and 一第一端子位于该电容线的末端，该第一端子由一第一金属层所构成，该第一端子之上具有一保护层，该保护层与该像素电极由同一透明导电层所构成。A first terminal is located at the end of the capacitance line. The first terminal is made of a first metal layer. There is a protective layer on the first terminal. The protective layer and the pixel electrode are made of the same transparent conductive layer. 24.根据权利要求23所述的像素结构，其特征在于，还包括一第二端子位于该扫描线的末端，以及一第三端子位于该数据线的末端。24. The pixel structure according to claim 23, further comprising a second terminal located at the end of the scan line, and a third terminal located at the end of the data line. 25.根据权利要求24所述的像素结构，其特征在于，该扫描线、该至少一栅极与该第二端子由一第二金属层所构成，以及该数据线、该第一导线、该第二导线与该第三端子由一第三金属层所构成。25. The pixel structure according to claim 24, wherein the scan line, the at least one gate and the second terminal are formed by a second metal layer, and the data line, the first wire, the The second wire and the third terminal are formed by a third metal layer. 26.根据权利要求21所述的像素结构，其特征在于，部分的该扫描线位于该主动堆栈上方的该栅介电层上。26. The pixel structure according to claim 21, wherein a part of the scan line is located on the gate dielectric layer above the active stack. 27.根据权利要求21所述的像素结构，其特征在于，该硅层的材料包括多晶硅或非晶硅。27. The pixel structure according to claim 21, wherein the material of the silicon layer comprises polysilicon or amorphous silicon. 28.根据权利要求21所述的像素结构，其特征在于，该栅介电层的材料包括氧化硅、氮化硅或氮氧化硅。28. The pixel structure according to claim 21, wherein the material of the gate dielectric layer comprises silicon oxide, silicon nitride or silicon oxynitride. 29.根据权利要求21所述的像素结构，其特征在于，该像素电极的材料包括氧化铟锡、氧化铟锌或氧化铝锌。29. The pixel structure according to claim 21, wherein the material of the pixel electrode comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide.
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