CN100464241C - Picture element structure of liquid crystal display device and producing method thereof - Google Patents
Picture element structure of liquid crystal display device and producing method thereof Download PDFInfo
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- CN100464241C CN100464241C CNB200710127222XA CN200710127222A CN100464241C CN 100464241 C CN100464241 C CN 100464241C CN B200710127222X A CNB200710127222X A CN B200710127222XA CN 200710127222 A CN200710127222 A CN 200710127222A CN 100464241 C CN100464241 C CN 100464241C
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Abstract
The invention discloses a pixel structure for LCD and the making method thereof. In the pixel structure, it uses metallic layer/dielectric layer/heavy doped silicon layer to compose lower electrode/capacitor dielectric layer/upper electrode of a storage capacitor, respectively, to increase the capacity of the storage capacitor; besides, it forms metal screening layer at the bottom of TFT to reduce light leakage current occurrence. Thus, as compared with the existing storage capacitor composed of non-doped silicon layer, gate dielectric layer and metallic layer, the capacity of the storage capacitor in the invention can be largely increased. Besides, a metal screening layer is added under the TFT to stop light leakage current occurring.
Description
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, and relate in particular to a kind of dot structure and manufacture method thereof of LCD.
Background technology
In the dot structure of available liquid crystal display, if its thin film transistor (TFT) is the structure of top grid (top gate), then the silicon island of the bottom electrode of its reservior capacitor and thin film transistor (TFT) is usually by being constituted with one deck silicon layer, and the grid of the top electrode of reservior capacitor and thin film transistor (TFT) is usually by being constituted with one deck metal level.Cause when coming that with the grid and the mask that powers on very above-mentioned silicon layer carried out ion doping, because the top electrode of reservior capacitor covers in bottom electrode, therefore can't carry out effective ion doping to bottom electrode, cause the storage capacitors amount that can't effectively increase reservior capacitor.And thin film transistor (TFT) also produces leakage current because of irradiation easily.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of dot structure and manufacture method thereof that is applicable to LCD.
For achieving the above object, the invention provides a kind of dot structure, be applicable to a LCD, this dot structure comprises at least: a thin film transistor (TFT), be positioned on the active region of a substrate, this thin film transistor (TFT) comprises: an active storehouse, and this active storehouse has a metal light shield layer, a dielectric layer and a silicon island from the bottom to top in regular turn, and the two ends of this silicon island have a heavily doped one source pole district and a drain region; One gate dielectric layer is positioned on this active storehouse; And at least one grid, be positioned on this gate dielectric layer of this active storehouse top; One reservior capacitor, be positioned on the capacitive region of this substrate, this reservior capacitor has one first electrode, a capacitance dielectric layer and one second electrode from the bottom to top in regular turn, wherein this first electrode and this metal light shield layer are made of a discontinuous the first metal layer, this capacitance dielectric layer and this dielectric layer are made of discontinuous one first dielectric layer, this second electrode and this silicon island are made of a discontinuous silicon layer, and this second electrode is heavy doping and is electrically connected with this drain region; And a pixel electrode, be electrically connected with this second electrode.
And, for achieving the above object, the invention provides a kind of manufacture method of display picture element structure, at first, on substrate, form the first metal layer, first dielectric layer and silicon layer in regular turn, this metal level of patterning, first dielectric layer and silicon layer then form initiatively storehouse and electric capacity storehouse respectively on the active region of substrate and capacitive region, and the electric capacity line that is connected with the electric capacity storehouse of formation.Then, at substrate, initiatively form the gate dielectric layer and second metal level in regular turn on storehouse, electric capacity storehouse and the electric capacity line, patterning second metal level again, with at least one grid of formation above the active storehouse, and the sweep trace that links to each other with grid.With grid and sweep trace is the doping mask, and the silicon layer of active storehouse, electric capacity storehouse and electric capacity line is carried out heavy doping technology to form a plurality of heavily doped regions.Wherein, initiatively the heavily doped region at the silicon layer two ends of storehouse is respectively source area and drain region, and the first metal layer of electric capacity storehouse and heavily doped region are respectively first electrode and second electrode that constitutes reservior capacitor.
Then, form second dielectric layer on gate dielectric layer, grid and sweep trace, patterning second dielectric layer exposes source area, drain region and second electrode respectively to form first opening, second opening and the 3rd opening again.Then, form the 3rd metal level and be covered on second dielectric layer, patterning the 3rd metal level forms data line, electrically connects first lead of data line and source area and second lead that electrically connects the drain region and second electrode again.Then, form flatness layer on second dielectric layer, data line, first lead and second lead, the patterning flatness layer forms the 4th opening to expose second lead then.Then, forming transparency conducting layer on the flatness layer with among the 4th opening, patterned transparent conductive layer forms the pixel electrode that is electrically connected with second lead again.
Adopt the present invention, in the part of reservior capacitor, its bottom electrode (also being the first electrode 105b) is made of metal, and its top electrode (also being the second electrode 130c) is made of heavily doped silicon layer.Therefore, and compare down, can significantly increase the electric capacity of reservior capacitor by the reservior capacitor of the prior art that non-doped silicon layer, gate dielectric layer and metal level constituted.In addition, the below of thin film transistor (TFT) is many layer of metal light shield layer also, with the blocking-up photo leakage current.
Description of drawings
State with other purpose, feature, advantage and embodiment and can become apparent on the present invention for allowing, being described in detail as follows of appended accompanying drawing:
Please refer to Figure 1A-Fig. 6 B, it illustrates the manufacturing process synoptic diagram according to the dot structure of a kind of LCD of the single grid embodiment of the present invention.
Please refer to Fig. 7 A-Fig. 7 B, it illustrates the synoptic diagram according to the dot structure of a kind of LCD of bigrid embodiment of the present invention.
Wherein, Reference numeral:
100: substrate 105a: the metal light shield layer
105b: the first electrode 105c: the first terminal
110b: capacitance dielectric layer 110a: first dielectric layer
110d: the first dielectric layer 110c: first dielectric layer
115b: silicon layer 115a: silicon island
115d: silicon layer 115c: silicon layer
118b: electric capacity storehouse 118a: active storehouse
118d: electric capacity line 118c: terminal storehouse
125a: grid 120: gate dielectric layer
125c: the second terminal 125b: sweep trace
130b: drain region 130a: source area
130d: heavily doped region 130c: second electrode
130f: heavily doped region 130e: heavily doped region
145b: the second opening 145a: first opening
145d: the 4th opening 145c: the 3rd opening
150b: data line 150a: first lead
150d: the 3rd terminal 150c: second lead
160a: the 5th opening 155: flatness layer
165a: pixel electrode 160b: the 6th opening
165b: protective seam
Embodiment
Single grid embodiment:
Please refer to Figure 1A-Fig. 6 B, it illustrates the manufacturing process synoptic diagram according to the dot structure of a kind of LCD of the single grid embodiment of the present invention.
Please earlier with reference to Figure 1A-Figure 1B, Figure 1A is a vertical view, and Figure 1B is AA ', BB ', the CC ' cross-sectional view of Figure 1A.On substrate 100, form earlier the first metal layer, first dielectric layer and silicon layer in regular turn, patterning the first metal layer, first dielectric layer and silicon layer then, forms active storehouse 118a, electric capacity storehouse 118b and terminal storehouse 118c respectively in active region (profile line AA '), capacitive region (profile line BB ') and terminal region (profile line CC ') respectively, and the electric capacity line 118d that is connected with terminal storehouse 118c with electric capacity storehouse 118b.The material of above-mentioned silicon layer for example can be polysilicon or amorphous silicon, and the material of first dielectric layer for example can be monox.
Above-mentioned active storehouse 118a is formed by metal light shield layer 105a, the first dielectric layer 110a and silicon island 115a storehouse, and wherein metal light shield layer 105a is made of the first metal layer, and silicon island 115a is made of silicon layer.Electric capacity storehouse 118b is formed by the first electrode 105b, capacitance dielectric layer 110b and silicon layer 115b storehouse, and wherein the first electrode 105b is made of the first metal layer, and capacitance dielectric layer 110b is made of first dielectric layer.Terminal storehouse 118c is formed by the first terminal 105c, the first dielectric layer 110c and silicon layer 115c storehouse, and the first terminal 105c is made of the first metal layer.And above-mentioned electric capacity line 118d (Figure 1A), it is formed by the first metal layer, first dielectric layer and silicon layer storehouse, can only see the silicon layer 115d of the superiors at 1A figure.
Please earlier with reference to Fig. 2 A-Fig. 2 B, Fig. 2 A is a vertical view, and Fig. 2 B is AA ', BB ', the CC ' cross-sectional view of Fig. 2 A.On substrate 100, active storehouse 118a, electric capacity storehouse 118b, terminal storehouse 118c and electric capacity line 118d, form the gate dielectric layer 120 and second metal level in regular turn earlier, patterning second metal level then is to form grid 125a and the sweep trace 125b that links to each other with grid 125a and the second terminal 125c on active storehouse 118a.Then, being the doping mask with grid 125a carries out heavy doping technology to silicon island 115a and silicon layer 115b, 115c, 115d, to form heavily doped region.The heavily doped region that wherein is arranged in silicon island 115a is respectively as source area 130a and drain region 130b, and heavily doped silicon layer 115b is as the second electrode 130c, and the heavily doped region 130e that is arranged in silicon layer 115d.In addition, also have the heavily doped region 130d of position in silicon layer 115c.The first above-mentioned electrode 105b and the second electrode 130c form reservior capacitor.Above-mentioned gate dielectric layer 120 for example can be monox, silicon nitride or silicon oxynitride.
In addition, also optionally further isotropic etching grid 125a (and sweep trace 125b) is that the doping mask carries out light doping process to silicon island 115a with grid 125a again, forms light doped region 135.
Please refer to Fig. 3, on gate dielectric layer 120, grid 125a and sweep trace 125b and the second terminal 125c, form second dielectric layer 140 earlier.Then, patterning second dielectric layer 140 forms the first opening 145a, the second opening 145b, the 3rd opening 145c and the 4th opening 145d to expose source area 130a, drain region 130b, the second electrode 130c and heavily doped region 130d respectively among second dielectric layer 140.The material of the second above-mentioned dielectric layer 140 for example can be monox.
Please earlier with reference to Fig. 4 A-Fig. 4 B, Fig. 4 A is a vertical view, and Fig. 4 B is AA ', BB ', the CC ' cross-sectional view of Fig. 4 A.Forming the 3rd metal level on second dielectric layer 140 and among the first opening 145a, the second opening 145b, the 3rd opening 145c and the 4th opening 145d earlier.Then, patterning the 3rd metal level is with the 3rd terminal 150d that forms data line 150b, data line 150b end, connect the first lead 150a (via the first opening 145a) of data line 150b and source area 130a and be connected drain region 130b and the second lead 150c of the second electrode 130c (via the second opening 145b and the 3rd opening 145c).Simultaneously, also second metal level in the 4th opening 145d and the heavily doped region 130d that exposes are removed it, expose the first dielectric layer 110c.
Please refer to Fig. 5, then forming flatness layer 155 on second dielectric layer 140, data line 150b, the first lead 150a, the second lead 150c, the 3rd terminal 150d and among the 4th opening 145d.Then, patterning flatness layer 155 forms the 5th opening 160a and the 6th opening 160b in flatness layer 155.Wherein, the 5th opening 160a exposes the second lead 150c, and the 6th opening 160b then exposes the first terminal 105c.
Please earlier with reference to Fig. 6 A-Fig. 6 B, Fig. 6 A is a vertical view, and Fig. 6 B is AA ', BB ', the CC ' cross-sectional view of Fig. 6 A.Then, on flatness layer 155 and the interior formation transparency conducting layer of the 5th opening 160a, the 6th opening 160b.Patterned transparent conductive layer again is to form the protective seam 165b of pixel electrode 165a and the first terminal 105c.The material of above-mentioned transparency conducting layer for example can be tin indium oxide, indium zinc oxide or aluminum zinc oxide.
Bigrid embodiment:
Please refer to Fig. 7 A-Fig. 7 B, it illustrates the synoptic diagram according to the dot structure of a kind of LCD of bigrid embodiment of the present invention.Fig. 7 A is a vertical view, and Fig. 7 B is AA ', BB ', the CC ' cross-sectional view of Fig. 7 A.
Basically,, transistorized structure (is shown in profile line AA '), other basic structure identical (as profile line BB ' and profile line CC ') except being changed into the bigrid by single grid.Therefore the part of same structure all adopts the components identical label, repeats no more.In addition, because bigrid embodiment is also substantially the same with the manufacturing process of single grid embodiment, therefore also repeat no more.Below only narrated with regard to the part of thin-film transistor structure.
In Fig. 7 A, being shaped as of the active storehouse 118a of thin-film transistor structure is crooked, partly to overlap with grid 125a and sweep trace 125b, allows the part formation double-grid structure (125a, 125b) that overlaps.Section AA ' part in Fig. 7 B, grid 125a with as part of scanning line 125b, the source area 130a of grid, drain region 130b and heavily doped region 130f formation double-gate film transistor.In addition, also can be in manufacture process, be chosen in grid 125a and the both sides silicon layer and make light doped region 135 respectively as the part of scanning line 125b of grid.
From the above, in the part of reservior capacitor, its bottom electrode (also being the first electrode 105b) is made of metal, and its top electrode (also being the second electrode 130c) is made of heavily doped silicon layer.Therefore, and compare down, can significantly increase the electric capacity of reservior capacitor by the reservior capacitor of the prior art that non-doped silicon layer, gate dielectric layer and metal level constituted.In addition, the below of thin film transistor (TFT) is many layer of metal light shield layer also, with the blocking-up photo leakage current.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (29)
1. an one pixel structure process method is applicable to a LCD, it is characterized in that, this manufacture method comprises:
Form a first metal layer, one first dielectric layer and a silicon layer in regular turn on a substrate;
This first metal layer of patterning, this first dielectric layer and this silicon layer form initiatively a storehouse and an electric capacity storehouse respectively on an active region of this substrate and a capacitive region, and the electric capacity line that is connected with this electric capacity storehouse of formation;
Form a gate dielectric layer and one second metal level in regular turn on this substrate, this active storehouse, this electric capacity storehouse and this electric capacity line;
This second metal level of patterning, with at least one grid of formation above this active storehouse, and the one scan line that links to each other with this grid;
With this grid and this sweep trace is the doping mask, this silicon layer of this active storehouse, this silicon layer of this electric capacity storehouse and this silicon layer of this electric capacity line are carried out a heavy doping technology to form a plurality of heavily doped regions, wherein two heavily doped regions at these silicon layer two ends of this active storehouse are respectively an one source pole district and a drain region, and the heavily doped region of this first metal layer of this electric capacity storehouse and this electric capacity storehouse is respectively one first electrode and one second electrode that constitutes a reservior capacitor;
Form one second dielectric layer on this gate dielectric layer, this grid and this sweep trace;
This second dielectric layer of patterning exposes this source area, this drain region and this second electrode respectively to form one first opening, one second opening and one the 3rd opening;
Form one the 3rd metal level be covered on this second dielectric layer and this first opening, this second opening and the 3rd opening in;
Patterning the 3rd metal level forms a data line, electrically connects one first lead of this data line and this source area and electrically connects this drain region and one second lead of this second electrode;
Form a flatness layer on this second dielectric layer, this data line, this first lead and this second lead;
This flatness layer of patterning forms one the 5th opening to expose this second lead;
Form a transparency conducting layer on this flatness layer with the 5th opening among; And
This transparency conducting layer of patterning forms a pixel electrode that is electrically connected with this second lead.
2. method according to claim 1 is characterized in that, also comprises between the step of carrying out this heavy doping technology and this second dielectric layer of formation:
This grid of isotropic etching is to reduce the size of this grid; And
With this grid after the etching is the doping mask, and this silicon layer of this active storehouse is carried out a light doping process, forms a light doped region respectively with the inboard in this source area and this drain region.
3. method according to claim 1 is characterized in that, the end that also is included in this electric capacity line forms a first terminal, and the formation method of this first terminal comprises:
In the step of this first metal layer of patterning, this first dielectric layer and this silicon layer, form a terminal storehouse that connects this electric capacity line end;
In the step of this second dielectric layer of patterning, form one the 4th and be opened on this silicon layer that exposes this terminal storehouse in this second dielectric layer;
In the step of patterning the 3rd metal level, remove the 3rd metal level and this silicon layer on this terminal storehouse;
In the step of this flatness layer of patterning, remove this flatness layer on this terminal storehouse and this first dielectric layer to expose this first metal layer, this first metal layer of this terminal storehouse constitutes this first terminal; And
In the step of this transparency conducting layer of patterning, form a protective seam on this first terminal that exposes.
4. method according to claim 1 is characterized in that, also comprises in the step of this second metal level of patterning forming one second terminal, is electrically connected at the end of this sweep trace.
5. method according to claim 1 is characterized in that, also comprises in the step of this patterning the 3rd metal level forming one the 3rd terminal, is electrically connected at the end of this data line.
6. method according to claim 1 is characterized in that, this sweep trace of part is positioned on this gate dielectric layer of this active storehouse top.
7. method according to claim 1 is characterized in that the material of this silicon layer comprises polysilicon or amorphous silicon.
8. method according to claim 1 is characterized in that, the material of this first dielectric layer and this second dielectric layer comprises monox.
9. method according to claim 1 is characterized in that the material of this gate dielectric layer comprises monox, silicon nitride or silicon oxynitride.
10. method according to claim 1 is characterized in that the material of this transparency conducting layer comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
11. a dot structure is applicable to a LCD, it is characterized in that, this dot structure comprises at least:
One thin film transistor (TFT) is positioned on the active region of a substrate, and this thin film transistor (TFT) comprises:
One active storehouse, this active storehouse has a metal light shield layer, a dielectric layer and a silicon island from the bottom to top in regular turn, and the two ends of this silicon island have a heavily doped one source pole district and a drain region;
One gate dielectric layer is positioned on this active storehouse; And
At least one grid is positioned on this gate dielectric layer of this active storehouse top;
One reservior capacitor, be positioned on the capacitive region of this substrate, this reservior capacitor has one first electrode, a capacitance dielectric layer and one second electrode from the bottom to top in regular turn, wherein this first electrode and this metal light shield layer are made of a discontinuous the first metal layer, this capacitance dielectric layer and this dielectric layer are made of discontinuous one first dielectric layer, this second electrode and this silicon island are made of a discontinuous silicon layer, and this second electrode is heavy doping and is electrically connected with this drain region; And
One pixel electrode is electrically connected with this second electrode.
12. dot structure according to claim 11 is characterized in that, also comprises two light doped regions, lays respectively at the inboard of this source area and this drain region.
13. dot structure according to claim 11 is characterized in that, also comprises:
The one scan line is electrically connected at this at least one grid;
One second dielectric layer is positioned on this gate dielectric layer, this at least one grid and this sweep trace;
One data line is positioned on this second dielectric layer;
One first lead is positioned on this second dielectric layer, electrically connects this data line and this source area; And
One second lead is positioned on this second dielectric layer, electrically connects this drain region, this second electrode and this pixel electrode.
14. dot structure according to claim 13 is characterized in that, also comprises:
One electric capacity line is electrically connected at this reservior capacitor, and the structure of this electric capacity line is identical with this reservior capacitor from the bottom to top; And
One the first terminal is positioned at the end of this electric capacity line, and this first terminal is made of this first metal layer, has a protective seam on this first terminal, and this protective seam and this pixel electrode are made of same transparency conducting layer.
15. dot structure according to claim 14 is characterized in that, comprise that also one second terminal is positioned at the end of this sweep trace, and one the 3rd terminal is positioned at the end of this data line.
16. dot structure according to claim 15, it is characterized in that, this sweep trace, this at least one grid and this second terminal are made of one second metal level, and this data line, this first lead, this second lead and the 3rd terminal are made of one the 3rd metal level.
17. dot structure according to claim 13 is characterized in that, this sweep trace of part is positioned on this gate dielectric layer of this active storehouse top.
18. dot structure according to claim 11 is characterized in that, the material of this silicon layer comprises polysilicon or amorphous silicon.
19. dot structure according to claim 11 is characterized in that, the material of this gate dielectric layer comprises monox, silicon nitride or silicon oxynitride.
20. dot structure according to claim 11 is characterized in that, the material of this pixel electrode comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
21. a dot structure is applicable to a LCD, it is characterized in that, this dot structure comprises:
One thin film transistor (TFT) is positioned on the active region of a substrate, and this thin film transistor (TFT) comprises:
One active storehouse, this active storehouse has a metal light shield layer, a dielectric layer and a silicon island from the bottom to top in regular turn, and this metal light shield layer, this dielectric layer have identical pattern with this silicon island, and the two ends of this silicon island have a heavily doped one source pole district and a drain region;
One gate dielectric layer is positioned on this active storehouse; And
At least one grid is positioned on this gate dielectric layer of this active storehouse top;
One reservior capacitor is positioned on the capacitive region of this substrate, and this reservior capacitor has one first electrode, a capacitance dielectric layer and one second electrode from the bottom to top in regular turn, and wherein this second electrode is a heavily doped silicon layer and is electrically connected with this drain region; And
The one scan line is electrically connected at this at least one grid;
One second dielectric layer is positioned on this gate dielectric layer, this at least one grid and this sweep trace;
One data line is positioned on this second dielectric layer;
One first lead is positioned on this second dielectric layer, electrically connects this data line and this source area;
One second lead is positioned on this second dielectric layer, electrically connects this drain region and this second electrode; And
One pixel electrode electrically connects this second lead.
22. dot structure according to claim 21 is characterized in that, also comprises two light doped regions, lays respectively at the inboard of this source area and this drain region.
23. dot structure according to claim 21 is characterized in that, also comprises:
One electric capacity line is electrically connected at this reservior capacitor, and the structure of this electric capacity line is identical with this reservior capacitor from the bottom to top; And
One the first terminal is positioned at the end of this electric capacity line, and this first terminal is made of a first metal layer, has a protective seam on this first terminal, and this protective seam and this pixel electrode are made of same transparency conducting layer.
24. dot structure according to claim 23 is characterized in that, comprise that also one second terminal is positioned at the end of this sweep trace, and one the 3rd terminal is positioned at the end of this data line.
25. dot structure according to claim 24, it is characterized in that, this sweep trace, this at least one grid and this second terminal are made of one second metal level, and this data line, this first lead, this second lead and the 3rd terminal are made of one the 3rd metal level.
26. dot structure according to claim 21 is characterized in that, this sweep trace of part is positioned on this gate dielectric layer of this active storehouse top.
27. dot structure according to claim 21 is characterized in that, the material of this silicon layer comprises polysilicon or amorphous silicon.
28. dot structure according to claim 21 is characterized in that, the material of this gate dielectric layer comprises monox, silicon nitride or silicon oxynitride.
29. dot structure according to claim 21 is characterized in that, the material of this pixel electrode comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102269900B (en) | 2010-06-03 | 2013-04-24 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and making method thereof |
| CN102468308B (en) * | 2010-10-28 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate and method for manufacturing same and liquid crystal display |
| CN102420183B (en) * | 2011-12-07 | 2014-02-05 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) array substrate and TFT array substrate |
| CN102508376B (en) * | 2011-12-15 | 2014-07-16 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN102709243B (en) * | 2012-05-18 | 2015-04-29 | 京东方科技集团股份有限公司 | Organic light-emitting diode display panel and manufacturing method thereof |
| TWI495111B (en) * | 2013-03-22 | 2015-08-01 | Au Optronics Corp | Display panel and method of making the same |
| CN104793415A (en) * | 2014-01-17 | 2015-07-22 | 群创光电股份有限公司 | Thin film transistor substrate, display panel and display device |
| CN104465675B (en) * | 2014-12-31 | 2017-08-25 | 深圳市华星光电技术有限公司 | Thin-film transistor array base-plate, liquid crystal panel and liquid crystal display |
| CN104882414B (en) * | 2015-05-06 | 2018-07-10 | 深圳市华星光电技术有限公司 | The production method and its structure of TFT substrate |
| CN105826395A (en) * | 2016-04-28 | 2016-08-03 | 武汉华星光电技术有限公司 | Thin film transistor structure and manufacturing method thereof |
| CN105785682B (en) | 2016-05-23 | 2020-09-04 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method of array substrate |
| CN107134460B (en) * | 2017-04-11 | 2019-08-02 | 深圳市华星光电半导体显示技术有限公司 | Display device and its GOA circuit |
| CN107316873B (en) * | 2017-07-19 | 2020-03-10 | 武汉天马微电子有限公司 | Array substrate and display device |
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