CN100461389C - Planar pad design and production - Google Patents
Planar pad design and production Download PDFInfo
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- CN100461389C CN100461389C CNB200510025624XA CN200510025624A CN100461389C CN 100461389 C CN100461389 C CN 100461389C CN B200510025624X A CNB200510025624X A CN B200510025624XA CN 200510025624 A CN200510025624 A CN 200510025624A CN 100461389 C CN100461389 C CN 100461389C
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- salient point
- metal level
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The method is provided for designing and fabricating a flat bounding pad used in integrate circuit component and comprises: forming a metal layer on a substrate; the IC component has a passivation layer that surrounds the metal layer to form an opening; the two top sides of said passivation layer and metal layer define a successive plane; a under bump metallization structure is coupled to said successive plane; the said under bump metallization structure has a size and location capable of fully overlapping the top side of said metal layer; said under bump metallization structure is coupled to a salient point electrode; said salient point electrode has a 1 micron maximum surface roughness on its top side.
Description
Technical field
The present invention relates to integrated circuit and be used for process for fabrication of semiconductor device.More specifically, the invention provides the method and structure that is used to make the planar pad structure that is used for advanced integrated circuit (IC)-components, yet should be realized that the present invention has applicability more widely.
Background technology
Integrated circuit develops into millions of devices from the interconnect devices that is manufactured on the minority on the single silicon.Performance that the tradition integrated circuit provides and complexity are considerably beyond the imagination originally.For the raising of implementation complexity and current densities (that is, can be arranged to the quantity of the device on the given chip area), for integrated circuit, the size of minimum device live width (being also referred to as device " how much ") becomes more and more littler for each.
Constantly the current densities that increases has not only improved the complexity and the performance of integrated circuit, and provides more low cost components for the client.It is hundreds and thousands of ten thousand that integrated circuit or chip manufacturing factory may spend, even tens00000000 dollars.Each manufacturing works will have certain wafer throughput, and will have the integrated circuit of some on every wafer.Therefore, by making littler integrated circuit individual devices, more device can be fabricated on each wafer, so just can increase the output of manufacturing works.Making device is very challenging property more for a short time, because all there is restriction in each technology that is used for integrated manufacturing.That that is to say that a kind of given technology can only be worked into a certain specific live width size usually, and in whether technology is exactly that device layout need be changed.In addition, along with requirement on devices designs more and more fast, process technology limit exists with regard to following some traditional technology and material.
The example of such technology is the manufacturing of the pad structure of integrated circuit (IC)-components.It is more and more littler that such pad has become traditionally, and occupy the littler zone in the silicon substrate face.Though tangible improvement has been arranged, the design of pad structure still has many restrictions.As just example, it is more and more littler that these designs must become, but still will provide enough mechanical performance to support the bonding wire structure.Because usually there are the q﹠r problem in nonplanar bonding surface, traditional pad design in close spacing design.As shown in Figure 1, traditional pad structure 100 comprises passivation layer 102, and this passivation layer 102 is lifted to the top of the part of metal level 104.Need the elevated portion of passivation layer 102 to assign to seal following metal level zone 104.Unfortunately, the rising in the passivation layer 102 causes the salient point termination electrode inhomogenous surperficial 106, perhaps causes a convex surface (crown).In another traditional pad structure 200, by avoid directly overlying metal level zone 204 around (perhaps corresponding to the raised portion of passivation layer 202) zone, eliminate the formation of the convex surface on the surface 206.But this structure is owing to the total surface area that has reduced to can be used for bonding has been damaged bonding.In addition, traditional pad design usually requires complicated manufacturing process, for example the passivation layer of dual masks technology or rising.In this manual, more specifically hereinafter the restriction of these and other will be described in further detail.
Find out that from above the improvement technology that is used to handle semiconductor device is desirable.
Summary of the invention
According to the present invention, provide the technology that integrated circuit and its are used for the processing that semiconductor device makes that relates to.More specifically, the invention provides the method and structure that is used to make the planar pad that is used for advanced integrated circuit (IC)-components.Yet, should be realized that the present invention has applicability more widely.
In a specific embodiment, the invention provides a kind of integrated circuit (IC)-components.This integrated circuit (IC)-components comprises a substrate.The metal level zone is formed on the substrate.Integrated circuit (IC)-components also comprises a passivation layer, and this passivation layer has an opening that forms around the metal level zone.The top surface in passivation layer and metal level zone limits a continuous plane surface that has less than about 1 micron maximum surface roughness.Metallization structure is coupled to this continuous plane surface under the salient point, and the size of metallization structure and position are gone up the top surface in metal-clad zone fully under this salient point.Metallization structure is coupled to a salient point termination electrode under the salient point, and the top surface of this salient point termination electrode has less than about 1 micron maximum surface roughness.
In another embodiment, the invention provides a kind of method that is used to make the pad structure that is used for semiconductor device.The surface that is limited by metal level zone and passive area is provided.Polish this surface, have plane surface less than about 0.2 micron maximum surface roughness with generation.Above this plane surface, deposit PVD (physical vapour deposition (PVD)) the first film.This method also is included in PVD the first film top deposition PVD second film.Then, above metal level, deposit photoresist layer.The groove that utilizes first mask in photoresist layer, to align directly over patterning and the metal level zone.In groove, electroplate the salient point termination electrode.Afterwards, etching photoresist layer.Utilize the salient point termination electrode as self-aligned mask, etching PVD second and the first film layer.The top surface of salient point termination electrode has less than about 1 micron maximum surface roughness.
Than conventional art, the lot of advantages that has obtained by the present invention.For example, present technique is provided convenience for using the technology that depends on conventional art.In certain embodiments, this method provides the planar pad technology.In addition, this method provides compatible and need not carry out the technology of substantial modification to legacy equipment and technology with conventional process techniques.According to embodiment, can obtain one or more in these advantages.These advantages or other advantages are incited somebody to action in this specification and more specifically hereinafter, are more described.
With reference to the detailed description and the accompanying drawing of back, can more fully understand various other purposes of the present invention, feature and advantage.
Description of drawings
Fig. 1 shows the reduced graph of the viewgraph of cross-section of traditional pad structure;
Fig. 2 shows the reduced graph of the viewgraph of cross-section of another traditional pad structure;
Fig. 3 shows the reduced graph of the viewgraph of cross-section of pad structure according to an embodiment of the invention;
Fig. 4 shows the reduced graph of the viewgraph of cross-section of pad structure according to an embodiment of the invention;
Fig. 5 shows the reduced graph of the viewgraph of cross-section of pad structure according to an embodiment of the invention; With
Fig. 6 shows and is used to make the method for pad structure according to an embodiment of the invention.
Embodiment
According to the present invention, provide the technology that integrated circuit and its are used for the processing that semiconductor device makes that relates to.More specifically, the invention provides the method and structure that is used to make the planar pad that is used for advanced integrated circuit (IC)-components.Yet, should be realized that the present invention has applicability more widely.
Fig. 3 shows the reduced graph of the viewgraph of cross-section of pad structure 300 according to an embodiment of the invention.This figure only is an example, should not limit the scope of invention here.Those of ordinary skill in the art will recognize a lot of variations, substitute and revise.As shown in the figure, pad structure 300 comprises substrate 302.Preferably, substrate 302 is silicon wafer or Silicon-On-Insulator wafer etc.Substrate 302 comprises electronic device (such as MOS device, resistor, transistor, diode, capacitor etc.) usually thereon or therein.
In this specific embodiment, passivation layer 303 overlies substrate 302.In optional embodiment, one deck or multilayer intermediate layer can be disposed between passivation layer 303 and the substrate 302.Passivation layer 303 guarantees the chemical stability on surface 309.In other words, it is inactive to make that surface 309 becomes chemistry, and oxidation is prevented from.Passivation layer 303 self can comprise one deck or multilayer.For example, the ground floor 304 of passivation layer 303 can comprise silica (SiO), and the second layer 306 can comprise silicon nitride (SiN) or silicon oxynitride (SiO
xN
y).Passivation layer 303 has the opening that forms around metal level zone 308.Metal level zone 308 can comprise aluminium (Al) or copper (Cu) usually, and other metals.The top surface in passivation layer and metal level zone 308 limits a continuous plane surface 310, and surface 310 is level and smooth substantially in other words.Preferably, continuous plane surface 310 has less than about 0.4 micron maximum surface roughness, perhaps more preferably, and less than about 0.2 micron maximum surface roughness.
Salient point metallization (UBM) structure 311 down is disposed on the surface 310.In this exemplary embodiment, UBM structure 311 can be a sandwich construction.For example, UBM ground floor 312 can be the physical vapour deposition (PVD) film 312 of titanium tungsten (TiW) or chromium etc.Simultaneously, the UBM second layer 314 can be PVD second thin layer 314 of gold (Au) or copper (Cu) etc.
The UBM structure 311 that is coupled to continuous plane surface 310 is oriented to overlie fully the top surface in metal level zone 308.By extending UBM structure 311 by this way, UBM structure 311 provides gas-tight seal above metal level zone 308.UBM structure 311 also is coupled to salient point termination electrode 316.The top surface 318 of salient point termination electrode 316 does not comprise convex surface.In fact, top surface 318 can have less than about 1 micron maximum surface roughness, perhaps more preferably, and less than about 0.8 micron maximum surface roughness.Like this, top surface 318 just at close spacing design aspect for improving bonding and providing a horizontal surface for the integrated level of improving interconnection structure.
Salient point termination electrode 316 and UBM structure 311 can have width and length about equally.But, in optional embodiment, need not to be such.The size of salient point termination electrode 316 and UBM structure 311 can change at concrete application.For example, advanced integrated circuit can have scope from about 30 microns to 20 microns or even littler salient point termination electrode and UBM structure.Pad structure 300 will depend on both height of salient point termination electrode 316 and UBM structure 311 from the height of continuous plane surface 310.Usually, under hard-core situation, the height of pad structure 300 is from about 10 microns to 20 microns scope.Should be noted that the top surface 318 of salient point termination electrode 316 preferably has the shape of rectangle, but it also can have arbitrary arbitrary shape (for example, ellipse, square, circle, polygon etc.).
Fig. 4 shows the reduced graph of the viewgraph of cross-section of pad structure 400 according to an embodiment of the invention.This figure only is an example, should not limit the scope of invention here.Those of ordinary skill in the art will recognize a lot of variations, substitute and revise.
As shown in the figure, pad structure 400 comprises passivation layer, and this passivation layer comprises the ground floor 404 and the second layer 406.As discussed above, these layers can comprise silica material, silicon nitride material, silicon oxynitride material, with and combination.In this specific embodiment, two metal level zones 408,410 are coupling in the passivation layer. Metal level zone 408 and 410 can be a same material, but this not necessarily.Ground floor 404 has the opening that forms around metal level zone 408, and the second layer 406 has the opening that forms around metal level zone 410.The second layer 406 and metal level zone 410 limit continuous plane surface 412.Surface 412 have less than about 0.4 micron preferred less than about 0.2 micron maximum surface roughness.UBM structure and salient point termination electrode be disposed in metal level zone 408,410 directly over.
Fig. 5 shows the reduced graph of the viewgraph of cross-section of pad structure 500 according to an embodiment of the invention.This figure only is an example, should not limit the scope of invention here.Those of ordinary skill in the art will recognize a lot of variations, substitute and revise.Pad structure 500 comprises three metal level zones that are coupling in substrate top and the passive area.Passive area comprises three layers.In this specific embodiment, the top surface in the top surface of passive area and metal level zone together limits a plane surface.And the layer in the pad structure 500 all is the plane such as each layer in the layer of passive area, UBM structure and salient point termination electrode, perhaps preferably has less than about 0.8 micron maximum surface roughness.
Fig. 6 is used to make the method for simplifying of pad structure according to an embodiment of the invention.Method 600 comprises following technology:
1. technology 602, and the surface that comprises around the passivation layer in metal level zone is provided.
2. technology 604, polish this surface, make its substantially flat.In one embodiment, can use CMP (Chemical Mechanical Polishing) process.
3. technology 606, deposition PVD the first film.This film is the bottom that is used for the UBM structure.
4. technology 608, and deposition is used for PVD second thin layer of UBM structure.
5. technology 610, at UBM superstructure deposition photoresist.
6. technology 612, utilize photoetching technique, and pattern dissolves groove directly over (some) metal levels zone in photoresist.
7. technology 614, electroplate the salient point termination electrode in this groove.
8. technology 616, etch away photoresist (and any other photoetching film, for example any anti-reflecting layer).Etching agent can be traditional light carving rubber stripper.
9. technology 618, utilize the salient point termination electrode as mask, etching UBM structure (that is, PVD second and the first film layer).Etching agent can be the KI (KI) that is used for etching gold (Au), and the hydrogen peroxide (H that is used for etching titanium tungsten (TiW)
2O
2).
10. technology 620, and pad structure is annealed.
The technology of said sequence provides method according to an embodiment of the invention.In this embodiment, only need a mask to form pad structure.Many other alternative methods can also be provided, wherein under the situation of the scope that does not deviate from the claim here, add some step, leave out one or more steps, perhaps one or more steps are provided according to different orders.For example, Fu Jia technology is provided to form the additional metal level zone in the passivation layer.In this specification, more specifically hereinafter, can find the more details of this method.
It should also be understood that, example as described herein and embodiment are just for illustrative purposes, those of ordinary skill in the art can carry out various modifications or variation to the present invention according to above-mentioned example and embodiment, these modifications and variations will be included in the application's the spirit and scope, and also within the scope of the appended claims.
Claims (23)
1. integrated circuit (IC)-components comprises:
A substrate;
A metal level zone is formed on the described substrate;
A passivation layer has an opening that forms around described metal level zone;
A continuous plane surface is limited by the top surface in described passivation layer and described metal level zone, and described continuous planar surface has the maximum surface roughness less than 0.2 micron;
Metallization structure under the salient point is coupled to described continuous plane surface, and the size of metallization structure and position are covered the described top surface in described metal level zone at least fully under the described salient point; With
A salient point termination electrode is coupled to metallization structure under the described salient point,
Wherein, the top surface of described salient point termination electrode has the maximum surface roughness less than 1 micron.
2. integrated circuit (IC)-components according to claim 1, wherein said salient point termination electrode comprises gold.
3. integrated circuit (IC)-components according to claim 2, wherein said salient point termination electrode is electroplated onto metallization structure under the described salient point.
4. integrated circuit (IC)-components according to claim 1, wherein said passivation layer comprises the ground floor and the second layer, and described ground floor comprises silica, and the described second layer comprises at least a in silicon nitride and the silicon oxynitride.
5. integrated circuit (IC)-components according to claim 1, wherein said metal level zone comprises aluminium.
6. integrated circuit (IC)-components according to claim 1, wherein said metal level zone comprises copper.
7. integrated circuit (IC)-components according to claim 1, metallization structure comprises the physical vapour deposition (PVD) the first film adhesion/barrier and the second film wetting layer under the wherein said salient point.
8. integrated circuit (IC)-components according to claim 7, the wherein said second film wetting layer comprises gold.
9. integrated circuit (IC)-components according to claim 1, the length in wherein said metal level zone is less than 30 microns.
10. integrated circuit (IC)-components according to claim 1, the described top surface of wherein said salient point termination electrode be shaped as at least a in rectangle, square, ellipse, circle and the polygon.
11. integrated circuit (IC)-components according to claim 1, the described top surface of wherein said salient point termination electrode has the maximum surface roughness less than 0.8 micron.
12. an integrated circuit (IC)-components comprises:
A substrate;
A metal level zone is formed on the described substrate;
A silica material layer has an opening that forms around described metal level zone;
A silicon oxynitride material layer has an opening that forms around described metal level zone and overlies described silicon oxide layer;
A continuous plane surface is limited by the top surface in described silicon oxynitride layer and described metal level zone, and described continuous planar surface has the maximum surface roughness less than 0.2 micron;
A physical vapour deposition (PVD) the first film layer is coupled to described continuous plane surface, and the size of described physical vapour deposition (PVD) the first film layer and position are covered the described top surface in described metal level zone at least fully;
Physical vapour deposition (PVD) second thin layer overlies described physical vapour deposition (PVD) the first film layer, and the size of described physical vapour deposition (PVD) second thin layer and the first film layer and position are covered the described top surface in described metal level zone at least fully; With
An au bump termination electrode is coupled to described physical vapour deposition (PVD) second thin layer, and the size of described au bump termination electrode and position are covered the described top surface in described metal level zone at least fully,
Wherein, the top surface of described au bump termination electrode has the maximum surface roughness less than 1 micron.
13. an integrated circuit (IC)-components comprises:
A substrate;
A plurality of metal levels zone is formed on the described substrate;
A passivation layer has the opening that centers on each formation in described a plurality of metal levels zone;
A continuous plane surface is limited by the top surface in described passivation layer and described a plurality of metal levels zone, and described continuous planar surface has the maximum surface roughness less than 0.2 micron;
Metallization structure under a plurality of salient points, wherein each all is coupled to described continuous plane surface, and the size of each under described a plurality of salient points in the metallization structure and position are covered a top surface in described a plurality of metal levels zone at least fully; With
A plurality of salient point termination electrodes, wherein each all is coupled in the metallization structure under described a plurality of salient point,
Wherein, each top surface of described a plurality of salient point termination electrodes all has the maximum surface roughness less than 1 micron.
14. integrated circuit (IC)-components according to claim 13, the first salient point termination electrode in wherein said a plurality of salient point termination electrodes arrange 25 microns to 10 microns of second salient point termination electrodes in described a plurality of salient point termination electrodes.
15. a method that is used to make pad structure, this method comprises:
The surface that is limited by metal level zone and passive area is provided;
Polish described surface, have plane surface less than 0.2 micron maximum surface roughness with generation;
Deposition PVD the first film above described plane surface;
Deposition PVD second film above described PVD the first film;
Above described PVD second film, deposit photoresist layer;
Utilize first mask pattern in described photoresist layer to dissolve a groove, align directly over described groove and the described metal level zone;
Electroplate the salient point termination electrode in described groove, the top surface of described salient point termination electrode has the maximum surface roughness less than 1 micron;
The described photoresist layer of etching; And
Utilize described salient point termination electrode as self-aligned mask, described PVD second of etching and the first film.
16. method according to claim 15, wherein said polishing operation is finished by CMP (Chemical Mechanical Polishing) process.
17. method according to claim 15, wherein, each in described PVD second and the first film has the maximum surface roughness less than 0.2 micron.
18. method according to claim 15 also comprises described pad structure is annealed.
19. method according to claim 15, wherein said metal level zone comprises aluminium.
20. method according to claim 15, wherein said metal level zone comprises copper.
21. method according to claim 15, wherein said PVD second film comprises gold.
22. method according to claim 15, wherein said passive area comprises the ground floor and the second layer, and described ground floor comprises silica, and the described second layer comprises at least a in silicon nitride and the silicon oxynitride.
23. method according to claim 15, wherein said salient point termination electrode comprises gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510025624XA CN100461389C (en) | 2005-04-25 | 2005-04-25 | Planar pad design and production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510025624XA CN100461389C (en) | 2005-04-25 | 2005-04-25 | Planar pad design and production |
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| Publication Number | Publication Date |
|---|---|
| CN1855459A CN1855459A (en) | 2006-11-01 |
| CN100461389C true CN100461389C (en) | 2009-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200510025624XA Expired - Fee Related CN100461389C (en) | 2005-04-25 | 2005-04-25 | Planar pad design and production |
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| CN (1) | CN100461389C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794732B (en) * | 2012-11-02 | 2017-02-22 | 上海天马微电子有限公司 | Bonding pad structure and manufacturing method thereof |
| CN104793298B (en) * | 2015-04-13 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | Load board structure with side welding plate and manufacturing method of load board structure |
| US9601472B2 (en) * | 2015-04-24 | 2017-03-21 | Qualcomm Incorporated | Package on package (POP) device comprising solder connections between integrated circuit device packages |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1132934A (en) * | 1994-11-12 | 1996-10-09 | 株式会社东芝 | Semiconductor device |
| US6362090B1 (en) * | 1999-11-06 | 2002-03-26 | Korea Advanced Institute Of Science And Technology | Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method |
| US20030011069A1 (en) * | 2001-07-13 | 2003-01-16 | Kazutaka Shibata | Semiconductor device |
-
2005
- 2005-04-25 CN CNB200510025624XA patent/CN100461389C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1132934A (en) * | 1994-11-12 | 1996-10-09 | 株式会社东芝 | Semiconductor device |
| US6362090B1 (en) * | 1999-11-06 | 2002-03-26 | Korea Advanced Institute Of Science And Technology | Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method |
| US20030011069A1 (en) * | 2001-07-13 | 2003-01-16 | Kazutaka Shibata | Semiconductor device |
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| CN1855459A (en) | 2006-11-01 |
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