CN100456470C - Semi-fusible link system for a multi-layer integrated circuit and method of making same - Google Patents
Semi-fusible link system for a multi-layer integrated circuit and method of making same Download PDFInfo
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- CN100456470C CN100456470C CNB2004800187474A CN200480018747A CN100456470C CN 100456470 C CN100456470 C CN 100456470C CN B2004800187474 A CNB2004800187474 A CN B2004800187474A CN 200480018747 A CN200480018747 A CN 200480018747A CN 100456470 C CN100456470 C CN 100456470C
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- connection element
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Abstract
A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.
Description
Related application
The application requires the U.S. Provisional Application No.60/484 of submission on July 2nd, 2003,369 rights and interests, its title is " Thin Film Semi-Fusible Links in Sub-MicronProcesses ", with the U.S. Patent application No.10/777 that submitted on February 12nd, 2004,337 rights and interests, its title are " Semi-Fusible Link System for a Multi-LayerIntegrated Circuit and Method of Making Same ".
Technical field
The present invention relates generally to semi-fusible link system and method, relate more specifically to be used for this improved semi-fusible link system and the method for multilevel integration.
Background technology
Fusible connection is used in the integrated circuit (IC) usually to adjust one or more IC parameter.Typical fusible connection has good working condition and blown state.Under good working condition, fusible connection provides low-down resistance, and under blown state, fusible connection provides open circuit.The example application of fusible connection is to adjust the offset voltage have with the fusible IC that is connected of resistor in series, and the configuration resistor makes and can adjust the skew input of amplifier and the resistance between the ground by fusing suitably to connect.
Typical existing fusible link system comprises big MOS transistor selector circuit, and it provides big electric current with the fusible Connection Element that fuses.Useful chip space on the megacryst pipe waste IC of fusible connection.
The another kind of fusible connection that overcomes the problem relevant with big selector circuit is known as half fusible connection.Half fusible being connected has first resistance under the good working condition and have second high electrical resistance (not being open circuit) under blown state.Thin film resistor is used in typical prior art half fusible connection, and therefore its required magnitude of current of fusible connection that reduces to fuse also reduces IC and go up used amount of space.The example of half fusible connection is in U.S. Patent No. 6,246, and revealed in 243, this patent is incorporated into herein for your guidance.
United States Patent (USP) ' 243 generally comprise half fusible Connection Element, selection transistor, the active circuit that is connected to half fusible Connection Element and interconnection layer (as metal one deck) to be interconnected to half fusible Connection Element and semi-fusible link system.Yet the designing requirement of United States Patent (USP) ' 243 half fusible connection and active circuit all are connected to metal one deck, and this metal one deck prevents that half fusible Connection Element and active circuit from arranging on each other.Its design also requires selector circuit and fusible Connection Element on one deck.The result is that fusing Connection Element, active circuit and selector circuit must be horizontally arranged in on one deck with metal one deck, has wasted useful chip space.
Summary of the invention
Therefore, the semi-fusible link system and the method that the purpose of this invention is to provide a kind of improvement.
Further aim of the present invention provides such semi-fusible link system and method, the amount of space that it reduces to use on the integrated circuit.
Further aim of the present invention provides such semi-fusible link system and method, and its elimination need be arranged half fusible Connection Element and active circuit on one deck.
Further purpose of the present invention provides such semi-fusible link system and method, and its elimination need arrange half fusible Connection Element, active circuit and selector circuit on one deck.
Further purpose of the present invention provides such semi-fusible link system and method, wherein half fusible Connection Element can be different from active circuit institute position layer thereon layer on.
Further purpose of the present invention provides such semi-fusible link system and method, and wherein selector circuit can be on same one deck of half fusible Connection Element and/or on same one deck of active circuit.
Further purpose of the present invention provides such semi-fusible link system, and wherein half fusible Connection Element is positioned on the layer above or below the layer that active circuit is positioned at.
The present invention is derived from can be by providing source circuit on the ground floor that comprises metal one deck, half fusible Connection Element is provided on the second layer that comprises two layers on metal, and two layers on interconnecting metal one deck and metal with provide half fusible Connection Element be electrically coupled to active circuit and first or the second layer on selector circuit, with fusing half fusible Connection Element, thereby cause the parameter change in the active circuit of integrated circuit, realize half compacter fusible connection.
The invention provides a kind of semi-fusible link system that is used to comprise the multilevel integration of the active circuit on the ground floor with metal one deck, comprise half fusible Connection Element on the second layer with two layers on metal, metal is suitable for and the interconnection of metal one deck for two layers, and places the selector circuit on the ground floor.
In a preferred embodiment, semi-fusible link system can comprise at least one interconnection of two layers on coupling metal one deck and metal, is used to provide the electric coupling between half fusible Connection Element and the active circuit.Selector circuit can comprise half fusible Connection Element array on the second layer.Selector circuit can be selected an element in the half fusible Connection Element array.Selector circuit can comprise transistor.Selector circuit can comprise nmos pass transistor.Half fusible Connection Element can comprise silicochromium.The second layer can be positioned at the ground floor top.Half fusible Connection Element can be positioned at the top of active circuit.Half fusible Connection Element can be positioned at the top of active circuit and selector circuit.Half fusible Connection Element can comprise thin film resistor.The active circuit half fusible Connection Element that can fuse, thus the parameter change of integrated circuit caused.The selector circuit half fusible Connection Element that can fuse, thus the parameter change of integrated circuit caused.
The present invention further provides a kind of semi-fusible link system that is used for multilevel integration, this multilevel integration comprises the active circuit on the ground floor with metal one deck, this semi-fusible link system comprises half fusible Connection Element on the second layer, this second layer has and is suitable for and two layers on the metal of described metal one deck interconnection, with the selector circuit that places on the described ground floor, in described active circuit and the described selector circuit one the described half fusible Connection Element that is used to fuse, thus parameter change in the described integrated circuit caused.
The present invention also has the semi-fusible link system that is used for multilevel integration, this integrated circuit comprises the active circuit on the ground floor with metal one deck, this semi-fusible link system comprises half fusible Connection Element on the second layer, this second layer has and is suitable for and two layers on the metal of metal one deck interconnection, the second layer is above ground floor, at least one interconnection that coupling metal one deck and metal are two layers, it is used to provide the electric coupling between half fusible Connection Element and the active circuit and places selector circuit on the ground floor.
The present invention also has the semi-fusible link system that is used for multilevel integration, this integrated circuit comprises the active circuit on the ground floor with metal one deck, this semi-fusible link system comprises thin film resistor half fusible element on the second layer, this second layer has and is suitable for and two layers on the metal of metal one deck interconnection, the second layer is above ground floor, at least one interconnection that coupling metal one deck and metal are two layers, be used to provide the electric coupling between half fusible Connection Element and the active circuit, and selector circuit, comprise placing on the ground floor so that the selection transistor of fusing half fusible Connection Element.
The present invention further provides the method for making the semi-fusible link system that is used for multilevel integration, this method may further comprise the steps: be formed with source circuit and selector in silicon substrate, deposit first dielectric layer above substrate, depositing metal one deck above the contact, deposit second dielectric layer above metal one deck, on second dielectric layer, form half fusible Connection Element with thin film resistor body, deposit the 3rd dielectric layer above half fusible Connection Element, in the 3rd dielectric layer, provide the contact, depositing metal is two layers on the 3rd dielectric layer, the passivation layer of deposit the 3rd dielectric layer, and interconnection between two layers on metal one deck and the metal is provided.
In one embodiment, the method for making the semi-fusible link system be used for multilevel integration further is included in the step that the contact is provided on the first and the 3rd dielectric layer.
Description of drawings
Those skilled in the art will understand other purpose of the present invention from the explanation of following preferred embodiment and accompanying drawing, feature and advantage, wherein:
Fig. 1 is the circuit diagram of typical prior art semi-fusible link system;
Fig. 2 is the schematic section of prior art semi-fusible link system, and it is illustrated in half fusible jockey and the active circuit that is spaced laterally apart on the IC chip;
Fig. 3 is the schematic section that the present invention is used for the semi-fusible link system of multilevel integration;
Fig. 4 A and 4B are the exemplary circuit figure of the semi-fusible link system shown in Fig. 3; With
Fig. 5 A-5H is a side cross-sectional view, and it illustrates an example of the related step of method of making the semi-fusible link system that is used for multilevel integration of the present invention.
Embodiment
Except preferred embodiment or the embodiment that discloses below, the present invention can have other embodiment or implement by different way or carry out.Just, being appreciated that the present invention is not limited to the following describes its details to component construction and layout that provides in book or the accompanying drawing.
Discuss like that as top background technology part, prior art semi-fusible link system 10 generally includes half fusible Connection Element 12 and selection transistor 14 (as, nmos pass transistor).When half fusible connection 12 is selected will be by fusing the time, the logic-high signal activating transistor 14 at grid 16 places.The half fusible connection 12 of current fusing in the drain electrode 18 causes that the resistance of half fusible Connection Element 12 changes.The resistance of half fusible Connection Element 12 changes the parameter change that can be used to cause the active circuit 20 that is coupled to semi-fusible link system 10.
Shown in details among Fig. 2 was further, the design of prior art system 10 partly fusible Connection Element 12, selection transistor 14 and active circuit 20 was arranged on same one deck 22 of integrated circuit 24.Metal one deck 26 is used to through conductor 28 interconnection active circuits 20 and half fusible Connection Element 12, and will half fusible Connection Element 12 be interconnected to through conductor 30 and selects transistor 14.Require these devices on the layer 22 of integrated circuit 24, to arrange the lateral separation with metal one deck 26 interconnection active circuits 20, half fusible Connection Element 12 and selector transistor 14.
Compare, the semi-fusible link system 40 that the present invention among Fig. 3 is used for multilevel integration 42 comprises the active circuit 44 that is placed on the ground floor 46.Layer 46 comprises metal one deck 48.System 40 also comprises the half fusible Connection Element 50 that is placed on the second layer 52, and the second layer 52 has metal two layer 54, and it is suitable for interconnecting metal one deck 48.Although as shown in Figure 3, the layer 52 that has half fusible connection 50 is positioned in layer 46 top that have active circuit 44, and the present invention is not limited to this, can be placed in layer 52 top that have half fusible Connection Element 50 because have the layer 46 of active circuit 44.Ideally, half fusible Connection Element 50 is thin film resistors, and its 1.0 microns wide, 0.8 micron long and about 0.005 (50
) micron thickness.
The method of semi-fusible link system 40 of the present invention is included in the step that forms the active circuit 44 of Fig. 5 A in the silicon substrate 80 in the shop drawings 4.In Fig. 5 B, dielectric layer 82 is deposited on the silicon substrate 80 then.The complanation of execution level 82 so that the surface 84 of dielectric layer 82 flatten.The technology that is used for complanation can comprise to be used SOG (spin-on-glass), chemico-mechanical polishing (CMP) or uses the dielectric layer that highly mixes up, and this dielectric layer refluxes in stove then, or any other well known to a person skilled in the art technology.Dielectric layer 82 is used to metal one deck and silicon device electricity are isolated.
Shown in Fig. 5 C, etching contact holes 86 in dielectric layer 82 then.Shown in Fig. 5 D, then by with barrier layer/bonding (glue) metal (as, TiW or Ti/Tin) lining (lining) hole 86, and fill these holes and form contact 90 with tungsten or materials similar.Depositing metal one deck 48 and form pattern and etching above contact 90 then.Metal one deck 48 can comprise aluminium copper (AlCu) layer and/or titanium nitride (TiN) layer.Shown in Fig. 5 E, dielectric layer 92 is deposited on metal one deck 44 then with metal one deck 44 and two layers of isolation of metal.As mentioned above, on the surface 94 of dielectric layer 92, carry out complanation.
Fig. 5 F illustrates, and the thin film resistor body 98 that is used for half fusible Connection Element 50 is by the layer 95 that at first deposit is made up of SiCr ideally on dielectric layer 92, then on layer 95 deposit by titanium tungsten (TiW) form layers 96 and form. Layer 95 and 96 is by mask and etching, so that form thin film resistor body 98.
Fig. 5 G illustrates, and dielectric layer 100 is deposited on half fusible Connection Element 50 and dielectric layer 92 tops then.Contact 102 is to form in the mode similar to above-mentioned contact.Metal is deposited on dielectric layer 100 tops for two layer 54 then.
Shown in Fig. 5 H, deposit passivation layer 102 above layer 100 then.Ideally, passivation layer 102 is dielectric materials, and can comprise silica and silicon nitride layer (not shown).
Though above-mentioned technology is used for double layer of metal, can repeat this technology to make semi-fusible link system, it comprises one or above additional metal levels.In addition, in manufacturing process, the conductor 56 shown in the dotted line can be integrated in the procedure of processing, thereby provides electric interconnection between two layer 54 on metal one deck 48 and metal, and this enables electrical couplings half fusible connection 50 and active circuit 44.In addition, or alternatively, half fusible Connection Element 50 can be placed between any two metal levels.
Though the specific feature of the present invention is shown in some figure, and do not illustrate in other figure, this is for convenience because according to the present invention, each feature can with all or the combination of any further feature.Here used speech " includes ", and " comprising ", the extensive and detailed ground explain of " having " and " having " quilt, and be not limited to any physical interconnections.And any embodiment that discloses in target application can not be taken as unique possible embodiment.
Those skilled in the art will expect other embodiment, and in these embodiment claim below.
Claims (34)
1. semi-fusible link system that is used for multilevel integration, multilevel integration comprises the active circuit on the ground floor, and this ground floor has metal one deck, and this semi-fusible link system comprises:
Half fusible Connection Element on the second layer, the described second layer have be suitable for two layers on the metal of described metal one deck interconnection and
Place the selector circuit on the described ground floor.
2. semi-fusible link system as claimed in claim 1, further comprise at least one interconnection, two layers on described at least one interconnection described metal one deck of coupling and described metal are used to provide the electrical couplings between described half fusible Connection Element and the described active circuit.
3. semi-fusible link system as claimed in claim 1 further comprises the half fusible Connection Element array that places on the described second layer.
4. semi-fusible link system as claimed in claim 1, wherein said selector circuit are selected one and half fusible Connection Elements in the described half fusible Connection Element array.
5. semi-fusible link system as claimed in claim 3, wherein said selector circuit comprises transistor.
6. semi-fusible link system as claimed in claim 5, wherein said selector circuit comprises nmos pass transistor.
7. semi-fusible link system as claimed in claim 1, wherein said selector circuit comprises nmos pass transistor.
8. semi-fusible link system as claimed in claim 1, wherein said half fusible Connection Element comprises silicochromium.
9. semi-fusible link system as claimed in claim 1, the wherein said second layer are positioned at described ground floor top.
10. semi-fusible link system as claimed in claim 1, wherein said half fusible Connection Element places described top of active circuit.
11. semi-fusible link system as claimed in claim 1, wherein said half fusible Connection Element places described active circuit and described selector circuit top.
12. semi-fusible link system as claimed in claim 1, the described half fusible Connection Element of wherein said active circuit fusing is to cause the parameter change of described integrated circuit.
13. semi-fusible link system as claimed in claim 1, the described half fusible Connection Element of wherein said selector circuit fusing is to cause the parameter change of described integrated circuit.
14. semi-fusible link system as claimed in claim 1, wherein said half fusible Connection Element comprises thin film resistor.
15. a semi-fusible link system that is used for multilevel integration, this multilevel integration comprises the active circuit on the ground floor, and this ground floor has metal one deck, and this semi-fusible link system comprises:
Half fusible Connection Element on the second layer, the described second layer have and are suitable for and two layers on the metal of described metal one deck interconnection, and the described second layer is above described ground floor;
At least one interconnection, its be coupled two layers on described metal one deck and described metal are so that provide electrical couplings between described half fusible Connection Element and the described active circuit; With
Place the selector circuit on the described ground floor.
16. semi-fusible link system as claimed in claim 15, wherein said selector circuit comprises transistor.
17. semi-fusible link system as claimed in claim 16, wherein said selector circuit comprises nmos pass transistor.
18. semi-fusible link system as claimed in claim 15, wherein said half fusible Connection Element comprises silicochromium.
19. semi-fusible link system as claimed in claim 15, wherein said half fusible Connection Element comprises thin film resistor.
20. semi-fusible link system as claimed in claim 15, wherein said half fusible Connection Element is placed in described top of active circuit.
21. semi-fusible link system as claimed in claim 15, wherein said half fusible Connection Element is placed in described active circuit and described selector circuit top.
22. semi-fusible link system as claimed in claim 15, the described half fusible Connection Element of wherein said active circuit fusing, thus cause the parameter change of described integrated circuit.
23. semi-fusible link system as claimed in claim 15, the described half fusible Connection Element of wherein said selector circuit fusing, thus cause the parameter change of described integrated circuit.
24. a semi-fusible link system that is used for multilevel integration, this multilevel integration comprises the active circuit on the ground floor, and this ground floor has metal one deck, and this semi-fusible link system comprises:
Thin film resistor on the second layer half fusible Connection Element, this second layer have and are suitable for and two layers on the metal of described metal one deck interconnection, and the described second layer is above described ground floor;
At least one interconnection, described at least one interconnection is coupled to two layers on described metal with described metal one deck, so that the electrical couplings between described half fusible Connection Element and the described active circuit to be provided; With
Selector circuit, this selector circuit comprise the selection transistor that places on the described ground floor.
25. semi-fusible link system as claimed in claim 24, wherein said half fusible Connection Element comprises silicochromium.
26. semi-fusible link system as claimed in claim 24, wherein said half fusible Connection Element is placed in described top of active circuit.
27. semi-fusible link system as claimed in claim 24, wherein said half fusible Connection Element is placed in described active circuit and described selector circuit top.
28. semi-fusible link system as claimed in claim 24, the described half fusible Connection Element of wherein said active circuit fusing is to cause the parameter change of described integrated circuit.
29. semi-fusible link system as claimed in claim 24, the described half fusible Connection Element of wherein said selector circuit fusing is to cause the parameter change of described integrated circuit.
30. a semi-fusible link system that is used for multilevel integration, this multilevel integration comprises the active circuit on the ground floor, and this ground floor has metal one deck, and this semi-fusible link system comprises:
Have half fusible Connection Element on the second layer of two layers on metal, this metal is suitable for and the interconnection of described metal one deck for two layers; With
Place the selector circuit on the described ground floor, in described active circuit and the described selector circuit one the described half fusible Connection Element that is used to fuse, thus cause parameter change in the described integrated circuit.
31. a method that is used to make the semi-fusible link system that is used for multilevel integration, described method comprises:
In silicon substrate, be formed with source circuit and selector;
Deposit first dielectric layer above described substrate;
Depositing metal one deck above the contact;
Deposit second dielectric layer above described metal one deck;
On described second dielectric layer, form half fusible Connection Element with thin film resistor body;
Deposit the 3rd dielectric layer above described half fusible Connection Element;
Depositing metal is two layers on described the 3rd dielectric layer;
The passivation layer of described the 3rd dielectric layer of deposit; With
Between two layers on described metal one deck and described metal, provide interconnection.
32. half fusible jockey as claimed in claim 31, wherein said thin film resistor body comprise silicochromium or titanium-tungsten or the two.
33. half fusible jockey as claimed in claim 31, wherein said metal one deck comprise aluminum-copper alloy layer or nitrous acid titanium layer alloy-layer or the two.
34. half fusible jockey as claimed in claim 31, further be included in described first and described the 3rd dielectric layer in the step of contact is provided.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US48436903P | 2003-07-02 | 2003-07-02 | |
| US60/484,369 | 2003-07-02 | ||
| US10/777,337 | 2004-02-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1871704A CN1871704A (en) | 2006-11-29 |
| CN100456470C true CN100456470C (en) | 2009-01-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800187474A Expired - Fee Related CN100456470C (en) | 2003-07-02 | 2004-07-02 | Semi-fusible link system for a multi-layer integrated circuit and method of making same |
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| CN (1) | CN100456470C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04354178A (en) * | 1991-05-30 | 1992-12-08 | Tanaka Kikinzoku Kogyo Kk | Method of mounting semiconductor component on printed wiring board |
| WO1997033314A1 (en) * | 1996-03-05 | 1997-09-12 | Carnegie Mellon University | Method for fabricating mesa interconnect structures |
| US6246243B1 (en) * | 2000-01-21 | 2001-06-12 | Analog Devices, Inc. | Semi-fusible link system |
| US6265778B1 (en) * | 1999-07-27 | 2001-07-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a multi-level interconnection structure |
| US20030007081A1 (en) * | 2001-07-06 | 2003-01-09 | Oh-Bong Kwon | Image sensor with defective pixel address storage |
-
2004
- 2004-07-02 CN CNB2004800187474A patent/CN100456470C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04354178A (en) * | 1991-05-30 | 1992-12-08 | Tanaka Kikinzoku Kogyo Kk | Method of mounting semiconductor component on printed wiring board |
| WO1997033314A1 (en) * | 1996-03-05 | 1997-09-12 | Carnegie Mellon University | Method for fabricating mesa interconnect structures |
| US6265778B1 (en) * | 1999-07-27 | 2001-07-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a multi-level interconnection structure |
| US6246243B1 (en) * | 2000-01-21 | 2001-06-12 | Analog Devices, Inc. | Semi-fusible link system |
| US20030007081A1 (en) * | 2001-07-06 | 2003-01-09 | Oh-Bong Kwon | Image sensor with defective pixel address storage |
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| Publication number | Publication date |
|---|---|
| CN1871704A (en) | 2006-11-29 |
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