CN100448673C - Multi-mission spray printing system circuit and control circuit thereof - Google Patents
Multi-mission spray printing system circuit and control circuit thereof Download PDFInfo
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- CN100448673C CN100448673C CNB2005101329869A CN200510132986A CN100448673C CN 100448673 C CN100448673 C CN 100448673C CN B2005101329869 A CNB2005101329869 A CN B2005101329869A CN 200510132986 A CN200510132986 A CN 200510132986A CN 100448673 C CN100448673 C CN 100448673C
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Abstract
The invention discloses a multi-task spatter system circuit and control circuit to drive multiple sprayers, which is characterized by the following: generating signal according to the first clock signal and data; metering the signal through calculator; generating multiple time sequent metering signal; supplying these time sequent signals to N coders; generating N groups of active signal; moving the memory to move data according to signal and second clock signal (or the first clock signal and third clock signal); generating ith address signal (i is integral; N is not less than 2, which is also integral). Each heater controls the driving through one active signal in the address signal and each group of active signal, which drives corresponding sprayer.
Description
Technical field
The present invention relates to a kind of inkjet technology, particularly relate to a kind of multi-mission spray printing system circuit and control circuit thereof.
Background technology
Along with science and technology is showing improvement or progress day by day, inkjet technology develops towards the direction of the ink-jet chip of high-resolution, high print speed, high spray orifice number, to be applied among the more accurate special dimension.The size of ink droplet I more reaches high more print resolution, but under the same conditions, resolution ratio improves, and print speed also decreases.For promoting print speed and print resolution simultaneously, the number that increases spray orifice in single chip of ink-jet head is practicable solutions.
In the situation of thermal inkjet-printing, the electric current of control by resistor assembly is to drive each ink droplet generator.Thereby, resistor assembly is understood response current and is produced heat, and then add ink in the vaporized chamber of thermal proximity resistor assembly, so that ink seethes with excitement and produces vapour bubble, along with the expansion of vapour bubble, ink is pushed to spray orifice and formed little water droplet on the spray orifice top, wherein when vapour bubble expands gradually, little water droplet can break away from the surface tension of ink because of the pressure of vapour bubble, and sprays from spray orifice.
Traditional low spray orifice is counted ink jet-print head, whether work (on/off) state of its heating resistor (heater resistor) is connected by external connector (pad) and is determined, when the switch module such as field-effect transistor drives via grid, can make the electric current heating resistor of flowing through, thereby make heating resistor give birth to heat, and then ink is heated spray by spray orifice.But under this man-to-man type of drive, when the spray orifice number of needs increased, the number of external connector also increased thereupon relatively, thus, will increase the manufacturing cost of printhead, printing equipment and increase the difficulty of making assembling.
And then develop the type of drive that two-dimensional matrix, and it forms first dimension with many address wires, and forms second dimension with many power lines, thus the nozzle hole number that reaches control is the product of the number of the number of address wire and power line.Thereby an end of heating resistor is electrically connected to power line, and the other end is electrically connected to the drain electrode of field-effect transistor, and the source electrode of field-effect transistor is electrically connected to ground, and its grid is electrically connected to address wire; Wherein, only make the field-effect transistor conducting of its connection and the power line that is electrically connected with it when providing suitable voltage or electric current at heating resistor corresponding address line, this heating resistor just can enter duty, as United States Patent (USP) the 5th, 635, shown in No. 968.For the ink jet-print head of the type of drive that adopts two-dimensional matrix, 200 to 300 spray orifices generally can be provided, when must be, still can cause the number problem of external connector more than the spray orifice of this number.
Thereby, provide 400 or even the demand of more spray orifices for satisfying, further develop the type of drive that three-dimensional matrice, to increase considerably under the situation of spray orifice, the number that still can keep external connector is unlikely to significantly to increase.
Thereby, drive framework by known two-dimensional matrix, promptly constitute two-dimensional matrix by address wire and power line, increase the type of drive of selecting line to reach three-dimensional matrice again; Please refer to Fig. 1, in each heater circuit, the end of heating resistor R is electrically connected to power line, the other end is electrically connected to the drain electrode of first field effect transistor M 1, and the source electrode of first field effect transistor M 1 is electrically connected to ground, its grid is electrically connected to the source electrode of second field effect transistor M 2, and the drain and gate of second field effect transistor M 2 is electrically connected to address wire LA respectively and select line LQ; Thereby, when address wire LA has high potential simultaneously with selection line LQ, can make first field effect transistor M 1 present conducting state, simultaneously, power line LP also provides suitable voltage or electric current, and this moment, heating resistor R just can enter duty; Thereby the number of its spray orifice is for the number three's of the number of the number of selecting line, address wire and power line product, as United States Patent (USP) the 6th, 176, and No. 569 and the 6th, 431, shown in No. 677.
The another kind of similar framework of the type of drive of three-dimensional matrice that adopts please refer to Fig. 2, it constitutes the third dimension with active line LE, and the number of its spray orifice is the number three's of the number of number, address wire LA of active line LE and power line LP a product, as United States Patent (USP) the 6th, shown in 402, No. 279.Above-mentioned framework when 416 spray orifices are provided, can form the electric contact of 37 printheads in actual applications.
The type of drive of above-mentioned three-dimensional matrice still has its restriction, though just constitute the electric contact that the increase of the number of the selection line of the third dimension or active line can reduce printhead and main frame, has increased the complexity of heater circuit relatively.Just, except controlling the duty of heating resistor by two field-effect transistors, also need be in order to the field-effect transistor (as the field effect transistor M among the field effect transistor M among Fig. 13, M4, M5 and Fig. 2 6) that discharging function is provided, thereby guarantee when heating resistor does not need work, first field-effect transistor can be by noise or the coupled voltages of not expecting conducting, and then causes misoperation.
In order further to increase spray orifice again and to reduce electric contact, can also utilize the mode of sequence input, make it have 640 spray orifices, but only need 26 electric contacts that link to each other with main frame, the framework of associated driver circuitry please refer to United States Patent (USP) the 6th, 312, No. 079.Yet this kind data entry mode need use semiconductor subassembly faster to handle huge sequence input data, and required energy when also needing to be used high drive ink-jet being provided, therefore still have problems such as high power consumption, operation precision, cost costliness.
The type of drive of another three-dimensional matrice then is to adopt power line LP, address wire LA, address to activate the driving that line LD constitutes three-dimensional matrice; Please refer to Fig. 3, in each heater circuit, heating resistor R is configured between the drain electrode of power line LP and power transistor M7, and line is electrically connected to power transistor M7 by logic module grid is activated in address wire and address; When address wire LA and address are activated line LD and are logic low signal " 0 " simultaneously, produce logic high signal " 1 " after the computing by logic module, so that power transistor M7 presents conducting state, simultaneously, power line LP also provides suitable voltage or electric current, and this moment, heating resistor R just can enter duty.Thereby the heating resistor R that utilizes activation simultaneously to be connected to same power line LP accelerates print speed.Yet its printhead control circuit all is to be made of decoder, and graph data must earlier just can arrive corresponding spray orifice through decoder, thereby needs more control signal input.
Promote print speed and print resolution simultaneously though proposed the type of drive of multiple three-dimensional matrice in the prior art, and increasing considerably under the situation of spray orifice, the number that still can keep external connector is unlikely to increase considerably.Yet, the type of drive of above-mentioned three-dimensional matrice still has its restriction, for example: the contact of circuit structure complexity, power consumption height, cost costliness, increase control signal etc., and along with the progress of science and technology, prior art certainly will be able to not satisfy the demands at following nozzle hole number that can provide of acceptable electric contact number.Therefore, in order to promote print speed and print resolution simultaneously, how in single chip of ink-jet head, to increase the number of spray orifice, and the number that still can keep external connector is unlikely to significantly to increase, simultaneously do not increase power consumption, circuit complexity and area, it is still the direction that present correlative study personnel endeavour to study.
Summary of the invention
Based on above problem, main purpose of the present invention is to provide a kind of multi-mission spray printing system circuit and control circuit thereof, to solve one or more problem that exists in the prior art.
Therefore, for achieving the above object, the control circuit of multi-mission spray printing system disclosed in this invention comprises signal generation unit, offset buffer, a counter and N decoder, and wherein N is greater than or equal to 2 positive integer.
Here, the signal generation unit is electrically connected to the offset buffer sum counter, and counter is electrically connected to each decoder, and offset buffer and each decoder system be electrically connected to each heater circuit, so that corresponding heater circuit is driven control.Wherein, the signal generation unit is used for producing enable signal according to first clock signal and data; Offset buffer is used for according to enable signal and second clock signal and shifted data, thereby produces i address signal, and wherein i is a positive integer; Counter is used for counting according to enable signal, thereby produces a plurality of sequential count signals; And each decoder is used for receiving unit sequential count signal, and with its decoding to produce one group of activation signal, wherein N is greater than or equal to 2 positive integer; Like this, can reach the driving control of these heater circuits by any combination of address signal and each group activation signal, in other words, each heater circuit drives by the control of address signal and each one of them activation signal of group activation signal.
In addition, the signal generation unit is electrically connected to offset buffer, and counter is electrically connected to each decoder, and offset buffer and each decoder be electrically connected to each heater circuit, so that corresponding heater circuit is driven control.Wherein, the signal generation unit is used for producing enable signal according to first clock signal and data; Offset buffer is used for according to first clock signal and the 3rd clock signal and shifted data produces i address signal thus, and wherein i is a positive integer; Counter is used for counting according to enable signal, produces a plurality of sequential count signals thus; And each decoder is used for receiving unit sequential count signal, and with its decoding to produce one group of activation signal, wherein N is greater than or equal to 2 positive integer; Like this, can reach the driving control of these heater circuits by any combination of address signal and each group activation signal, in other words, each heater circuit drives by the control of address signal and each one of them activation signal of group activation signal.Here, the 3rd clock signal can be half of first clock signal.
Moreover the number of these heater circuits is the number of address signal and the product of the number of each group activation signal.
Wherein, the signal generation unit mainly is made of a plurality of triggers (flip-flop) and a plurality of logic module.Offset buffer mainly is made of a plurality of triggers.Counter mainly is made of a plurality of triggers and a plurality of logic module.And decoder can be n to 2
nDecoder is to decipher n sequential count signal to produce 2
nIndividual activation signal, wherein n is a positive integer.
And, can utilize CMOS field-effect transistor (CMOS) to constitute employed trigger here, with low-power consumption, the power consumption of whole ink-jet chip on control circuit can be reduced to minimum comparatively speaking.
The present invention also discloses a kind of multi-mission spray printing system circuit, in order to drive a plurality of spray orifices, includes control circuit and ink spray module.Wherein, control circuit includes signal generation unit, offset buffer, a counter and N decoder, and N is greater than or equal to 2 positive integer.And ink spray module includes a plurality of heater circuits, corresponds respectively to a spray orifice, and each heater circuit includes and gate logic switch, transistor switch and resistor assembly.
Here, the signal generation unit is electrically connected to the offset buffer sum counter, and counter is electrically connected to each decoder, and offset buffer and each decoder be electrically connected to each heater circuit, so that corresponding heater circuit is driven control; In other words, in each heater circuit, be electrically connected to offset buffer and decoder with the gate logic switch, the grid of transistor switch then is electrically connected to corresponding and the output gate logic switch, its drain electrode is electrically connected to an end of resistor assembly, and applies suitable voltage or electric current at the other end of resistor assembly, therefore can be according to the control of control circuit with the gate logic switch, and make the transistor switch conducting, and then drive resistor assembly to produce heat.
Wherein, the signal generation unit is used for producing enable signal according to first clock signal and data; Offset buffer is used for according to enable signal and second clock signal and shifted data, and to produce i address signal, wherein i is a positive integer; Counter is used for counting according to enable signal, to produce a plurality of sequential count signals; Each decoder is used for receiving unit sequential count signal, and it is deciphered to produce one group of activation signal, and wherein N is greater than or equal to 2 positive integer; Each is used for address signal and each one of them activation signal of group activation signal are carried out logical operation with the gate logic switch, drives signal to produce; Transistor switch is used for the conducting according to driving signal; And resistor assembly is used for when the transistor switch conducting producing heat, to drive corresponding spray orifice.Like this, can reach the driving control of these heater circuits by any combination of address signal and each group activation signal, in other words, each heater circuit drives by the control of address signal and each one of them activation signal of group activation signal.
In addition, the signal generation unit is electrically connected to offset buffer, and counter is electrically connected to each decoder, and offset buffer and each decoder be electrically connected to each heater circuit, so that corresponding heater circuit is driven control.Wherein, the signal generation unit is used for producing enable signal according to first clock signal and data; Offset buffer is used for according to first clock signal and the 3rd clock signal and shifted data, and to produce i address signal, wherein i is a positive integer; Counter is used for counting according to enable signal, to produce a plurality of sequential count signals; Each decoder is used for receiving unit sequential count signal, and it is deciphered to produce one group of activation signal, and wherein N is greater than or equal to 2 positive integer; Each is used for address signal and each one of them activation signal of group activation signal are carried out logical operation with the gate logic switch, drives signal to produce; Transistor switch is used for the conducting according to driving signal; And resistor assembly is used for when the transistor switch conducting producing heat, to drive corresponding spray orifice.Like this, can reach the driving control of these heater circuits by any combination of address signal and each group activation signal, in other words, each heater circuit drives by the control of address signal and each one of them activation signal of group activation signal.
In addition, the number of these heater circuits is the number of address signal and the product of the number of each group activation signal.In other words, the number of these spray orifices is the number of address signal and the product of the number of each group activation signal.
Wherein, the signal generation unit mainly is made of a plurality of triggers and a plurality of logic module.Offset buffer mainly is made of a plurality of triggers.Counter mainly is made of a plurality of triggers and a plurality of logic module.And decoder can be n to 2
nDecoder is to decipher n sequential count signal to produce 2
nIndividual activation signal, wherein n is a positive integer.
Here, transistor switch can adopt the field-effect transistor with big channel breadth length ratio (channel width/length), reduces the dead resistance (parasitic resistance) of series connection, so with power concentration in thermal resistance.And, at ink jet-print head than droplet since its to spray the required power of single drop lower, therefore under the situation that the voltage that main frame provided does not increase, can improve resistor assembly resistance so that the power that resistor assembly produced descend thereupon.
In addition, this transistor switch also can adopt asymmetric mos field effect transistor, to realize low driving transistors assembly resistance and small transistor area.And the drain electrode end of this asymmetric mos field effect transistor can be dual diffusion (double diffused drains; DDD), and its source terminal is low pressure N+ type diffusion structure, to reduce dead resistance.
And, can utilize complementary metal oxide semiconductor field effect transistor (CMOS) to constitute employed trigger here, with low-power consumption, the power consumption of whole ink-jet chip on control circuit can be reduced to minimum comparatively speaking.
About the feature of the present invention and the specific embodiment, be elaborated below with reference to accompanying drawings.
Description of drawings
Figure 1 shows that the schematic diagram of the heater circuit of prior art;
Figure 2 shows that the schematic diagram of the heater circuit of prior art;
Figure 3 shows that the schematic diagram of the heater circuit of prior art;
Figure 4 shows that schematic diagram according to the multi-mission spray printing system circuit of first embodiment of the invention;
Fig. 5 A is depicted as the schematic diagram according to first embodiment of signal generation unit in the multi-mission spray printing system circuit of the present invention;
Fig. 5 B is the sequential chart of the signal generation unit among Fig. 5 A;
Figure 6 shows that schematic diagram according to second embodiment of signal generation unit in the multi-mission spray printing system circuit of the present invention;
Fig. 7 A is depicted as the schematic diagram according to the 3rd embodiment of signal generation unit in the multi-mission spray printing system circuit of the present invention;
Fig. 7 B is depicted as the schematic diagram according to the 4th embodiment of signal generation unit in the multi-mission spray printing system circuit of the present invention;
Fig. 8 figure is depicted as the schematic diagram according to first embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 9 shows that schematic diagram according to second embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 10 A is depicted as the schematic diagram according to first embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 10 B is the schematic diagram according to second embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 10 C is depicted as the schematic diagram according to the 3rd embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 10 D is depicted as the schematic diagram according to the 4th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 11 A is depicted as the schematic diagram according to the 5th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 11 B is depicted as the schematic diagram according to the 6th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 11 C is depicted as the schematic diagram according to the 7th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 11 D is depicted as the schematic diagram according to the 8th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 12 shows that schematic diagram according to first embodiment of first decoder in the multi-mission spray printing system circuit of the present invention;
Figure 13 shows that schematic diagram according to first embodiment of second decoder in the multi-mission spray printing system circuit of the present invention;
Figure 14 shows that schematic diagram according to first embodiment of ink spray module in the multi-mission spray printing system circuit of the present invention;
Figure 15 shows that the schematic diagram of an embodiment of heater circuit in the ink spray module shown in Figure 14;
Figure 16 shows that schematic diagram according to the multi-mission spray printing system circuit of second embodiment of the invention;
Figure 17 shows that schematic diagram according to the 3rd embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 18 shows that schematic diagram according to the 9th embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Figure 19 shows that schematic diagram according to second embodiment of first decoder in the multi-mission spray printing system circuit of the present invention;
Figure 20 shows that schematic diagram according to second embodiment of second decoder in the multi-mission spray printing system circuit of the present invention;
Figure 21 A and 21B are depicted as according to the measured sequential chart of each signal in the multi-mission spray printing system circuit of second embodiment of the invention;
Shown in Figure 22 is schematic diagram according to second embodiment of ink spray module in the multi-mission spray printing system circuit of the present invention;
Shown in Figure 23 is the schematic diagram of an embodiment of heater circuit in the ink spray module among Figure 22;
Shown in Figure 24 is schematic diagram according to the multi-mission spray printing system circuit of third embodiment of the invention;
Figure 25 A and 25B are depicted as the schematic diagram according to the 4th embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 26 A and 26B are depicted as the schematic diagram according to the 5th embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 27 A is depicted as the schematic diagram according to the multi-mission spray printing system circuit of fourth embodiment of the invention;
Figure 27 B is depicted as the schematic diagram according to the multi-mission spray printing system circuit of fifth embodiment of the invention;
Shown in Figure 28 is schematic diagram according to the tenth embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Shown in Figure 29 is the schematic diagram of an embodiment of decoder in the multi-mission spray printing system circuit shown in Figure 27 A or Figure 27 B;
Shown in Figure 30 is the schematic diagram of forming heater circuit one embodiment of ink spray module in the multi-mission spray printing system circuit shown in Figure 27 A or Figure 27 B;
Figure 31 A is depicted as the schematic diagram according to the multi-mission spray printing system circuit of sixth embodiment of the invention;
Figure 31 B is depicted as the schematic diagram according to the multi-mission spray printing system circuit of seventh embodiment of the invention;
Figure 32 A is depicted as the schematic diagram according to the 6th embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 32 B is depicted as the schematic diagram according to the 7th embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Figure 32 C is depicted as the schematic diagram according to the 8th embodiment of offset buffer in the multi-mission spray printing system circuit of the present invention;
Shown in Figure 33 is schematic diagram according to the 11 embodiment of counter in the multi-mission spray printing system circuit of the present invention;
Shown in Figure 34 is schematic diagram according to an embodiment of the 3rd decoder in the multi-mission spray printing system circuit of the present invention;
Shown in Figure 35 is schematic diagram according to the 3rd embodiment of ink spray module in the multi-mission spray printing system circuit of the present invention; And
Shown in Figure 36 is the schematic diagram of an embodiment of heater circuit in the ink spray module shown in Figure 35.
Wherein, Reference numeral:
100........................... control circuit
110........................... signal generation unit
112........................... first D flip-flop
114........................... second D flip-flop
115........................... the 3rd D flip-flop
116........................... or gate logic switch
118........................... with the gate logic switch
119........................... reverser
120........................... offset buffer
122........................... the 4th D flip-flop
124........................... the 5th D flip-flop
130........................... counter
132........................... with the gate logic switch
134........................... the 6th D flip-flop
136........................... reverser
140........................... decoding module
141........................... first decoder
142........................... second decoder
143........................... the 3rd decoder
14N........................... N decoder
151........................... reverser
152........................... reverser
153........................... reverser
15j........................... reverser
161........................... with the gate logic switch
162........................... with the gate logic switch
163........................... with the gate logic switch
164........................... with the gate logic switch
165........................... with the gate logic switch
166........................... with the gate logic switch
167........................... with the gate logic switch
168........................... with the gate logic switch
162
j... ... ... ... .. and gate logic switch
171........................... reverser
172........................... reverser
173........................... reverser
174........................... reverser
17k........................... reverser
181........................... with the gate logic switch
182........................... with the gate logic switch
183........................... with the gate logic switch
184........................... with the gate logic switch
185........................... with the gate logic switch
186........................... with the gate logic switch
187........................... with the gate logic switch
188........................... with the gate logic switch
182
k... ... ... ... .. and gate logic switch
200........................... ink spray module
The #21........................... first displacement electronic circuit
The #22........................... second displacement electronic circuit
#23........................... the 3rd displacement electronic circuit
#24........................... the 4th displacement electronic circuit
#215.......................... the 15 displacement electronic circuit
#216.......................... the 16 displacement electronic circuit
#2 (i-1) ... ... ... ... the .. i-1 electronic circuit that is shifted
The #2i........................... i electronic circuit that is shifted
The #31........................... first counting electronic circuit
The #32........................... second counting electronic circuit
#33........................... the 3rd counting electronic circuit
#34........................... the 4th counting electronic circuit
#35........................... the 5th counting electronic circuit
#3 (n-1) ... ... ... ... .. n-1 counts electronic circuit
#3n........................... n counts electronic circuit
#3 (n+1) ... ... ... ... .. n+1 counts electronic circuit
#3 (n+ ... + k+j) ... ... ... n+ ... + k+j counts electronic circuit
A1, A2, A3-A (i-1), Ai......... address signal
B1-B2
j... ... ... ... first activation signal
C1-C2
k... ... ... ... second activation signal
CK1........................... first clock signal
CK2........................... second clock signal
D............................. input
Data.......................... data
D1-D4......................... the 3rd activation signal
E1-E2
n... ... ... ... the N activation signal
EN............................ enable signal
H
1,1,1, H
2,1,1-H
I, 1,1... ... .... heater circuit
H
1,2,1,
... .... heater circuit
, H
1,1,2... ... ... heater circuit
H
16,1,1, H
16,2,1-H
1,8,1... ... heater circuit
H
2,8,1-H
16,8,1... ... ... ... the .. heater circuit
H
2,1,2-H
16,1,2-H
1,8,2... ... the .. heater circuit
H
2,8,2-H
16,8,2-H
1,8,4... ... the .. heater circuit
H
2,8,4-H
16,8,4... ... ... ... the .. heater circuit
H
1,1,1,1-H
4,1,4,1-H
1,8,1,4-H
4,8,4,4... ... the .. heater circuit
LA....................................... address wire
LD....................................... line is activated in the address
LE....................................... active line
LP....................................... power line
LQ....................................... select line
M1....................................... first field-effect transistor
M2....................................... second field-effect transistor
M3....................................... field-effect transistor
M4....................................... field-effect transistor
M5....................................... field-effect transistor
M6....................................... field-effect transistor
M7....................................... power transistor
M
1,1,1-M
16,1,1-M
1,8,4-M
16,8,4... the .. transistor switch
M
1,1,1,1-M
4,1,4,1-M
1,8,1,4-M
4,8,4,4... ... transistor switch
P........................................ signal
Q........................................ output
Q ' ... ... ... ... ... ... the .. inverse output terminal
R............................. heating resistor
RB1-RBj....................... sequential count signal
RC1-RCk....................... sequential count signal
RD1........................... sequential count signal
RD2........................... sequential count signal
RX............................ sequential count signal
First group of sequential count signal of j * RXs........................
Second group of sequential count signal of k * RXs........................
N * RXs........................ N group sequential count signal
R
1,1,1-R
16,1,1-R
1,8,4-R
16,8,4... .... resistor assembly
R
1,1,1,1-R
4,1,4,1-R
1,8,1,4-R
4,8,4,4... ... resistor assembly
Z
1,1,1-Z
16,1,1-Z
1,8,4-Z
16,8,4... .... with the gate logic switch
Z
1,1,1,1-Z
4,1,4,1-Z
1,8,1,4-Z
4,8,4,4... .... with the gate logic switch
The specific embodiment
Below enumerate specific embodiment describing content of the present invention in detail, and with accompanying drawing as aid illustration.The symbol system of mentioning in the explanation is with reference to the symbol in the accompanying drawing.
With reference to Fig. 4, it shows the multi-mission spray printing system circuit according to the embodiment of the invention, and it includes control circuit 100 and ink spray module 200.Here, control circuit 100 includes signal generation unit 110, offset buffer 120, counter (counter) 130, first decoder (decoder) 141 and second decoder 142.
Here, signal generation unit 110 is electrically connected to offset buffer 120 sum counters 130, counter 130 is electrically connected to first decoder 141 and second decoder 142, and offset buffer 120, first decoder 141 and second decoder 142 are electrically connected to ink spray module 200, so that ink spray module 200 is printed control.
Wherein, signal generation unit 110 produces enable signal EN according to the first clock signal C K1 and data Data.
Offset buffer 120 produces a group address signal A1-Ai according to this according to this enable signal EN and second clock signal CK2 shifted data Data.
And then by address signal A1-Ai, the first activation signal B1-B2
jWith the second activation signal C1-C2
kControl the running of ink spray module 200, that is to say, by address signal A1-Ai, the first activation signal B1-B2
jWith the second activation signal C1-C2
kAny combination can reach i * 2
j* 2
kThe driving control of individual heater circuit, and then can control i * 2
j* 2
kThe running of individual spray orifice.Wherein, i, j and k are positive integer.
Wherein, signal generation unit 110 mainly is made of trigger and logic module.
Please refer to Fig. 5 A, it shows the circuit diagram of signal generation unit one embodiment; This signal generation unit 110 include first D flip-flop 112, second D flip-flop 114 or gate logic switch 116 and with gate logic switch 118.
Here, first D flip- flop 112 and 114 parallel connections of second D flip-flop, its output Q with or gate logic switch 116 and connect successively with gate logic switch 118; In other words, the output Q of D flip-flop (i.e. first D flip-flop 112 and second D flip-flop 114) is electrically connected to or the input of gate logic switch 116, or the output of gate logic switch 116 then is electrically connected to the input with gate logic switch 118.And the inverse output terminal Q ' of each D flip-flop (i.e. first D flip-flop 112 and second D flip-flop 114) feeds back to input D separately.
Described enable signal EN is input to the trigger end of first D flip-flop 112 and second D flip-flop 114; Wherein, first D flip-flop 112 triggers for trailing edge, and second D flip-flop 114 triggers for rising edge.Data Data then is input to and gate logic switch 118.
Here, the first clock signal C K1 trigger through the trailing edge of first D flip-flop 112 and the rising edge triggering of second D flip-flop 114 after, via or gate logic switch 116 make to produce after the logical operation signal P, this signal P again with data Data through and gate logic switch 118 do after the logical operation and produce enable signal EN, its sequential chart is shown in Fig. 5 B.With reference to Fig. 5 B,, when the trailing edge of the first clock signal C K1 takes place, can make the output Q transition of first D flip-flop 112 here, the output Q of second D flip-flop 114 then remains unchanged; Otherwise, when the rising edge of the first clock signal C K1 takes place, then make the output Q transition of second D flip-flop 114, and the output Q of first D flip-flop 112 remains unchanged.
In addition, each D flip-flop (i.e. first D flip-flop 112 and second D flip-flop 114) is input to the signal of its input D, also can feed back to input D via reverser 119 by its output Q, as shown in Figure 6.That is to say, the output Q of D flip-flop (i.e. first D flip-flop 112 and second D flip-flop 114) is electrically connected to or the input of gate logic switch 116, or the output of gate logic switch 116 then is electrically connected to the input with gate logic switch 118, and the output Q of each D flip-flop (i.e. first D flip-flop 112 and second D flip-flop 114) feeds back to separately input D via reverser 119 again.
In addition, also can come providing of control data Data by initialization the 3rd D flip-flop 115, that is to say, data Data is input to the input D of initialization the 3rd D flip-flop 115, output Q by initialization the 3rd D flip-flop 115 is connected to or the input of gate logic switch 116 again, shown in Fig. 7 A and Fig. 7 B.
Here, offset buffer 120 mainly is made of trigger.Please refer to Fig. 8, it shows the circuit diagram of offset buffer one embodiment; This offset buffer 120 includes i displacement electronic circuit (for convenience of description, below be referred to as first displacement electronic circuit to the i displacement electronic circuit #21-#2i respectively), and the electronic circuit that respectively is shifted includes two D flip-flops (being referred to as the 4th D flip-flop 122 and the 5th D flip-flop 124 for convenience of description, respectively).Here, the 4th D flip-flop 122 and the 5th D flip-flop 124 all adopt rising edge to trigger, and second clock signal CK2 is input to the trigger end of each the 4th D flip-flop 122, and enable signal EN then is input to the trigger end of each the 5th D flip-flop 124.Wherein, in the first displacement electronic circuit #21, the input D of the 4th D flip-flop 122 receives data Data, and input D and next stage that its output Q is electrically connected to the 5th D flip-flop 124 are shifted electronic circuit (here, the input D of the 4th D flip-flop 122 i.e. second displacement electronic circuit #22), therefore the 5th D flip-flop 124 is again according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal A1; And, in the second displacement electronic circuit #22, the input D of the 4th D flip-flop 122 is electrically connected to previous stage displacement electronic circuit (here, the output Q of the 4th D flip-flop 122 i.e. first displacement electronic circuit #21), and input D and next stage that its output Q is electrically connected to the 5th D flip-flop 124 are shifted electronic circuit (here, the input D of the 4th D flip-flop 122 i.e. the 3rd displacement electronic circuit #23), therefore the 5th D flip-flop 124 is again according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal A2; By that analogy, until i-1 displacement electronic circuit #2 (i-1), and the electronic circuit of one-level displacement in the end (here, i.e. i displacement electronic circuit #2i) in, the input D of its 4th D flip-flop 122 is electrically connected to previous stage displacement electronic circuit (here, the output Q of the 4th D flip-flop 122 i.e. i-1 displacement electronic circuit #2 (i-1)), and the output Q of the 4th D flip-flop 122 only is electrically connected to the input D of the 5th D flip-flop 124, and the 5th D flip-flop 124 is again according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal Ai.
In addition, in offset buffer 120, displacement electronic circuits at different levels (i.e. first displacement electronic circuit to the i displacement electronic circuit #21-#2i), its the 4th D flip-flop 122 and the 5th D flip-flop 124 can all be that trailing edge triggers, that is to say, second clock signal CK2 and enable signal EN just import the trigger end of the 4th D flip-flop 122 and the trigger end of the 5th D flip-flop 124 respectively after oppositely, as shown in Figure 9.
Here, counter 130 mainly is made of trigger and logic module.Please refer to Figure 10 A, 10B, 10C and 10D, it shows the circuit diagram of counter one embodiment; This counter 130 includes k+j counting electronic circuit (for convenience of description, below be referred to as first counting electronic circuit to the k+j counting electronic circuit #31-#3k, #3 (k+1)-#3 (k+j) respectively), wherein second to the k+j counting electronic circuit #32-#3 (k+j) include with gate logic switch 132 and D flip-flop (for convenience of description, below be referred to as the 6th D flip-flop 134 respectively), the first counting electronic circuit #31 includes D flip-flop (i.e. the 6th D flip-flop 134).And, each counts electronic circuit (i.e. first counting electronic circuit to the k+j counting electronic circuit #31-#3k, #3 (k+1), #3 (k+2)-#3 (k+j-1), #3 (k+j)), and the output Q of its 6th D flip-flop 134 can distinguish output timing count signal (preface count signal RC1, RC2-RCk, RB1, RB2-RB (j-1), RBj in real time).
Wherein, counter 130 can have odd number counting electronic circuit (shown in Figure 10 A and 10C), or has even number counting electronic circuit (shown in Figure 10 B and 10D).And no matter offset buffer 120 has odd number counting electronic circuit or even number counting electronic circuit, its k all can be odd number or even number.
Here, each the 6th D flip-flop 134 is trailing edge and triggers, and its inverse output terminal Q ' can feed back to input D separately.And enable signal EN is input to the trigger end of the first counting electronic circuit # 31, the second counting electronic circuit #32 (promptly the 3rd counts electronic circuit with gate logic switch 132 and next odd level counting electronic circuit, not shown in the accompanying drawing) the trigger end of the 6th D flip-flop 134, and the 6th D flip-flop 134 of the first counting electronic circuit # 31 is understood according to the feedback signal of enable signal EN and its inverse output terminal Q ' and from its output Q output timing count signal RC1, and this sequential count signal RC1 is input to the second counting electronic circuit # 32 with gate logic switch 132, with carry out logical operation (that is, the first counting electronic circuit output Q with output gate logic switch 132 and Qi Di six D flip-flops 134 #31 can be electrically connected to the second counting electronic circuit # 32 with input gate logic switch 132).
And in the second counting electronic circuit # 32, with gate logic switch 132 sequential count signal RC1 and the enable signal EN that imports done logical operation, and operation result is outputed to trigger end and the 3rd counting electronic circuit and input gate logic switch 132 of the 6th D flip-flop 134, thereby the 6th D flip-flop 134 of this second counting electronic circuit # 32 can be according to itself and the output of gate logic switch 132 and the feedback signal of its inverse output terminal Q ', and from its output Q output timing count signal RC2, and the output of this sequential count signal RC2 and itself and gate logic switch 132 is input to the 3rd that count electronic circuit and gate logic switch 132, with with enable signal EN carry out logical operation (that is, the second counting electronic circuit output Q with output gate logic switch 132 and Qi Di six D flip-flops 134 #32 can be electrically connected to the 3rd counting electronic circuit with input gate logic switch 132).
Count electronic circuit at the 4th counting electronic circuit (not shown in the accompanying drawing) to k+j-1, in even level counting electronic circuit, the input of itself and gate logic switch 132 is electrically connected to the output Q of previous stage counting the 6th D flip-flop 134 with output gate logic switch 132 and previous stage counting electronic circuit electronic circuit, be that itself and gate logic switch 132 receives the output (being the sequential count signal that previous stage counting electronic circuit is exported) with output gate logic switch 132 and the 6th D flip-flop 134 electronic circuit of previous stage counting to carry out logical operation, and be electrically connected to the trigger end of its 6th D flip-flop 134 with the output of gate logic switch 132, and with the output Q of the output of gate logic switch 132 and the 6th D flip-flop 134 be electrically connected to the next stage counting electronic circuit with input gate logic switch 132; And, in odd level counting electronic circuit, itself and gate logic switch 132 receive the previous stage counting electronic circuit with output gate logic switch 132 and the 6th D flip-flop 134 output (being the sequential count signal that previous stage counting electronic circuit is exported) and last odd level counting electronic circuit with output gate logic switch 132, to carry out logical operation, and be electrically connected to the trigger end of its 6th D flip-flop 134 with the output of gate logic switch 132, and with the output Q of the output of gate logic switch 132 and the 6th D flip-flop 134 be electrically connected to the next stage counting electronic circuit with input gate logic switch 132; By that analogy, until k+j-1 counting electronic circuit #3 (k+j-1).
In addition, in the 3rd counting electronic circuit (not shown in the accompanying drawing), except itself and gate logic switch 132 receives enable signal EN, the previous stage counting is electronic circuit counts the output (being the sequential count signal that previous stage counting electronic circuit is exported) of the 6th D flip-flop 134 of electronic circuit to carry out logical operation (promptly with output gate logic switch 132 and previous stage, the input of itself and gate logic switch 132 is electrically connected to the output (not shown in the accompanying drawing) of signal generation unit, the output of previous stage counting the 6th D flip-flop 134 with output gate logic switch 132 and previous stage counting electronic circuit electronic circuit) outside, remaining structure is identical with the structure and the operation principles of above-mentioned odd level counting electronic circuit with operation principles, so repeat no more.
And at afterbody counting electronic circuit (here, promptly k+j counts electronic circuit #3 (k+j)), when offset buffer 120 has odd number counting electronic circuit (shown in Figure 10 A and 10C), this k+j counting electronic circuit #3 (k+j) receives previous stage counting electronic circuit (here with gate logic switch 132, the output of i.e. k+j-1 counting electronic circuit #3 (k+j-1)) and output gate logic switch 132 and the 6th D flip-flop 134 (here, be sequential count signal RB (j-1)) and last odd level counting electronic circuit is (here, promptly k+j-2 counts electronic circuit, not shown in the accompanying drawing) with the output of gate logic switch 132, carrying out logical operation, and should be electrically connected to the trigger end of its 6th D flip-flop 134 with the output of gate logic switch 132; Otherwise, when offset buffer 120 has even number counting electronic circuit (shown in Figure 10 B and 10D), this k+j counting electronic circuit #3 (k+j) receives previous stage counting electronic circuit (here with gate logic switch 132, the output of i.e. k+j-1 counting electronic circuit #3 (k+j-1)) and output gate logic switch 132 and the 6th D flip-flop 134 (here, be sequential count signal RB (j-1)) carrying out logical operation, and should be electrically connected to the trigger end of its 6th D flip-flop 134 with the output of gate logic switch 132.
In addition, the 6th D flip-flop 134 is input to the signal of its input D, also can feed back to input D via reverser 136 by its output Q, shown in figure 11A, 11B, 11C and 11D.That is to say, the output Q of the 6th D flip-flop 134 be electrically connected to next stage counting electronic circuit with input gate logic switch 132 (except the afterbody counting electronic circuit), and the output Q of the 6th D flip-flop 134 feeds back to input D separately again via reverser 136.
Here, first decoder 141 is that j is to 2
jDecoder, it includes j reverser 151,152,153-15j and 2
jIndividual and gate logic switch 161,162,163-162
j, and by these reversers 151,152,153-15j and with gate logic switch 161,162,163-162
jCombination, can produce 2 according to j sequential count signal RB1-RBj
jThe individual first activation signal B1-B2
j, as shown in figure 12.And second decoder 142 is that k is to 2
kDecoder, it includes k reverser 171,172,173-17k and 2
kIndividual and gate logic switch 181,182,183-182
k, and by these reversers 171,172,173-17k and with gate logic switch 181,182,183-182
kCombination, can produce 2 according to k sequential count signal RC1-RCk
kThe individual second activation signal C1-C2
k, as shown in figure 13.Because j is to 2
jDecoder and k are to 2
kThe structure and the operation principles of decoder are known by those skilled in the art, so do not repeat them here.
At last, again with address signal A1-Ai, the first activation signal B1-B2
jWith the second activation signal C1-C2
kBe input to ink spray module 200,, that is to say, by address signal A1-Ai, the first activation signal B1-B2 to control its running
jWith the second activation signal C1-C2
kAny combination can reach i * 2
j* 2
kIndividual heater circuit H
1,1,1, H
2,1,1-H
I, 1,1, H
1,2,1,
H
1,1,2,
Driving control, and then can control i * 2
j* 2
kThe running of individual spray orifice, as shown in figure 14.Wherein, i, j and k are positive integer.
With reference to Figure 15, it shows the circuit diagram of heater circuit one embodiment; This heater circuit
Include and the gate logic switch
Transistor switch
And resistor assembly
Here, with the gate logic switch
Input be electrically connected to offset buffer 120, first decoder 141 and second decoder 142, with receive address signal Ai from offset buffer 120, from the first activation signal B2 of first decoder 141
jWith the second activation signal C2 from second decoder 142
kWith the gate logic switch
Input be electrically connected to transistor switch
Grid, in other words, with the gate logic switch
According to address signal Ai, the first activation signal B2
jWith the second activation signal C2
kCarry out logical operation, with output drive signal
Control transistor switch
Conducting whether; And, transistor switch
Source ground, its drain electrode is electrically connected to resistor assembly
An end, and at resistor assembly
The other end apply suitable voltage or electric current.
Wherein, as address signal Ai, the first activation signal B2
jWith the second activation signal C2
kWhen being logic high signal " 1 " simultaneously, process and gate logic switch
Computing after can produce the driving signal of logic high signal " 1 "
, so that transistor switch
Present conducting state, this is resistor assembly
Just can enter duty and produce heat, and then drive corresponding nozzle emission ink and print.Like this, can utilize less control signal to realize increasing considerably the number of spray orifice, and the number that still can keep external connector is unlikely to increase considerably.And, can be according to directly extracting the corresponding spray orifice of data segment in the data of required printing.
For instance, when wanting control to drive 512 spray orifices, can make i=16, j=3 and k=2, as shown in figure 16.With reference to Figure 16, here, counter 130 is counted according to enable signal EN, to produce 5 sequential count signal RB1-RB3, RC1, RC2, and be divided into two parts, a part of sequential count signal RB1-RB3 is input in first decoder 141 and deciphers, to produce 2
3(=8) individual first activation signal B1-B8; And another part sequential count signal RC1, RC2 be input to and decipher in second decoder 142, to produce 2
2(=4) individual second activation signal C1-C4.Offset buffer 120 then produces 16 address signal A1-A16 according to this according to this enable signal EN and second clock signal CK2 displacement data Data.And then, control the running of ink spray module 200 by these address signals A1-A16, the first activation signal B1-B8 and the second activation signal C1-C4, that is to say that any combination by address signal A1-A16, the first activation signal B1-B8 and the second activation signal C1-C4 can reach 16 * 2
3* 2
2(driving of=16 * 8 * 4=512) individual heater circuits is controlled, and then can control the running of 512 spray orifices.
Wherein, signal generation unit 110 can adopt the structure shown in Fig. 5 A, and its operation principles is same as described above, so do not repeat them here.
And the structure of offset buffer 120 is similar to structure shown in Figure 8, i=16 wherein, as shown in figure 17.With reference to Figure 17, this offset buffer 120 includes 16 displacement electronic circuits (for convenience of description, below be referred to as the first displacement electronic circuit to the, 16 displacement electronic circuit #21, #22, #23-#215, #216 respectively), and the electronic circuit that respectively is shifted includes two D flip-flops (being referred to as the 4th D flip-flop 122 and the 5th D flip-flop 124 for convenience of description, respectively).Here, the 4th D flip-flop 122 and the 5th D flip-flop 124 all adopt rising edge to trigger, and second clock signal CK2 is input to the trigger end of the 4th D flip-flop 122 of the electronic circuit that respectively is shifted, and enable signal EN then is input to the trigger end of the 5th D flip-flop 124 of the electronic circuit that respectively is shifted.Wherein, in the first displacement electronic circuit #21, the input D of the 4th D flip-flop 122 receives data Data, and its output Q is electrically connected to the input D of the 4th D flip-flop 122 of the input D of the 5th D flip-flop 124 and the second displacement electronic circuit #22, and therefore the 5th D flip-flop 124 is again according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal A1; And, in the second displacement electronic circuit #22, the input D of the 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of the first displacement electronic circuit #21, and its output Q is electrically connected to the input D of the 4th D flip-flop 122 of the input D of the 5th D flip-flop 124 and the 3rd displacement electronic circuit #23, and therefore the 5th D flip-flop 124 is again according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal A2; In like manner, by that analogy, and respectively by the 4th displacement electronic circuit to the 15 displacement electronic circuit OPADD signal A4-A15, and in the 16 displacement electronic circuit #216, the input D of its 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of the 15 displacement electronic circuit #215, and the output Q of the 4th D flip-flop 122 is electrically connected to the input D of the 5th D flip-flop 124, by its 5th D flip-flop 124 according to the output of the 4th D flip-flop 122 and enable signal EN and from output Q OPADD signal A16.
And the structure of counter 130 is similar to the structure shown in Figure 10 A, wherein j=3 and k=2, as shown in figure 18.With reference to Figure 18, this counter 130 includes 5 counting electronic circuits (for convenience of description, below be referred to as the first counting electronic circuit to the, five counting electronic circuit # 31, #32, #33, #34, #35 respectively), wherein the first counting electronic circuit # 31 includes the 6th D flip-flop 134, and second to the 5th counting electronic circuit #32-#35 includes and gate logic switch 132 and the 6th D flip-flop 134.And each counts electronic circuit (i.e. the first counting electronic circuit to the, five counting electronic circuit #31-#35), and the output Q of its 6th D flip-flop 134 can distinguish output timing count signal RC1, RC2, RB1, RB2, RB3.Here, each the 6th D flip-flop 134 of counting electronic circuit is trailing edge and triggers, and its inverse output terminal Q ' feeds back to input D separately, and its output Q be electrically connected to the next stage counting electronic circuit with input gate logic switch 132.
This enable signal EN is input to the trigger end of the first counting electronic circuit # 31, second counts trigger end electronic circuit # 32 and the 6th D flip-flop 134 gate logic switch 132 and the 3rd counting electronic circuit # 33, and the 6th D flip-flop 134 of the first counting electronic circuit # 31 is according to the feedback signal of enable signal EN and its inverse output terminal, and from its output Q output timing count signal RC1, and this sequential count signal RC1 is input to the second counting electronic circuit # 32 with gate logic switch 132, with carry out logical operation (that is, the output Q of the 6th D flip-flop 134 of the first counting electronic circuit # 31 be electrically connected to the second counting electronic circuit # 32 with input gate logic switch 132).
In the second counting electronic circuit #32, the input of itself and gate logic switch 132 is electrically connected to the output Q of the 6th D flip-flop 134 of the output (not shown in the accompanying drawing) of signal generation unit and the first counting electronic circuit #32, be that itself and gate logic switch 132 receives sequential count signal RC1 and enable signal EN so that it is done logical operation, and operation result is outputed to the trigger end of the 6th D flip-flop 134 and the 3rd counting electronic circuit #33 with gate logic switch 132, thereby the 6th D flip-flop 134 of this second counting electronic circuit #32 can be according to itself and the output of gate logic switch 132 and the feedback signal of its inverse output terminal Q ', and from its output Q output timing count signal RC2, and the output of this sequential count signal RC2 and itself and gate logic switch 132 is input to the 3rd that count electronic circuit #33 and gate logic switch 132, with with enable signal EN carry out logical operation (that is, the second counting electronic circuit output Q with output gate logic switch 132 and Qi Di six D flip-flops 134 #32 be electrically connected to the 3rd counting electronic circuit #33 with input gate logic switch 132).
In the 3rd counting electronic circuit #33, the input of itself and gate logic switch 132 is electrically connected to the output (not shown in the accompanying drawing) of signal generation unit, the output Q of the second counting electronic circuit the 6th D flip-flop 134 with output gate logic switch 132 and second counting electronic circuit #32 #32, to receive enable signal EN, the second counting electronic circuit #32 with output gate logic switch 132 and sequential count signal RC2 to carry out logical operation, and operation result is outputed to the trigger end of its 6th D flip-flop 134, the 4th counting electronic circuit #33 with gate logic switch 132 and the 5th counting electronic circuit #35 with gate logic switch 132, and the 6th D flip-flop 134 of the 3rd counting electronic circuit #33 can be according to itself and the output of gate logic switch 132 and the feedback signal of its inverse output terminal Q ', and from its output Q output timing count signal RB1, and the output of this sequential count signal RB1 and itself and gate logic switch 132 is input to the 4th counting electronic circuit #34 with gate logic switch 132, with carry out logical operation (that is, the 3rd counting electronic circuit output Q with output gate logic switch 132 and Qi Di six D flip-flops 134 #33 be electrically connected to the 4th counting electronic circuit #34 with input gate logic switch 132).
In the 4th counting electronic circuit #34, the input of itself and gate logic switch 132 is electrically connected to the output Q of the 3rd counting electronic circuit the 6th D flip-flop 134 with output gate logic switch 132 and the 3rd counting electronic circuit #33 #33, be itself and gate logic switch 132 receive the 3rd counting electronic circuit #33 with output gate logic switch 132 and sequential count signal RB1, to carry out logical operation, and with operation result trigger end that is input to its 6th D flip-flop 134 and the 5th counting electronic circuit #35 with gate logic switch 132, in other words, the output of the 4th counting electronic circuit #34 with gate logic switch 132 be electrically connected to the trigger end of its 6th D flip-flop 134 and the 5th counting electronic circuit #35 with input gate logic switch 132, and the 6th D flip-flop 134 of the 4th counting electronic circuit #34 is according to itself and the output of gate logic switch 132 and the feedback signal of its inverse output terminal Q ', and from its output Q output timing count signal RB2, and the output of this sequential count signal RB2 and itself and gate logic switch 132 is input to the 5th counting electronic circuit #35 with gate logic switch 132, with carry out logical operation (that is, the 4th counting electronic circuit output Q with output gate logic switch 132 and Qi Di six D flip-flops 134 #34 be electrically connected to the 5th counting electronic circuit #35 with input gate logic switch 132).
And in the end one-level is counted in the electronic circuit, promptly the 5th count electronic circuit # 35, the input of itself and gate logic switch 132 be electrically connected to the 3rd counting electronic circuit # 33 with output gate logic switch 132, the output Q of the 4th counting electronic circuit the 6th D flip-flop 134 with output gate logic switch 132 and the 4th counting electronic circuit # 34 #34, with receive the 3rd counting electronic circuit # 33 and the 4th counting electronic circuit # 34 with output gate logic switch 132 and sequential count signal RB2 to carry out logical operation, and operation result is exported to the trigger end of its 6th D flip-flop 134, thereby the 6th D flip-flop 134 of this 5th counting electronic circuit # 35 can be according to itself and the output of gate logic switch 132 and the feedback signal of its inverse output terminal Q ', and from its output Q output timing count signal RB3.
And the structure of first decoder 141 is similar to structure shown in Figure 12, j=3 wherein, as shown in figure 19.With reference to Figure 19, this first decoder 141 is 3 pairs 8 decoders, and it includes 3 reversers 151,152,153 and 2
3(=8) individual and gate logic switch 161,162,163,164,165,166,167,168; Here, sequential count signal RB1, RB2, RB3 are input to reverser 151,152,153 respectively, wherein sequential count signal RB1 is input to and gate logic switch 161,162,163,164 after oppositely, sequential count signal RB2 is input to and gate logic switch 161,162,165,166 after oppositely, and sequential count signal RB3 is input to and gate logic switch 161,163,165,167 after oppositely; And, with gate logic switch 161 with reverse sequential count signal RB1, RB2, RB3 carries out logical operation to produce the first activation signal B1, with gate logic switch 162 with reverse sequential count signal RB1, RB2 and sequential count signal RB3 carry out logical operation to produce the first activation signal B2, with gate logic switch 163 with reverse sequential count signal RB1, RB3 and sequential count signal RB2 carry out logical operation to produce the first activation signal B3, with gate logic switch 164 with reverse sequential count signal RB1 and sequential count signal RB2, RB3 carries out logical operation to produce the first activation signal B4, with gate logic switch 165 with reverse sequential count signal RB2, RB3 and sequential count signal RB1 carry out logical operation to produce the first activation signal B5, with gate logic switch 166 with reverse sequential count signal RB2 and sequential count signal RB1, RB3 carries out logical operation to produce the first activation signal B6, with gate logic switch 167 with reverse sequential count signal RB3 and sequential count signal RB1, RB2 carries out logical operation producing the first activation signal B7, and with gate logic switch 168 with sequential count signal RB1, RB2, RB3 carries out logical operation to produce the first activation signal B8.
The structure of second decoder 142 is similar to the structure shown in Figure 13, k=2 wherein, as shown in figure 20.With reference to Figure 20, this second decoder 142 is 2 pairs 4 decoders, and it includes 2 reversers 171,172 and 2
2(=4) individual and gate logic switch 181,182,183,184; Here, sequential count signal RC1, RC2 are input to reverser 171,172 respectively, and wherein sequential count signal RC1 is input to and gate logic switch 181,182 after oppositely, and sequential count signal RC2 is input to and gate logic switch 181,183 after oppositely; And, with gate logic switch 181 reverse sequential count signal RC1, RC2 are carried out logical operation to produce the second activation signal C1, with gate logic switch 182 reverse sequential count signal RC1 and sequential count signal RC2 are carried out logical operation to produce the second activation signal C2, with gate logic switch 183 reverse sequential count signal RC2 and sequential count signal RC1 are carried out logical operation producing the second activation signal C3, and sequential count signal RC1, RC2 are carried out logical operation to produce the second activation signal C4 with gate logic switch 184.
In above-mentioned framework, the measured sequential chart of each signal is shown in Figure 21 A and 21B.
At last, these address signals A1-A16, the first activation signal B1-B8 and the second activation signal C1-C4 can be input to ink spray module 200, to carry out 16 * 2
3* 2
2(=16 * 8 * 4=512) individual heater circuit H
1,1,1, H
2,1,1-H
16,1,1, H
1,2,1, H
2,2,1-H
16,2,1-H
1,8,1, H
2,8,1-H
16,8,1, H
1,1,2, H
2,1,2-H
16,1,2-H
1,8,2, H
2,8,2-H
16,8,2-H
1,8,4, H
2,8,4-H
16,8,4Driving control, and then can control the running of 512 spray orifices, as shown in figure 22.
And each heater circuit (is respectively heater circuit H
1,1,1-H
16,1,1-H
1,8,4-H
16,8,4) include with the gate logic switch and (be respectively and gate logic switch Z
1,1,1-Z
16,1,1-Z
1,8,4-Z
16,8,4), transistor switch (is respectively transistor switch M
1,1,1-M
16,1,1-M
1,8,4-M
16,8,4) and resistor assembly (be respectively resistor assembly R
1,1,1-R
16,1,1-R
1,8,4-R
16,8,4), as shown in figure 23.Wherein, the structure of each heater circuit is same as structure shown in Figure 15 haply, so its operation principles repeats no more here.
Wherein, heater circuit H
1,1,1Be itself and gate logic switch Z
1,1,1Receiver address signal A1, the first activation signal B1 and the second activation signal C1 to be to carry out logical operation, in other words, and heater circuit H
1,1,1Control by address signal A1, the first activation signal B1 and the second activation signal C1 drives; Heater circuit H
2,1,1Be itself and gate logic switch Z
1,2,1Receiver address signal A1, the first activation signal B2 and the second activation signal C1 to be to carry out logical operation, in other words, and heater circuit H
1,2,1Control by address signal A1, the first activation signal B2 and the second activation signal C1 drives; By that analogy, this heater circuit H
16,8,4Be itself and gate logic switch Z
16,8,4Receiver address signal A16, the first activation signal B8 and the second activation signal C4 to be to carry out logical operation, in other words, and heater circuit H
16,8,4Control by address signal A16, the first activation signal B8 and the second activation signal C4 drives; Like this, can reach the running control of 512 spray orifices.
In another embodiment, this offset buffer 120 also can be according to the first clock signal C K1 and the 3rd clock signal C K3 shifted data Data to produce a group address signal A1-Ai, as shown in figure 24; Wherein, the 3rd clock signal C K3 is half of the first clock signal C K1.Wherein, signal generation unit 110, counter 130, first decoder 141, second decoder 142 and ink spray module 200 all can adopt above-mentioned structure, so its operation principles does not repeat them here.
Please refer to Figure 25 A and Figure 25 B, it shows the circuit diagram of offset buffer one embodiment; This offset buffer 120 includes i displacement electronic circuit (for convenience of description, below be referred to as first displacement electronic circuit to the i displacement electronic circuit respectively, and the tenth displacement electronic circuit # 210 only is shown in the accompanying drawings, follow-up then by that analogy), and the electronic circuit that respectively is shifted includes two D flip-flops (being referred to as the 4th D flip-flop 122 and the 5th D flip-flop 124 for convenience of description, respectively).
Here, the 4th D flip-flop 122 in individual odd level displacement electronic circuit triggers for rising edge, 122 of the 4th D flip-flops in individual even level displacement electronic circuit are the trailing edge triggering, and the 5th D flip-flop 124 in the electronic circuit that respectively is shifted then all adopts rising edge to trigger.
Wherein, this offset buffer 120 is input to the respectively trigger end of the 4th D flip-flop 122 with the 3rd clock signal C K3, and the trigger end that the first clock signal C K1 is input to each the 5th D flip-flop 124.
In the first displacement electronic circuit # 21, the input D of its 4th D flip-flop 122 receives data Data, and input D and next odd level that output Q is electrically connected to the 5th D flip-flop 124 are shifted electronic circuit (here, the input D of the 4th D flip-flop 122 i.e. the 3rd displacement electronic circuit #23), thereby the 5th D flip-flop 124 of this first displacement electronic circuit # 21 can be according to the output and the first clock signal C K1 of the 4th D flip-flop 122, and from its output Q OPADD signal A1.
In the second displacement electronic circuit # 22, the input D of its 4th D flip-flop 122 receives data Data, and input D and next even level that output Q is electrically connected to the 5th D flip-flop 124 are shifted electronic circuit (here, the input D of the 4th D flip-flop 122 i.e. the 4th displacement electronic circuit #24), thereby the 5th D flip-flop 124 of this second displacement electronic circuit # 22 can be according to the output and the first clock signal C K1 of the 4th D flip-flop 122, and from its output Q OPADD signal A2.
Subsequently, in odd level displacement electronic circuit (promptly beginning) from the 3rd displacement electronic circuit #23, the input D of its 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of last odd level displacement electronic circuit, and output Q is electrically connected to the input D of the 4th D flip-flop 122 of the input D of its 5th D flip-flop 124 and next odd level displacement electronic circuit, thereby its 5th D flip-flop 124 can be according to the output and the first clock signal C K1 of its 4th D flip-flop 122, and from output Q OPADD signal; By that analogy to last odd level displacement electronic circuit, in the electronic circuit of odd level displacement in the end, the input D of its 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of last odd level displacement electronic circuit, and the output Q of its 4th D flip-flop 122 only is electrically connected to the input D of the 5th D flip-flop 124, thereby its 5th D flip-flop 124 is promptly according to the output and the first clock signal C K1 of the 4th D flip-flop 122, and from output Q OPADD signal.
In like manner, in even level displacement electronic circuit (promptly beginning) subsequently from the 4th displacement electronic circuit #24, the input D of its 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of last even level displacement electronic circuit, and output Q is electrically connected to the input D of the 4th D flip-flop 122 of the input D of its 5th D flip-flop 124 and next even level displacement electronic circuit, thereby its 5th D flip-flop 124 can be according to the output and the first clock signal C K1 of its 4th D flip-flop 122, and from output Q OPADD signal; By that analogy to last even level displacement electronic circuit, in the electronic circuit of even level displacement in the end, the input D of its 4th D flip-flop 122 is electrically connected to the output Q of the 4th D flip-flop 122 of last even level displacement electronic circuit, and the output Q of its 4th D flip-flop 122 only is electrically connected to the input D of the 5th D flip-flop 124, thereby its 5th D flip-flop 124 is promptly according to the output and the first clock signal C K1 of the 4th D flip-flop 122, and from output Q OPADD signal.
In addition, in offset buffer 120, also can be that the 4th D flip-flop 122 in each odd level displacement electronic circuit is the trailing edge triggering, and the 4th D flip-flop 122 in each even level displacement electronic circuit triggers for rising edge, yet the 5th D flip-flop 124 in the electronic circuit that respectively is shifted still all adopts rising edge to trigger, shown in Figure 26 A and 26B.
Like this, cooperate the data of required printing and/or the spray orifice number of design,, can increase considerably the number of spray orifice, and the number that still can keep external connector is unlikely to increase considerably by the above-mentioned i of any design, j and k.
In other words, can be according to the data of required printing and/or the spray orifice number of design, and the quantity of the quantity of design displacement electronic circuit and/or counting electronic circuit, produce the address signal and the sequential count signal of requirement, and the suitable decoder of arranging in pairs or groups is to carry out the decoding of sequential count signal, can produce address signal, first activation signal and second activation signal of requirement, to control the running control of a large amount of spray orifices.
Though above-mentioned two decoders (i.e. first decoder and second decoder) that all adopt on line design, also can be merged into single decoder with first decoder and second decoder.
And, for further reducing the number of external connector, also the sequential count signal that counter 130 is produced can be divided into three groups, four groups or even more, and the decoder of arranging in pairs or groups is respectively deciphered.With reference to Figure 27 A and 27B, this multi-mission spray printing system circuit includes control circuit 100 and ink spray module 200.Here, control circuit 100 includes signal generation unit 110, offset buffer 120, counter 130 and decoding module 140.And decoding module 140 includes N decoder (that is, first decoder 141, second decoder to the N decoder 142-14N).Wherein, the structure and the operation principles of signal generation unit 110, offset buffer 120 and ink spray module 200, same as described above haply, so do not repeat them here.
And, the structure of this counter 130 is identical with said structure haply, it includes a plurality of counting electronic circuits (for convenience of description, below be referred to as first counting electronic circuit to the n+ respectively ... + k+j counting electronic circuit # 31, #32, #33, #34-#3 (n-1), #3n, #3 (n+1)-#3 (n+ ... + k+j)), wherein the first counting electronic circuit # 31 includes the 6th D flip-flop 134, and second to n+ ... + k+j counting electronic circuit # 32 ~ #3 (n+ ... + k+j) include and gate logic switch 132 and the 6th D flip-flop 134, to produce N group sequential count signal RX according to enable signal EN (promptly, first group of sequential count signal j * RXs shown in Figure 27 A and the 27B, second group of sequential count signal k * RXs to the N group sequential count signal n * RXs), and each group sequential count signal R is exported to corresponding decoder (promptly, first decoder to the N decoder 141-14N), as shown in figure 28.
And each decoder all includes a plurality of reversers and a plurality of cascode logic switch as shown in figure 29, and its structure and operation principles are known by those skilled in the art, so do not repeat them here.Here, each decoder (promptly, first decoder to the N decoder 141-14N) receives one group of sequential count signal R respectively (promptly, first group of sequential count signal j * Rs, second group of sequential count signal k * Rs to the N group sequential count signal n * Rs), and with its decoding, to export one group of activation signal (that is first activation signal B1-B2, respectively
j, the second activation signal C1-C2
kTo N activation signal E1-E2
n), shown in Figure 27 A and 27B.
At last, again with address signal A1-Ai and N group activation signal (that is first activation signal B1-B2,
j, the second activation signal C1-C2
kTo N activation signal E1-E2
n) input to ink spray module 200, to control its running, that is to say, by address signal A1-Ai and N group activation signal (that is first activation signal B1-B2,
j, the second activation signal C1-C2
kTo N activation signal E1-E2
n) any combination can realize i * 2
j* 2
k* ... * 2
nThe driving control of individual heater circuit, and then can control i * 2
j* 2
k* ... * 2
nThe running of individual spray orifice.Wherein, i, j, k and n are positive integer.
With reference to Figure 30, it shows the circuit diagram of heater circuit one embodiment; This heater circuit
Include and the gate logic switch
, transistor switch
And resistor assembly
Here, with the gate logic switch
Input be electrically connected in offset buffer 120 and the decoding module 140 each decoder (promptly, first decoder to the N decoder 141-14N), to receive from the address signal Ai of offset buffer 120 and respectively (promptly from each decoder, first decoder to the N decoder 141-14N) activation signal (that is first activation signal B2,
j, the second activation signal C2
kTo N activation signal E2
n); With the gate logic switch
Input be electrically connected to transistor switch
Grid, in other words, with the gate logic switch
With received address signal Ai and activation signal (that is first activation signal B2,
j, the second activation signal C2
kTo N activation signal E2
n) carry out logical operation, with output drive signal
Control transistor switch
Conducting whether; And, transistor switch
Source ground, its drain electrode is electrically connected to resistor assembly
An end, and at resistor assembly
The other end apply suitable voltage.
Wherein, as address signal Ai and each activation signal (that is first activation signal B2,
j, the second activation signal C2
kTo N activation signal E2
n) when being logic high signal " 1 " simultaneously, process and gate logic switch
Computing after can produce the driving signal of logic high signal " 1 "
, so that transistor switch
Present conducting state, at this moment, resistor assembly
Just can enter duty and produce heat, and then drive corresponding nozzle emission ink and print.Like this, can utilize less control signal to realize increasing considerably the number of spray orifice, and the number that still can keep external connector is unlikely to increase considerably.And, can be according to directly extracting the corresponding spray orifice of data segment in the data of required printing.
For convenience of description, here to utilize three decoders to realize that the driving of 512 spray orifices is controlled to be example, describes.With reference to Figure 31 A and 31B, this multi-mission spray printing system circuit includes control circuit 100 and ink spray module 200.Here, control circuit 100 includes signal generation unit 110, offset buffer 120, counter 130 and decoding module 140, and this decoding module 140 includes first decoder 141, second decoder 142 and the 3rd decoder 143.Wherein, the structure and the operation principles of signal generation unit 110, offset buffer 120 and ink spray module 200, same as described above haply, so do not repeat them here.
Here, offset buffer 120 has 4 displacement electronic circuits (being respectively the first displacement electronic circuit #21, the second displacement electronic circuit #22, the 3rd displacement electronic circuit #23 and the 4th displacement electronic circuit #24), to produce 4 address signal A1-A4 (shown in Figure 32 A, 32B, 32C) according to data Data, second clock signal CK2 and enable signal EN (or according to data Data, the first clock signal C K1 and the 3rd clock signal C K3).And counter 130 has 7 displacement electronic circuits and (is respectively the first displacement electronic circuit #31, the second displacement electronic circuit #32, the 3rd displacement electronic circuit #33, the 4th displacement electronic circuit #34, the 5th displacement electronic circuit #35, the 6th displacement electronic circuit #36 and the 7th displacement electronic circuit #37), to count according to enable signal EN to produce 7 sequential count signal RB1-RB3, RC1, RC2, RD1, RD2 (as shown in figure 33), and with these sequential count signals RB1-RB3, RC1, RC2, RD1, RD2 is divided into three groups to export to first decoder 141 respectively, second decoder 142 and the 3rd decoder 143.Wherein, first decoder 141 is 3 pairs 8 (=2
3) decoder, it includes 151,152,153 and 8 of 3 reversers and gate logic switch 161-168, and by these reversers 151,152,153 and with the combination of gate logic switch 161-168, can produce 2 according to sequential count signal RB1-RB3
3(=8) individual first activation signal B1-B8, as shown in figure 19.Second decoder 142 is 2 pairs 4 (=2
2) decoder, it includes 171,172 and 4 of 2 reversers and gate logic switch 181,182,183,184, and by these reversers 171,172 and with the combination of gate logic switch 181-184, can produce 2 according to sequential count signal RC1, RC2
2(=4) individual second activation signal C1-C4, as shown in figure 20.And the 3rd decoder 143 also adopts 2 pairs 4 (=2
2) decoder, it includes 173,174 and 4 of 2 reversers and gate logic switch 185,186,187,188, and by these reversers 173,174 and with the combination of gate logic switch 185-188, can produce 2 according to sequential count signal RD1, RD2
2(=4) individual the 3rd activation signal D1-D4, as shown in figure 34.
At last, again address signal A1-A4, the first activation signal B1-B8, the second activation signal C1-C4 and the 3rd activation signal D1-D4 are input to ink spray module 200, to control its running, that is to say that any combination by address signal A1-A4, the first activation signal B1-B8, the second activation signal C1-C4 and the 3rd activation signal D1-D4 can reach 4 * 2
3* 2
2* 2
2(=4 * 8 * 4 * 4=512) individual heater circuit H
1,1,1,1, H
2,1,1,1-H
4,1,1,1, H
1,1,2,1-H
4,1,4,1, H
1,2,1,1, H
2,2,1,1-H
4,2,1,1, H
1,2,2,1-H
4,2,4,1-H
1,8,1,1, H
2,8,1,1-H
4,8,1,1, H
1,8,2,1-H
4,8,4,1, H
1,1,1,2, H
2,1,1,2-H
4,1,1,2, H
1,1,2,2-H
4,1,4,2-H
1,8,1,2, H
2,8,1,2-H
4,8,1,2, H
1,8,2,2-H
4,8,4,2-H
1,8,1,4, H
2,8,1,4-H
4,8,1,4, H
1,8,2,4-H
4,8,4,4Driving control, and then can control 4 * 2
3* 2
2* 2
2(running of=4 * 8 * 4 * 4=512) individual spray orifices, as shown in figure 35.
And each heater circuit (is respectively heater circuit H
1,1,1,1-H
4,1,4,1-H
1,8,1,4-H
4,8,4,4) include with the gate logic switch and (be respectively and gate logic switch Z
1,1,1,1-Z
4,1,4,1-Z
1,8,1,4-Z
4,8,4,4), transistor switch (is respectively transistor switch M
1,1,1,1-M
4,1,4,1-M
1,8,1,4-M
4,8,4,4) and resistor assembly (be respectively resistor assembly R
1,1,1,1-R
4,1,4,1-R
1,8,1,4-R
4,8,4,4), as shown in figure 36.Wherein, the structure of each heater circuit structure with shown in Figure 15 haply is identical, so its operation principles does not repeat them here.
Wherein, heater circuit H
1,1,1,1Be itself and gate logic switch Z
1,1,1,1Receiver address signal A1, the first activation signal B1, the second activation signal C1 and the 3rd activation signal D1 to be to carry out logical operation, in other words, and heater circuit H
1,1,1,1Control by address signal A1, the first activation signal B1, the second activation signal C1 and the 3rd activation signal D1 drives; By that analogy, for heater circuit H
4,8,4,4Be itself and gate logic switch Z
4,8,4,4Receiver address signal A4, the first activation signal B8, the second activation signal C4 and the 3rd activation signal D4 to be to carry out logical operation, in other words, and heater circuit H
4,8,4,4Control by address signal A4, the first activation signal B8, the second activation signal C4 and the 3rd activation signal D4 drives; Like this, can reach the running control of 512 spray orifices.
Here, transistor switch can adopt the field-effect transistor with big channel breadth length ratio (channel width/length), reduces the dead resistance (parasitic resistance) of series connection, so with power concentration in thermal resistance.Wherein, this field-effect transistor can be the high power assembly with big channel breadth length ratio.And at the ink jet-print head than droplet, to spray the required power of single drop lower because of it, therefore under the situation that the voltage that main frame provided does not increase, can improve resistor assembly resistance so that the power that resistor assembly produced descend thereupon.
In addition, this transistor switch also can adopt asymmetric mos field effect transistor, to realize low driving transistors assembly resistance and small transistor area.And the drain electrode end of this asymmetric mos field effect transistor can be dual diffusion (double diffused drains; DDD), and its source terminal is low pressure N+ type diffusion structure, to reduce dead resistance.
In addition, can utilize complementary metal oxide semiconductor field effect transistor (CMOS) to constitute employed trigger here,, the power consumption of whole ink-jet chip on control circuit can be reduced to minimum comparatively speaking with low-power consumption.In fact, when spray printing during one period long duration, it mainly influences on the assembly of ink-jet chip temperature or the resistor assembly in ink spray module, the power that the control circuit running is consumed reduces, to arrive the heat drop that it was produced minimum, like this, temperature-controlling module can very accurately be read the heat that produces because of thermal resistance (being the resistor assembly in the ink spray module) consumed power.
Though the present invention by aforesaid preferred embodiment openly as above; but these embodiment are not in order to limit the present invention; anyly be familiar with those of ordinary skill in the art; without departing from the spirit and scope of the present invention; various modifications and changes may be made, and therefore scope of patent protection of the present invention has this specification appending claims to limit.
Claims (41)
1, a kind of control circuit of multi-mission spray printing system is used to drive at least one heater circuit, includes:
The signal generation unit is used for producing enable signal according to one first clock signal and data;
Offset buffer is electrically connected to this signal generation unit, and with these data that are shifted according to this enable signal and second clock signal, to produce i address signal, wherein i is a positive integer;
Counter is electrically connected to this signal generation unit, to count according to this enable signal, to produce a plurality of sequential count signals; And
N decoder, be electrically connected to this counter, to receive these sequential count signals part wherein respectively, wherein each described decoder be used for will receive these sequential count signals decodings to produce a plurality of activation signals, wherein N is greater than or equal to 2 positive integer;
Wherein, realize the driving control of this heater circuit by these address signals and N group activation signal.
2, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
3, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through these reversers one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through these reversers wherein another each and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
4, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
5, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through these reversers one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in these reversers another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
6, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this offset buffer includes:
I displacement electronic circuit, each described displacement electronic circuit includes:
The 4th D flip-flop, the trigger end of the 4th D flip-flop receive this second clock signal; And
The 5th D flip-flop, the input of the 5th D flip-flop is electrically connected to the output of the 4th D flip-flop, the trigger end of the 5th D flip-flop is used to receive this enable signal, exports this address signal with output and this enable signal according to the 4th D flip-flop;
Wherein, be somebody's turn to do in the displacement electronic circuit first, the input of the 4th D flip-flop is used to receive these data; And in the second displacement electronic circuit was shifted electronic circuit to i-1, the output of the 4th D flip-flop was electrically connected to the input of the 4th D flip-flop of next described displacement electronic circuit.
7, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
The 6th D flip-flop, the inverse output terminal of the 6th D flip-flop feeds back to the input of the 6th D flip-flop;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of this 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, each described and gate logic switch input terminal are electrically connected to the output of the output of the 6th D flip-flop of previous stage this counting electronic circuit and this and gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also are electrically connected to this counting electronic circuit of last odd level and the output gate logic switch and output described and the gate logic switch.
8, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
Reverser;
The 6th D flip-flop, the output of the 6th D flip-flop feed back to the input of the 6th D flip-flop through this reverser;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of the 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, respectively be electrically connected to the output and this output of the 6th D flip-flop of this counting electronic circuit of previous stage with the gate logic switch with the gate logic switch input terminal, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
9, the control circuit of multi-mission spray printing system as claimed in claim 1 is characterized in that, also comprises:
At least one and gate logic switch, it is electrically connected to this offset buffer and these decoders, each described and gate logic switch are used for that one of them carries out logical operation with those address signals one of them and each group activation signal, drive signal to produce, to drive corresponding heater circuit.
10, the control circuit of multi-mission spray printing system as claimed in claim 9 is characterized in that, described number with the gate logic switch is organized the product of the number of those activation signals for the number of those address signals with each.
11, a kind of control circuit of multi-mission spray printing system, it is used to drive at least one heater circuit, includes:
The signal generation unit is used for producing enable signal according to one first clock signal and data;
Offset buffer is used for according to this first clock signal and the 3rd clock signal this data that are shifted, and to produce i address signal, wherein i is a positive integer;
Counter is electrically connected to this signal generation unit, to count according to this enable signal, to produce a plurality of sequential count signals; And
N decoder, many these counters that are electrically connected, to receive the part in these sequential count signals respectively, wherein the sequential count signal decoding that is used for receiving of each decoder is to produce a plurality of activation signals, and wherein N is greater than or equal to 2 positive integer;
Wherein, realize the driving control of this heater circuit by address signal and N group activation signal.
12, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
13, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through reverser one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through reverser wherein another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
14, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
15, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through reverser one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in the reverser another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
16, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this offset buffer includes:
I displacement electronic circuit, each described displacement electronic circuit includes:
The 4th D flip-flop, the trigger end of the 4th D flip-flop receives the 3rd clock signal; And
The 5th D flip-flop, the input of the 5th D flip-flop is electrically connected to the output of the 4th D flip-flop, the trigger end of the 5th D flip-flop is used to receive this first clock signal, exports this address signal with output and this first clock signal according to the 4th D flip-flop;
Wherein, should be somebody's turn to do in the displacement electronic circuit by displacement electronic circuit and second first, the input of the 4th D flip-flop is used to receive these data; And in the 3rd this displacement electronic circuit is shifted electronic circuit to i-1, the output of the 4th D flip-flop of odd level displacement electronic circuit is electrically connected to the input of the 4th D flip-flop of next odd level displacement electronic circuit, and the output of the 4th D flip-flop of this displacement electronic circuit of even level is electrically connected to the input of the 4th D flip-flop of next even level displacement electronic circuit.
17, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
The 6th D flip-flop, the inverse output terminal of the 6th D flip-flop feeds back to the input of the 6th D flip-flop;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of the 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, each described and gate logic switch input terminal be electrically connected to previous stage counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, in the odd level displacement electronic circuit each and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
18, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
Reverser;
The 6th D flip-flop, the output of the 6th D flip-flop feed back to the input of the 6th D flip-flop through this reverser;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of the 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to the first counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, each described and gate logic switch input terminal be electrically connected to previous stage counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
19, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, also comprises:
A plurality of and gate logic switch, be electrically connected to this offset buffer and decoder, described each be used for the gate logic switch that one of them carries out logical operation with those address signals one of them and each group activation signal, drive signal to produce, to drive corresponding heater circuit.
20, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, the described number that is address signal with the number gate logic switch is organized the product of the number of activation signal with each.
21, the control circuit of multi-mission spray printing system as claimed in claim 11 is characterized in that, the 3rd clock signal is half of this first clock signal.
22, a kind of multi-mission spray printing system circuit is used to drive a plurality of spray orifices, includes:
Control circuit includes:
The signal generation unit is used for producing enable signal according to one first clock signal and data;
Offset buffer is electrically connected to this signal generation unit, and with these data that are shifted according to this enable signal and second clock signal, to produce i address signal, wherein i is a positive integer;
Counter is electrically connected to this signal generation unit, to count according to this enable signal, to produce a plurality of sequential count signals; And
N decoder is electrically connected to this counter, to receive the part in the sequential count signal respectively, wherein each decoder be used for will receive the decoding of sequential count signal to produce a plurality of activation signals, wherein N is greater than or equal to 2 positive integer; And
Ink spray module includes: at least one heater circuit, and corresponding to described spray orifice, wherein each described heater circuit includes:
With the gate logic switch, be electrically connected to this offset buffer and decoder, one of them carries out logical operation to be used for that those address signals one of them and each are organized activation signal, drives signal to produce;
Transistor switch, the grid of this transistor switch are electrically connected to the output of this and gate logic switch, to drive signal and conducting according to this; And
Resistor assembly, an end of this resistor assembly is electrically connected to the drain electrode of this transistor switch, and the other end is used to receive suitable voltage or electric current, with when this transistor switch conducting and produce heat, to drive corresponding described spray orifice.
23, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
24, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through described reverser one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in the described reverser another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
25, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
26, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through described reverser one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in the described reverser another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
27, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this offset buffer includes:
I displacement electronic circuit, each described displacement electronic circuit includes:
The 4th D flip-flop, the trigger end of the 4th D flip-flop receive this second clock signal; And
The 5th D flip-flop, the input of the 5th D flip-flop is electrically connected to the output of the 4th D flip-flop, the trigger end of the 5th D flip-flop is used to receive this enable signal, exports this address signal with output and this enable signal according to the 4th D flip-flop;
Wherein, be somebody's turn to do in the displacement electronic circuit first, the input of the 4th D flip-flop is used to receive these data; And in second this displacement electronic circuit should be shifted electronic circuit to i-1, the output of the 4th D flip-flop was electrically connected to the input of the 4th D flip-flop of next displacement electronic circuit.
28, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
The 6th D flip-flop, the inverse output terminal of the 6th D flip-flop feeds back to the input of the 6th D flip-flop;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of this 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, each described and gate logic switch input terminal are electrically connected to the output of the output of the 6th D flip-flop of previous stage this counting electronic circuit and this and gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
29, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
Reverser;
The 6th D flip-flop, the output of the 6th D flip-flop feed back to the input of the 6th D flip-flop through this reverser;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, should should count in the electronic circuit to afterbody by the counting electronic circuit second, each described counting electronic circuit also includes:
With the gate logic switch, should be electrically connected to the trigger end of this 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, should should count in the electronic circuit by counting electronic circuit to afterbody the 4th, each described and gate logic switch input terminal are electrically connected to the output of the output of the 6th D flip-flop of previous stage this counting electronic circuit and this and gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
30, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this transistor switch is asymmetric mos field effect transistor.
31, multi-mission spray printing system circuit as claimed in claim 22 is characterized in that, this transistor switch is a field-effect transistor, and this field-effect transistor has big channel breadth length ratio.
32, a kind of multi-mission spray printing system circuit is used to drive a plurality of spray orifices, includes:
Control circuit includes:
The signal generation unit is used for producing enable signal according to first clock signal and data;
Offset buffer is used for according to this first clock signal and the 3rd clock signal this data that are shifted, and to produce i address signal, wherein i is a positive integer;
Counter is electrically connected to this signal generation unit, to count according to this enable signal, to produce a plurality of sequential count signals; And
N decoder is electrically connected to this counter, to receive the part in the sequential count signal respectively, wherein each decoder be used for will receive the decoding of sequential count signal to produce a plurality of activation signals, wherein N is greater than or equal to 2 positive integer; And
Ink spray module includes: at least one heater circuit, and corresponding to described spray orifice, wherein each described heater circuit includes:
With the gate logic switch, be electrically connected to this offset buffer and decoder, one of them carries out logical operation to be used for that those address signals one of them and each are organized activation signal, drives signal to produce;
Transistor switch, the grid of this transistor switch are electrically connected to the output of this and gate logic switch, to drive signal and conducting according to this; And
Resistor assembly, an end of this resistor assembly is electrically connected to the drain electrode of this transistor switch, and the other end is used to receive suitable voltage or electric current, with when this transistor switch conducting and produce heat, to drive corresponding described spray orifice.
33, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
34, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through those reversers one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in the described reverser another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop; And
With the gate logic switch, be used for according to these data and should or the output of gate logic switch export this enable signal.
35, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this signal generation unit includes:
First D flip-flop, the inverse output terminal of this first D flip-flop feeds back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the inverse output terminal of this second D flip-flop feeds back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
36, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this signal generation unit includes:
A plurality of reversers;
First D flip-flop, the output of this first D flip-flop through described reverser one of them and feed back to the input of this first D flip-flop, and the trigger end of this first D flip-flop receives this first clock signal;
Second D flip-flop, in parallel with this first D flip-flop, the output of this second D flip-flop through in the described reverser another and feed back to the input of this second D flip-flop, and the trigger end of this second D flip-flop receives this first clock signal;
Or the gate logic switch, should or the input of gate logic switch be electrically connected to the output of this first D flip-flop and the output of this second D flip-flop;
The 3rd D flip-flop, the input of the 3rd D flip-flop is used to receive these data; And
With the gate logic switch, should be electrically connected to this or the output of gate logic switch and the output of the 3rd D flip-flop with input of gate logic switch, with according to should or the output of gate logic switch and the output of the 3rd D flip-flop export this enable signal.
37, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this offset buffer includes:
I displacement electronic circuit, each described displacement electronic circuit includes:
The 4th D flip-flop, the trigger end of the 4th D flip-flop receives the 3rd clock signal; And
The 5th D flip-flop, the input of the 5th D flip-flop is electrically connected to the output of the 4th D flip-flop, the trigger end of the 5th D flip-flop is used to receive this first clock signal, exports this address signal with output and this first clock signal according to the 4th D flip-flop;
Wherein, should be somebody's turn to do in the displacement electronic circuit by displacement electronic circuit and second first, the input of the 4th D flip-flop is used to receive these data; And in the 3rd this displacement electronic circuit should be shifted electronic circuit to i-1, the output of the 4th D flip-flop of odd level displacement electronic circuit is electrically connected to the input of the 4th D flip-flop of next odd level displacement electronic circuit, and the output of the 4th D flip-flop of even level displacement electronic circuit is electrically connected to the input of the 4th D flip-flop of next even level displacement electronic circuit.
38, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
The 6th D flip-flop, the inverse output terminal of the 6th D flip-flop feeds back to the input of the 6th D flip-flop;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, to afterbody counting electronic circuit, each described counting electronic circuit also includes at the second counting electronic circuit:
With the gate logic switch, should be electrically connected to the trigger end of the 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, second should counting electronic circuit in, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, count in the electronic circuit at the 4th counting electronic circuit to afterbody, each described and gate logic switch input terminal are electrically connected to the output of the output of the 6th D flip-flop of previous stage this counting electronic circuit and this and gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
39, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this counter includes:
A plurality of counting electronic circuits, each described counting electronic circuit includes:
Reverser;
The 6th D flip-flop, the output of the 6th D flip-flop feed back to the input of the 6th D flip-flop through this reverser;
Wherein, should count in the electronic circuit first, the trigger end of the 6th D flip-flop is used to receive this enable signal, to export this sequential count signal; And
Wherein, to afterbody counting electronic circuit, each described counting electronic circuit also includes at the second counting electronic circuit:
With the gate logic switch, should be electrically connected to the trigger end of the 6th D flip-flop with the output of gate logic switch; And
The 6th D flip-flop is used for according to exporting this sequential count signal with the output of gate logic switch and the input of the 6th D flip-flop;
Wherein, in the second counting electronic circuit, should with input of gate logic switch be electrically connected to this signal generation unit with the output of the 6th D flip-flop that receives this enable signal and be electrically connected to first this counting electronic circuit to receive this sequential count signal;
Wherein, should count in the electronic circuit the 3rd, should with the gate logic switch input terminal be electrically connected to this signal generation unit with receive this enable signal and be electrically connected to second this counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch to receive this sequential count signal and the output of being somebody's turn to do with the gate logic switch; And
Wherein, count in the electronic circuit at the 4th counting electronic circuit to afterbody, each described and gate logic switch input terminal be electrically connected to previous stage counting electronic circuit the 6th D flip-flop output and should with the output of gate logic switch, to receive this sequential count signal and this output with the gate logic switch, wherein, each of odd level displacement electronic circuit and gate logic switch input terminal also be electrically connected to last odd level counting electronic circuit with the output gate logic switch, and should with the output of gate logic switch.
40, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this transistor switch is asymmetric mos field effect transistor.
41, multi-mission spray printing system circuit as claimed in claim 32 is characterized in that, this transistor switch is a field-effect transistor, and this field-effect transistor has the high power assembly of big channel breadth length ratio.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101329869A CN100448673C (en) | 2005-12-31 | 2005-12-31 | Multi-mission spray printing system circuit and control circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101329869A CN100448673C (en) | 2005-12-31 | 2005-12-31 | Multi-mission spray printing system circuit and control circuit thereof |
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| CN100448673C true CN100448673C (en) | 2009-01-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519416A (en) * | 1992-04-23 | 1996-05-21 | Canon Kabushiki Kaisha | Recording apparatus with cascade connected integrated drive circuits |
| US6467863B1 (en) * | 1999-06-04 | 2002-10-22 | Canon Kabushiki Kaisha | Ink jet recording head, and ink jet recording device |
| CN1672937A (en) * | 2004-03-24 | 2005-09-28 | 财团法人工业技术研究院 | Printing unit, ink jet head, ink jet head driving circuit and its control method |
| CN1680097A (en) * | 2004-04-07 | 2005-10-12 | 佳能株式会社 | Serial data transfer method, electric device, and printing apparatus |
-
2005
- 2005-12-31 CN CNB2005101329869A patent/CN100448673C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519416A (en) * | 1992-04-23 | 1996-05-21 | Canon Kabushiki Kaisha | Recording apparatus with cascade connected integrated drive circuits |
| US6467863B1 (en) * | 1999-06-04 | 2002-10-22 | Canon Kabushiki Kaisha | Ink jet recording head, and ink jet recording device |
| CN1672937A (en) * | 2004-03-24 | 2005-09-28 | 财团法人工业技术研究院 | Printing unit, ink jet head, ink jet head driving circuit and its control method |
| CN1680097A (en) * | 2004-04-07 | 2005-10-12 | 佳能株式会社 | Serial data transfer method, electric device, and printing apparatus |
Also Published As
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|---|---|
| CN1990245A (en) | 2007-07-04 |
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