CN100446504C - Shared storage convertion device and method for line frame protocol data under broadband CDMA system - Google Patents
Shared storage convertion device and method for line frame protocol data under broadband CDMA system Download PDFInfo
- Publication number
- CN100446504C CN100446504C CNB2005100710552A CN200510071055A CN100446504C CN 100446504 C CN100446504 C CN 100446504C CN B2005100710552 A CNB2005100710552 A CN B2005100710552A CN 200510071055 A CN200510071055 A CN 200510071055A CN 100446504 C CN100446504 C CN 100446504C
- Authority
- CN
- China
- Prior art keywords
- frame protocol
- data
- protocol data
- parallel
- metadata cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Communication Control (AREA)
Abstract
The present invention relates to a downlink frame protocol data sharing store-and-forward device in a wide band CDMA system and a method thereof. The device comprises a buffer of frame protocol data, which is connected with an interface (1) of a digital signal processor and a frame protocol data reading circuit (3), the frame protocol data reading circuit (3) which is connected with the buffer of frame protocol data and at least a parallel and series connection forwarding circuits (4) and at least a parallel and series connection forwarding circuit which is connected with the frame protocol data reading circuit and an encoder (5), wherein the buffer of frame protocol data is used for caching downlink frame protocol data and can be simultaneously accessed by the digital signal processor and a frame protocol data reading circuit; the frame protocol data reading circuit (3) is used for responding to the reading request of the parallel and series connection forwarding circuits and for reading and transmitting the corresponding data of the buffer of frame protocol data to the parallel and series connection forwarding circuits (4); the parallel and series connection forwarding circuits are used for converting parallel byte data which is sent by the frame protocol data reading circuit to serial data, and the serial data is sent to the parallel and series connection forwarding circuits. The present invention has the achievement of resource sharing among a base station and a plurality of districts, high efficiency and high expandability.
Description
Technical field
The present invention relates to the code division multiple access communication technique field, especially a kind of Wideband Code Division Multiple Access (WCDMA) (WCDMA) system descending Frame Protocol data sharing storing and forwarding device and method.
Background technology
Standard agreement 3GPP TS 25.212 and 25.427 is that WCDMA has stipulated technology such as handling process and data format, but does not also realize at present.In Wideband Code Division Multiple Access (WCDMA) in the prior art (WCDMA) system, radio base station controller interface (NODEB) downlink system need receive the Frame Protocol packet from radio base station interface (Iub), and carries out chnnel coding and modulation.Because the down channel quantity of a NODEB support is very many, the Frame Protocol data volume is very big, the handling property of the effectiveness affects NODEB down channel of the buffer memory of Frame Protocol data and forwarding.Therefore, the mechanism of seeking a kind of effective caching frame protocol data seems extremely important.But prior art exists the processing time-delay bigger, influences the deficiency of the performance of downlink processing.
Summary of the invention
For overcoming the deficiencies in the prior art, the object of the present invention is to provide a kind of broadband CDMA system downlink frame protocol data to share storing and forwarding device, comprise with the lower part:
A kind of broadband CDMA system downlink frame protocol data is shared storing and forwarding device, and this device comprises with the lower part:
One Frame Protocol metadata cache, one end connects digital signal processor interface, the other end connects the Frame Protocol data reading circuit, be used for the downlink frame protocol data that the buffer memory digital signal processor issues, can be simultaneously by the Frame Protocol data reading circuit visit of the digital signal processor interface of prime and back level;
One Frame Protocol data reading circuit, connect Frame Protocol metadata cache and at least one parallel-to-serial converter, be used to respond reading request from back level parallel-to-serial converter, and these requests are ranked, corresponding data are read out from the Frame Protocol metadata cache, pass to parallel-to-serial converter;
At least one parallel-to-serial converter, an end connects the Frame Protocol data reading circuit, and the other end is used for the parallel byte data that the Frame Protocol data reading circuit is sent here is converted to serial data and gives encoder with being connected with its corresponding codes device.
Described parallel-to-serial converter further comprises:
At least one temporary register is used for the Frame Protocol data of a temporary byte;
At least one shift register is used for step-by-step and shifts out the Frame Protocol data that import from temporary register.
The data memory format of described Frame Protocol metadata cache is 25.427 protocol formats.
Described Frame Protocol metadata cache is a twoport dynamic random access memory.
Described Frame Protocol data reading circuit comprises with lower member:
At least one request indicator register, it connects decoder, is used for decoder for decoding is deposited and delivered to the state of the reading request of back level parallel-to-serial converter;
At least one decoder, its connection request indicator register and delay time register is used for the Frame Protocol metadata cache is deciphered and be sent to the reading request of back level parallel-to-serial converter;
Two delay time registers, one is the address byte delay time register, one is the impulse response delay time register, is used for compensated frame protocol data buffer memory and is issued to the time that data are exported from reading the address.
A kind of broadband CDMA system downlink frame protocol data is shared the store and forward mode of storing and forwarding device, and digital signal processor may further comprise the steps from radio base station controller and base-station interface received frame protocol data bag and signaling:
A, digital signal processor interface issue downlink frame protocol data bag, and write in the Frame Protocol metadata cache;
Initial address in all Frame Protocol packets that B, Frame Protocol data reading circuit comprise a link converts the initial address of all transmission channels of link to;
C, parallel-to-serial converter send reading request to the Frame Protocol data reading circuit, and the Frame Protocol data reading circuit is ranked to reading request;
D, Frame Protocol data reading circuit read the Frame Protocol data and send to parallel-to-serial converter from the Frame Protocol metadata cache, the parallel byte data that parallel-to-serial converter will receive sends to the corresponding codes device after converting serial data to.
The bit wide of the Frame Protocol metadata cache in the described steps A is 32 bits.
Frame Protocol metadata cache that data are write in the described steps A further may further comprise the steps:
The time of the Frame Protocol packet that the determination number word signal processor receives is after can writing between the Frame Protocol metadata cache earliest time still, if the Frame Protocol packet time that digital signal processor receives is after the earliest time that can write the Frame Protocol metadata cache, then directly the data that receive are write in the Frame Protocol metadata cache, if the time of the Frame Protocol packet that digital signal processor receives is before can writing Frame Protocol metadata cache earliest time, then it is write in the outer dynamic random access memory of sheet, write again in the Frame Protocol metadata cache after the earliest time that can write the Frame Protocol metadata cache by the time satisfies.
Frame Protocol data in the described Frame Protocol metadata cache are stored according to octet, each transmission block byte-aligned.
The initial address of the Frame Protocol packet among the described step B is that the byte number of having deposited the Frame Protocol packet in the Frame Protocol metadata cache removes the shared byte number of frame head.
All Frame Protocol packets that a link among the described step B comprises can be stored in discontinuous position, address in the Frame Protocol metadata cache.
The initial address of the transmission channel among the described step B is that Frame Protocol data initial address adds this transmission channel byte length of all transmission channels before.
The initial address that all Frame Protocol packet initial addresses that a link is comprised among the described step B convert all transmission channels of link to further may further comprise the steps:
The initial address of B1, Frame Protocol data adds that the byte number that takies when pre-treatment transmission channel all transmission channels before is as the initial address when the pre-treatment transmission channel;
B2, according to cache size to transmission channel initial address delivery.
Parallel-to-serial converter among the described step C sends the reading of data request according to the initial address of transmission channel frame protocol data to the Frame Protocol metadata cache.
When the parallel-to-serial converter among the described step C shifts out bitstream data from Frame Protocol metadata cache shift register, handle, promptly no longer shift out remaining bit number in the shift register if run into a transmission block.
Frame Protocol metadata cache among the described step C adopts priority queueing to the queuing of reading request.
The Frame Protocol data that read from the Frame Protocol metadata cache among the described step D are taked L2 cache mechanism.
Frame Protocol data reading circuit among the described step D reads the Frame Protocol data and further may further comprise the steps from the Frame Protocol metadata cache:
The parallel byte data that parallel-to-serial converter will receive among the described step D sends to the corresponding codes device after converting serial data to, also has a data block Nepit digit counter in the wherein said parallel-to-serial converter, when parallel-to-serial converter is sent to the corresponding codes device with data, if the value of low 3 bits of bit counter is 0, then stop to shift out bit stream, simultaneously with the Frame Protocol data latching in the temporary register in shift register, otherwise continue to shift out bit stream.
The present invention has significant advantage and good effect.
1, digital signal processor (DSP) is from Iub interface received frame protocol data bag and signaling, finishes signaling process and to the parameter configuration of downlink processing chip.Frame Protocol packet for too early arrival carries out buffer memory in the chip external memory of digital signal processor (DSP), the Frame Protocol packet is moved the Frame Protocol data buffer zone of downlink processing chip internal in the appropriate moment, reduced the size of Frame Protocol metadata cache in the chip simultaneously, reduce the integral body time-delay that downlink coding is handled, improved the performance of downlink processing.
2, the data format of Frame Protocol metadata cache as far as possible and agreement be consistent, reduced the complexity of software processes and the time of data-moving, help to support the downlink processing of how little area large-capacity base station.The Frame Protocol metadata cache is supported big end and two kinds of patterns of small end of CPU simultaneously, has made things convenient for various types of central processor CPUs and digital signal processor (DSP) to carry out interface.
3, descending chip is finished the coding and the modulation of each channel, and chip can be supported the coding and the modulation of the down channel of a plurality of sub-districts.Descending chip internal comprises that the Frame Protocol metadata cache reads circuit and parallel-to-serial converter.The Frame Protocol metadata cache is finished the buffer memory of Frame Protocol data, and can respond the Frame Protocol data read request of back level Frame Protocol data reading circuit, reads corresponding byte data process and string conversion and send to encoder from buffering area.It can respond the reading request of back level from the different coding device of different districts or same sub-district, the processing of ranking simultaneously.
The present invention adopts many local resources of downlink frame protocol data buffer memory to share method, and by priority queueing, same cache resources is shared in a plurality of sub-districts.Realized the resource-sharing between a plurality of sub-districts, a base station, utilized monolithic ram in slice on a small scale to support in many sub-districts Frame Protocol metadata cache and processing than multiple downlink.Efficient effectively improves, and has very big extensibility, helps the upgrading of down channel capacity.
Description of drawings
Fig. 1 is a formation picture of device of the present invention;
Fig. 2 is a main flow chart of the present invention;
Fig. 3 is the storage format figure of Frame Protocol metadata cache;
Fig. 4 is a Frame Protocol data Caching Mechanism schematic diagram;
Fig. 5 is and string conversion electrograph;
Fig. 6 is Frame Protocol data reading circuit figure.
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is described.
See also Fig. 1, formation picture of device of the present invention, downlink frame protocol data in Wideband Code Division Multiple Access (WCDMA) (WCDMA) system of the present invention is shared storing and forwarding device, mainly comprise with the lower part: Frame Protocol metadata cache 2, its end linking number word signal processor (DSP) interface, the other end connects Frame Protocol data reading circuit 3, be used for the downlink frame protocol data that buffer memory digital signal processor (DSP) issues, can be simultaneously by Frame Protocol data reading circuit 3 visits of digital signal processor of prime (DSP) and back level; Frame Protocol data reading circuit 3, it connects Frame Protocol metadata cache 2 and at least one parallel-to-serial converter 4, be used to respond reading request from back each parallel-to-serial converter 4 of level, and these requests are ranked, corresponding data are read out from Frame Protocol metadata cache 2, pass to parallel-to-serial converter 4; At least one parallel-to-serial converter 4, as 4, it is identical with encoder 5 quantity, these parallel-to-serial converter 4 one ends connect Frame Protocol data reading circuit 3, the other end is used for the parallel byte data that Frame Protocol data reading circuit 3 is sent here is converted to serial data and gives encoder 5 with being connected with its corresponding codes device 5; At least one encoder 5, encoder 5 is continuous with corresponding parallel-to-serial converter 4, and quantity is identical, is used for the byte data after also string is changed is encoded, and temporary register 6 and shift register 7 are arranged in the parallel-to-serial converter 4.
Usually the data that comprise one or more transmission channels in Frame Protocol packet.In the Frame Protocol packet, the data of each transmission channel are deposited successively, and the data of each transmission channel are according to byte-aligned, the partially filled invalid bit of a byte of less than.
The data of each transmission channel generally include one or more transmission blocks (TB), and the length of each transmission block is equal.Depositing also according to byte-aligned of each transmission block, insufficient section is filled invalid bit.
The present invention reaches and reduces the Frame Protocol data latching and the purpose in processing time for a kind of valid frame protocol data caching mechanism is provided, and finally reaches the purpose that reduces the downlink processing time-delay.Support bigger data throughout with Frame Protocol metadata cache 2 on a small scale as far as possible, can select the capacity of suitable buffer memory 2 in actual applications, realize flexible configuration according to the demand of reality.One buffering area is arranged in the Frame Protocol metadata cache, and buffering area can be shared by same base station different districts, supports under the constant situation of base station total capacity the flexible configuration of different size between each sub-district.Simultaneously, in order to reduce the queuing delay that introduces because of sharing, reduce the negative effect of waiting in line whole encoding process time-delay as far as possible.Queuing treatment mechanism of the present invention can effectively address this problem.
Because the data flow of the input of 212 codings is bit streams of serial, and the data of Frame Protocol packet are deposited by byte, that device of the present invention need be finished parallel data and go here and there conversion process, and go here and there in the translation process, can add the cyclic check code CRC of each transmission block along band.
In device of the present invention, Frame Protocol metadata cache 2 is used for the downlink frame protocol data that buffer memory digital signal processor (DSP) issues, be a Double Port Random Memory, can be simultaneously by prime digital signal processor (DSP) and back level Frame Protocol data reading circuit 3 visits.
Frame Protocol data reading circuit 3 responds the reading request from back each road parallel-to-serial converter 4 of level, and these requests are ranked, and corresponding data are read out from Frame Protocol metadata cache 2, passes to parallel-to-serial converter 4.
Parallel-to-serial converter 4 is finished the also string conversion of byte data, passes to back level encoder 5 modules.Simultaneously, in order to simplify processing, parallel-to-serial converter 4 of the present invention also calculates and safeguards the address of the data read of each transmission channel on the link, and this circuit is finished the conversion of each Frame Protocol packet initial address to each transmission channel initial address.
See also Fig. 2 main flow chart of the present invention, at first, digital signal processor (DSP) is from Iub interface received frame protocol data bag and signaling, and then, digital signal processor (DSP) interface issues downlink frame protocol data bag, and writes in the Frame Protocol metadata cache 2.Frame Protocol metadata cache 2 adopts cycle storage method.Digital signal processor (DSP) safeguards and to begin to write the Frame Protocol packet from this address by a Frame Protocol data address write pointer when needs write the Frame Protocol data, write the Frame Protocol packet after, the value increase Frame Protocol data length of address write pointer.
In the inner data initial address that also needs to safeguard each Frame Protocol data of digital signal processor (DSP), because coding is the data field from the Frame Protocol packet, Frame Protocol data initial address is to remove the shared byte number of frame head.When starting a link coding, the initial address of all Frame Protocol data that this link comprised is disposed to the downlink processing chip, and chip calculates the initial address of each transmission channel frame protocol data in buffering area according to these initial addresses and some relevant parameters.
See also Fig. 3, Frame Protocol data buffering storage format figure, the data format of storing in the Frame Protocol data buffer zone is consistent with the Frame Protocol data format of 25.427 agreements regulation, can save the transfer process of digital signal processor (DSP) to the data form like this.The Frame Protocol packet is that unit stores with 8 bit bytes, comprises frame head territory, data field and verification territory.For downlink coding, generally only use the content of data field.
Because the Frame Protocol deposit data in Frame Protocol metadata cache 2 is by byte-aligned, if the bit wide of Frame Protocol metadata cache 2 is designed to i.e. 8 bits of 1 byte, the addressing system of Frame Protocol data read can be fairly simple, yet such bit wide has influenced the efficient of digital signal processor (DSP) transmission Frame Protocol packet.In order to improve the throughput that digital signal processor (DSP) writes data, need be designed to 32 bits to the bit wide of Frame Protocol metadata cache 2.
The degree of depth of Frame Protocol metadata cache 2 can be adjusted according to the specification such as the number of channel of downlink system support, the present invention is example with 32K, and the Frame Protocol metadata cache 2 of this size approximately can be supported the nothing covering storage of totally 300 channel frame protocol datas of descending 3 sub-districts.Guarantee that the data that write are not covered by new data, must guarantee that it is that encoding process is finished that new data is write the historical data in fashionable corresponding space invalid, this condition is by the degree of depth and the Frame Protocol data write time window common guarantee of Frame Protocol metadata cache 2.Time window is meant the earliest time that the Frame Protocol data can write, if the Frame Protocol packet that digital signal processor (DSP) receives from Iub interface is early than this time, then earlier it is left in the chip external memory, the equal time window writes in the Frame Protocol metadata cache 2 of descending chip after satisfying again; If the Frame Protocol packet that digital signal processor (DSP) receives within time window, can directly be moved the packet that receives in the Frame Protocol metadata cache 2 of chip internal to.Time window of the present invention is arranged to 10 milliseconds (ms), if the Frame Protocol data are early than 10ms the time of advent, earlier the sheet external space of Frame Protocol deposit data, satisfy the Frame Protocol metadata cache 2 that again data-moving is arrived descending chip behind the time window by the time at digital signal processor (DSP); If the Frame Protocol data time of advent within 10ms, can be directly the Frame Protocol data-moving in the Frame Protocol metadata cache 2 of descending chip.
As shown in Figure 4, this memory mechanism is to the not constraint of memory location of each Frame Protocol data, and the different frame protocol data of a link can be stored in the diverse location of Frame Protocol metadata cache 2, and the address needn't be continuous.Buffer memory for the Frame Protocol data is very favorable like this, because be unordered at random the time of advent of Frame Protocol data, each Frame Protocol packet that link comprises may arrive at different time, digital signal processor (DSP) does not need extraly the Frame Protocol packet to be carried out buffer memory in time window, so both reduce the time of data-moving, reduced the load that digital signal processor (DSP) increases because of the Frame Protocol data processing again.
Afterwards, the initial address in Frame Protocol data reading circuit 3 all Frame Protocol packets that a link is comprised converts the initial address of all transmission channels of link to.The target of address transition is to want to find the data that are stored in each bit in the Frame Protocol metadata cache 2.Address transition mechanism is shared Frame Protocol metadata cache 2 with many sub-districts odd encoder device 5, data format and the Frame Protocol metadata cache mechanism of Frame Protocol data in Frame Protocol metadata cache 2 is relevant.Address transition will be considered the response efficiency of the efficient and the back level Frame Protocol data read request of prime data-moving.
Address transition of the present invention is divided into 3 steps:
1, the conversion of all transmission channel initial addresses of initial address to a link of all Frame Protocol data of comprising of link.
As previously mentioned, digital signal processor (DSP) is the initial address of each Frame Protocol packet internal maintenance, because digital signal processor (DSP) only is concerned about moving of Frame Protocol packet, be indifferent to the processing of a link internal transmission channel, and when link is encoded, carry out according to each transmission channel, need finish of the conversion of Frame Protocol packet initial address to each transmission channel initial address.
A Frame Protocol packet inside has the Frame Protocol data of one or more transmission channels, support 8 transmission channels as maximum, the data of the transmission channel that link comprises may be carried on one or more Frame Protocol data, as comprising 8 transmission channels at most.The corresponding relation of Frame Protocol data initial address and transmission channel initial address is relatively complicated like this.
The carrying several transport is determined when link establishment in certain Frame Protocol data, which Frame Protocol data same certain link comprises and comprise several transport determines when link establishment that also these parameters are as can be known for digital signal processor (DSP).The parameter that address transition need be used mainly contains: be addressed to the number of the transmission channel that the transmission channel number of initial address, each Frame Protocol Data-carrying of each Frame Protocol data of byte, link comprise, the transformat that each transmission channel current transmission time interval (TTI) is used, comprise transmission block number (tb_num) and transmission block size (tb_len).
The form that the Frame Protocol data define in agreement is stored according to byte (8bit), each transmission block is a byte-aligned, this means that if the data length of a transmission block is not the i.e. integral multiple of 8 bits of integral multiple of byte then need to fill VB vacancy bit, polishing is to the integral multiple of byte.So the byte number that transmission channel takies is [tb_len/8] * tb_num.Wherein [] is for rounding up.
The initial address of first transmission channel is exactly the initial address of Frame Protocol data in the Frame Protocol data; The initial address of second transmission channel is: the initial address of Frame Protocol data+1st byte number that transmission channel takies; The initial address of the 3rd transmission channel is: the initial address of the 1st transmission channel+2nd byte number that transmission channel takies; ....When calculating the transmission channel initial address, want the size of considered frame protocol data buffer memory 2, need carry out the big or small delivery of protocol data buffer memory 2 frame by frame to operation result, if the result who promptly calculates greater than the size of Frame Protocol metadata cache 2, need deduct the size of Frame Protocol metadata cache 2 to the result.
The order of transmission channel address computation is to calculate the initial address of first transmission channel earlier, calculates the initial address of the 2nd transmission channel again, all calculates up to 1 all transmission channel initial address of link and finishes.
2, the address maintenance of inner each byte of transmission channel.
After address computation was finished, parallel-to-serial converter 4 sent reading request to Frame Protocol data reading circuit 3, and 3 pairs of reading request of Frame Protocol data reading circuit are ranked.Parallel-to-serial converter 4 reads a byte by Frame Protocol data reading circuit 3 at every turn from Frame Protocol metadata cache 2 data are carried out and go here and theres conversion, finish after converting next byte and go here and there and change.For the ease of the control of flow in the whole encoding process process, the Frame Protocol data read adopts and initiatively initiates reading request by parallel-to-serial converter 4, the mechanism of Frame Protocol data reading circuit 3 response request.
When carrying out transmission channel coding, parallel-to-serial converter 4 at first sends the request of reading of first byte data to the prime module according to the initial address of this transmission channel frame protocol data.Whenever after sending the request of a byte, the address increases by 1.When running into a transmission block and finish dealing with, abandon shift register 7 inner remaining bits in the parallel-to-serial converter 4, send the single reading request again.Processing has just met a requirement that transmission block is stored by byte-aligned in buffer memory 2 like this.
3, to the visit of each bit of byte inner.
Next, Frame Protocol data reading circuit 3 reads the Frame Protocol data and sends to parallel-to-serial converter 4 from Frame Protocol metadata cache 2.Visit to each bit of byte inner does not need to safeguard separately the address, in parallel-to-serial converter 4 from eight bit shift register 7 successively output bit flow get final product.The highest order of each Output Shift Register 7, and shift register 7 done shift left operation.Finish if run into a transmission block processing, the remaining bits in the shift register 7 is abandoned, and these bits just in time are the invalid bits that is used for each transmission block alignment in Frame Protocol metadata cache 2, does not need to pass to back level encoding process.
Send the Frame Protocol data read request from parallel-to-serial converter 4 and be issued to and meet with a response, need the time-delay of several clocks.If do not take special processing, parallel-to-serial converter 4 needs to insert extra latent period after whenever handling the data of a byte, just can carry out after reading request meets with a response by the time next byte and go here and there conversion process.Inserting extra latent period can increase the time-delay of whole encoding process, influences the performance of whole downlink processing.Send request simultaneously as a plurality of encoders 5 in a plurality of sub-districts under abominable situation, may make the processing time-delay of whole coding increase by 1 times, this time-delay is that the downlink processing system is unacceptable.Therefore, needs adopt special method to guarantee and go here and there and change the continuous transmission of data flow afterwards.
As shown in Figure 5, in order to reduce because extra latent period is inserted in Frame Protocol data readings time-delay, and the Frame Protocol data read is taked L2 cache mechanism, be in advance and the Frame Protocol data of what a byte of string conversion preparation.Request is once read in every transmission, just from 2 li data that read a byte of Frame Protocol metadata cache of prime.The Frame Protocol data latching that reads is in temporary register 6.After encoding process starts, as long as when finding that temporary register 6 be sky, will send the single reading request, in temporary register 6, depositing and do not carrying out and go here and there till the data converted.The shift register 7 of parallel-to-serial converter 4 is whenever finished after the processing of a byte the data latching in the temporary register 6 in shift register 7.Certainly need judge in latch data whether what deposit in the temporary register 6 is the number of a renewal, if not, need to wait for post temporary register 6 Data Update after, promptly reading request meets with a response, again data latching.This probability that wait for to take place is very little, and only after first reading request is sent, the data of back can be got up automatically continuously usually, and temporary register 6 can be sent out reading request and new data more in advance, for next byte and string conversion are ready to data.The address of each reading request is that this result also needs the size of Frame Protocol metadata cache 2 is carried out delivery with the initial address fp_beg_addr of transmission channel and the result of the current number req_cnt addition that meets with a response.
In the parallel-to-serial converter 4 of Fig. 5, count the bit of handling in the transmission block with a bit counter parallel-to-serial converter 4 inside.When the value of low 3 bits of bit counter is 0, promptly needing to upgrade shift register 7 the shift register 7 of the data latching in the temporary register 6 to 8 bits, simultaneously to the sign zero clearing of temporary register 6, the data of this expression temporary register 6 are removed, no data updated.Will send a reading request pulse when temporary register 6 is masked as sky, the address of reading request is the value that the initial address of transmission channel adds byte counter.When receiving reading request when response, byte counter adds 1, simultaneously data latching in temporary register 6, and the sign of set temporary register 6, these expression data are upgraded.After a transmission block is finished dealing with, next transmission block is handled, before handling, need bit counter is carried out zero clearing.After the bit counter zero clearing,, just abandon, because these data are the invalid datas that are used for the transmission block byte-aligned if exist remaining data not send in the shift register 7.
Because Frame Protocol metadata cache 2 is shared by a plurality of coding processing unit, it for certain coding unit non-exclusive resource, the Frame Protocol data read module needs to handle the reading request that back level multichannel processing module is sent simultaneously, and the queuing of multichannel request and response mechanism can influence the time-delay of whole downlink processing.If it is long to be issued to the time that meets with a response from request, may cause the increase of whole downlink processing time-delay.
The key problem of Frame Protocol data reading circuit 3 is the multichannel reading request that how to respond the back level, and its main circuit is a queue circuit.General queue circuit has two kinds: 1, priority queueing; 2, repeating query queuing.Because repeating query queuing needs to insert certain wait umber of beats, and request can not in time be handled, so, under the few situation of request way as 8 the tunnel with the interior priority queuing mechanism that then adopts.If back level encoder 5 numbers are more, in order to reduce the correlation of each coding processing unit, processing delay performance each other is unaffected, can consider to adopt the repeating query queuing mechanism.
Adopting a secondary face effect of priority queueing is if exist other path of high priority to send request always, and other path of low priority may can not get response forever.But do not have such problem in the present invention, need 8 cycles to finish data processing because back level parallel-to-serial converter 4 whenever obtains a secondary response, the interval of twice reading request is generally 8 and claps.So do not exist the path of high priority to take the situation of Frame Protocol data readings circuit always.
It is example that the present invention shares a Frame Protocol metadata cache 2 with the corresponding 4 cover parallel-to-serial converters 4 of 4 cover coding processing unit, and the implementation method that adopts priority queueing is described.The Frame Protocol data read request of Frame Protocol data read module response 4 cover parallel-to-serial converters 4, reading corresponding data offers parallel-to-serial converter 4 from Frame Protocol metadata cache 2.Owing to may exist 4 parallel-to-serial converters 4 to send the situation of Frame Protocol data read request simultaneously, therefore need rank to 4 requests in Frame Protocol data read module inside, respond the request that each parallel-to-serial converter 4 sends successively.
Each response frame protocol data request of reading will be read a byte from Frame Protocol metadata cache 2 data send to parallel-to-serial converter 4.Frame association data view buffer memory 2 for 32 bit bit wides, according to the word addressing, therefore, higher bit with request address, remove low 2 bits bit in addition as the address, at first from Frame Protocol metadata cache 2, read the data of a word, from 1 word, select the content of 1 byte to send to parallel-to-serial converter 4 according to low 2 bits of request address then.For the large and small end pattern of supporting that CPU is different, when selecting, byte can handle accordingly according to different patterns.If be little endian mode, byte is since the low level of a word, and promptly byte address is 0,1,2,3 to select 7～0 bits, 15～8 bits, 23～16 bits and 31～24 bits in the word respectively.If be big end pattern, the order of preference of byte need be put upside down, and byte is selected the high position from word, and promptly byte address is 0,1,2,3 to select 31～24 bits, 23～16 bits, 15～8 bits and 7～0 bits in the word respectively.
See also Fig. 6, the queue circuit figure in the Frame Protocol data read of the present invention.In the figure, the present invention is provided with 4 indicator registers and deposits the state of 4 tunnel requests respectively, when receiving request, and register set, when the request of corresponding path meets with a response, the register zero clearing.The sign of each road indicator register is delivered to decoder and is carried out priority decoding.When the first via be masked as 1 the time, the request of the decoding response first via; When the second the tunnel be masked as 1 the time and last road when not asking, respond the second tunnel request; ....If the request of a certain road meets with a response, Frame Protocol data readings circuit can be selected the address of reading of corresponding path, and with the high position of this address carry out Frame Protocol metadata cache 2 by the word addressing, carry out byte with low 2 and select.Carry out that byte is selected and the output response impulse in to consider the flowing water umber of beats of reading buffer memory 2, the delay time register among the figure is exactly to clap as 2 from the flowing water of reading the address and being issued to data output in order to compensate buffer memory 2.
At last, parallel-to-serial converter 4 is sent to each channel encoder 5 with the data serial that reads.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (18)
1, a kind of broadband CDMA system downlink frame protocol data is shared storing and forwarding device, it is characterized in that this device comprises with the lower part:
One Frame Protocol metadata cache, one end connects digital signal processor interface, the other end connects the Frame Protocol data reading circuit, be used for the downlink frame protocol data that the buffer memory digital signal processor issues, can be simultaneously by the Frame Protocol data reading circuit visit of the digital signal processor interface of prime and back level;
One Frame Protocol data reading circuit, connect Frame Protocol metadata cache and at least one parallel-to-serial converter, be used to respond reading request from back level parallel-to-serial converter, and these requests are ranked, corresponding data are read out from the Frame Protocol metadata cache, pass to parallel-to-serial converter;
At least one parallel-to-serial converter, an end connects the Frame Protocol data reading circuit, and the other end is used for the parallel byte data that the Frame Protocol data reading circuit is sent here is converted to serial data and gives encoder with being connected with its corresponding codes device.
2, device as claimed in claim 1 is characterized in that, described parallel-to-serial converter further comprises:
At least one temporary register is used for the Frame Protocol data of a temporary byte;
At least one shift register is used for step-by-step and shifts out the Frame Protocol data that import from temporary register.
3, device as claimed in claim 1 is characterized in that, the data memory format of described Frame Protocol metadata cache is 25.427 protocol formats.
4, device as claimed in claim 1 is characterized in that, described Frame Protocol metadata cache is a twoport dynamic random access memory.
5, device as claimed in claim 1 is characterized in that, described Frame Protocol data reading circuit comprises with lower member:
At least one request indicator register, it connects decoder, is used for decoder for decoding is deposited and delivered to the state of the reading request of back level parallel-to-serial converter;
At least one decoder, its connection request indicator register and delay time register is used for the Frame Protocol metadata cache is deciphered and be sent to the reading request of back level parallel-to-serial converter;
Two delay time registers, one is the address byte delay time register, one is the impulse response delay time register, is used for compensated frame protocol data buffer memory and is issued to the time that data are exported from reading the address.
6, a kind of broadband CDMA system downlink frame protocol data is shared the store and forward mode of storing and forwarding device, digital signal processor is from radio base station controller and base-station interface received frame protocol data bag and signaling, it is characterized in that this method may further comprise the steps:
A, digital signal processor interface issue downlink frame protocol data bag, and write in the Frame Protocol metadata cache;
Initial address in all Frame Protocol packets that B, Frame Protocol data reading circuit comprise a link converts the initial address of all transmission channels of link to;
C, parallel-to-serial converter send reading request to the Frame Protocol data reading circuit, and the Frame Protocol data reading circuit is ranked to reading request;
D, Frame Protocol data reading circuit read the Frame Protocol data and send to parallel-to-serial converter from the Frame Protocol metadata cache, the parallel byte data that parallel-to-serial converter will receive sends to the corresponding codes device after converting serial data to.
7, method as claimed in claim 6 is characterized in that, the bit wide of the Frame Protocol metadata cache in the described steps A is 32 bits.
8, method as claimed in claim 6 is characterized in that, the Frame Protocol metadata cache that data are write in the described steps A further may further comprise the steps:
The time of the Frame Protocol packet that the determination number word signal processor receives before the earliest time that can write the Frame Protocol metadata cache still after, if the Frame Protocol packet time that digital signal processor receives is after the earliest time that can write the Frame Protocol metadata cache, then directly the data that receive are write in the Frame Protocol metadata cache, if the time of the Frame Protocol packet that digital signal processor receives is before can writing Frame Protocol metadata cache earliest time, then it is write in the outer dynamic random access memory of sheet, in the Frame Protocol metadata cache that writes again after the earliest time that can write the Frame Protocol metadata cache by the time satisfies.
9, method as claimed in claim 8 is characterized in that, the Frame Protocol data in the described Frame Protocol metadata cache are stored according to octet, each transmission block byte-aligned.
10, method as claimed in claim 6 is characterized in that, the initial address of the Frame Protocol packet among the described step B is that the shared byte number of having deposited the Frame Protocol packet in the Frame Protocol metadata cache removes the shared byte number of frame head.
11, method as claimed in claim 6 is characterized in that, all Frame Protocol packets that a link among the described step B comprises can be stored in discontinuous position, address in the Frame Protocol metadata cache.
12, method as claimed in claim 6 is characterized in that, the initial address of the transmission channel among the described step B is that Frame Protocol data initial address adds this transmission channel byte length of all transmission channels before.
13, method as claimed in claim 6 is characterized in that, the initial address in all the Frame Protocol packets that a link is comprised among the step B converts the initial address of all transmission channels of link to, comprising:
The initial address of B1, Frame Protocol packet adds that byte number that all transmission channels before the transmission channel when pre-treatment take is as the initial address when the transmission channel of pre-treatment;
B2, according to cache size to transmission channel initial address delivery.
14, method as claimed in claim 6 is characterized in that, the parallel-to-serial converter among the described step C sends the reading of data request according to the initial address of transmission channel frame protocol data to the Frame Protocol metadata cache.
15, method as claimed in claim 14, it is characterized in that, when the parallel-to-serial converter among the described step C shifts out bitstream data from Frame Protocol metadata cache shift register, handle, promptly no longer shift out remaining bit number in the shift register if run into a transmission block.
16, method as claimed in claim 6 is characterized in that, the Frame Protocol metadata cache among the described step C adopts priority queueing to the queuing of reading request.
17, method as claimed in claim 6 is characterized in that, the Frame Protocol data that read from the Frame Protocol metadata cache among the described step D are taked L2 cache mechanism.
18, method as claimed in claim 6, it is characterized in that, the parallel byte data that parallel-to-serial converter will receive among the described step D sends to the corresponding codes device after converting serial data to, also has a data block Nepit digit counter in the wherein said parallel-to-serial converter, when parallel-to-serial converter is sent to the corresponding codes device with data, if the value of low 3 bits of described bit counter is 0, then stop to shift out bit stream, simultaneously with the Frame Protocol data latching in the temporary register in shift register, otherwise continue to shift out bit stream.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100710552A CN100446504C (en) | 2005-05-23 | 2005-05-23 | Shared storage convertion device and method for line frame protocol data under broadband CDMA system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100710552A CN100446504C (en) | 2005-05-23 | 2005-05-23 | Shared storage convertion device and method for line frame protocol data under broadband CDMA system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1870565A CN1870565A (en) | 2006-11-29 |
| CN100446504C true CN100446504C (en) | 2008-12-24 |
Family
ID=37444117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100710552A Expired - Fee Related CN100446504C (en) | 2005-05-23 | 2005-05-23 | Shared storage convertion device and method for line frame protocol data under broadband CDMA system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100446504C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467562A (en) * | 2010-11-19 | 2012-05-23 | 金蝶软件（中国）有限公司 | Computer document input method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1291747A (en) * | 2000-11-24 | 2001-04-18 | 李楠甍 | Cache device and its application |
| CN1360444A (en) * | 2000-12-22 | 2002-07-24 | 西门子信息通讯网络公司 | Procedure for dispatching packet data sending permit on mobile station shared radio telecommunication channel |
| CN1407768A (en) * | 2001-09-02 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Device and method for group continuous transfer of multi-team data |
| WO2003073296A2 (en) * | 2002-02-27 | 2003-09-04 | Koninklijke Philips Electronics N.V. | Shared queue for multiple input-streams |
| CN1567849A (en) * | 2003-06-25 | 2005-01-19 | 华为技术有限公司 | A real time flow buffering and jitter eliminating method for decreasing additive time delay |
-
2005
- 2005-05-23 CN CNB2005100710552A patent/CN100446504C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1291747A (en) * | 2000-11-24 | 2001-04-18 | 李楠甍 | Cache device and its application |
| CN1360444A (en) * | 2000-12-22 | 2002-07-24 | 西门子信息通讯网络公司 | Procedure for dispatching packet data sending permit on mobile station shared radio telecommunication channel |
| CN1407768A (en) * | 2001-09-02 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Device and method for group continuous transfer of multi-team data |
| WO2003073296A2 (en) * | 2002-02-27 | 2003-09-04 | Koninklijke Philips Electronics N.V. | Shared queue for multiple input-streams |
| CN1567849A (en) * | 2003-06-25 | 2005-01-19 | 华为技术有限公司 | A real time flow buffering and jitter eliminating method for decreasing additive time delay |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1870565A (en) | 2006-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7751404B2 (en) | Method, system, and computer program product for high performance bonding resequencing | |
| US8352628B2 (en) | Method for transferring data from a source target to a destination target, and corresponding network interface | |
| US8627189B2 (en) | High performance digital signal processing in software radios | |
| US8934890B2 (en) | Transmission of data bursts on a constant data rate channel | |
| US20030133465A1 (en) | System for reordering sequenced based packets in a switching network | |
| US20040151177A1 (en) | Device to receive, buffer, and transmit packets of data in a packet switching network | |
| US7464201B1 (en) | Packet buffer management apparatus and method | |
| WO2021208734A1 (en) | Data transmission method of serial bus and communication device | |
| US20140344485A1 (en) | Communication system for interfacing a plurality of transmission circuits with an interconnection network, and corresponding integrated circuit | |
| JP2003037572A (en) | Scheduling system | |
| WO2021208733A1 (en) | Data transmission method of serial bus, and communication device | |
| CN116708579B (en) | Data access method, device, electronic equipment and computer readable storage medium | |
| CN105071859A (en) | Downlink and uplink data transmission method and apparatus | |
| CN101631327B (en) | Method for sending and receiving microwave business data, device thereof and transceiver system | |
| CN101848239A (en) | High-timeliness distributed service integration calling system | |
| WO2006098763A2 (en) | Intelligent memory interface | |
| CN100591067C (en) | A method for realizing SDH adaptation to Ethernet rate with logic | |
| CN100446504C (en) | Shared storage convertion device and method for line frame protocol data under broadband CDMA system | |
| CN101764797B (en) | Time division multi-channel LAPD processor and designing method thereof | |
| US20040151175A1 (en) | Transparent data format within host device supporting differing transaction types | |
| Chiueh et al. | Suez: A cluster-based scalable real-time packet router | |
| CN102164095B (en) | Datagram segmentation and reassembly system and realization method for onboard switching module | |
| CN106330413B (en) | Method and system for controlling packet loss of 2.4G wireless audio transmission | |
| WO2021063214A1 (en) | Data transmission method and apparatus | |
| CN103389962A (en) | CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081224 Termination date: 20150523 |
|
| EXPY | Termination of patent right or utility model |