WO2021208733A1

WO2021208733A1 - Data transmission method of serial bus, and communication device

Info

Publication number: WO2021208733A1
Application number: PCT/CN2021/084217
Authority: WO
Inventors: 冀晋
Original assignee: 展讯通信（上海）有限公司
Priority date: 2020-04-17
Filing date: 2021-03-31
Publication date: 2021-10-21
Also published as: CN111427832B; CN111427832A

Abstract

A data transmission method of a serial bus, and a communication device. The method comprises: acquiring data to be transmitted, and packaging the data into at least one data packet, the data length of the data packet being configurable, and the data packet comprising a length indication field and at least one data packet unit, wherein the length indication field is used for indicating the quantity of data packet units; and transmitting the at least one data packet by using the serial bus. By means of the solution provided in the present invention, low-delay and high-reliability data transmission can be better realized, data transmission efficiency is higher, and additional expenditure is less.

Description

A serial bus data transmission method and communication device

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 17, 2020, the application number is 2020103071911, and the invention title is "a serial bus data transmission method and communication device", the entire content of which is incorporated by reference In this application.

Technical field

The present invention relates to the field of communication technology, in particular to a serial bus data transmission method and communication device.

Background technique

Existing high-speed transmission technologies generally use 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. In addition, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standards (Peripheral Component Interconnect Express, PCI Express for short, also known as PCIE) and USB packaging are more complicated.

The above two problems result in that the existing data transmission mode cannot meet the requirements of the communication device for low delay and high reliability.

On the other hand, in order to meet the diverse needs of users, mobile phones and other communication devices have gradually expanded their diversified functions such as camera and games in addition to the call function. These applications can be controlled and implemented based on independent systems.

Therefore, for a communication device that can implement multiple applications, it usually has at least two integrated circuit chips, one of which is a modem (modem), which is used to implement cellular communication functions, and can be understood as a communication system; the other chip is application processing Application Processor (AP for short) is used to implement functions such as shooting, display, 2D/3D engine, etc., and can be understood as an application processing system.

Generally speaking, if a system requires large-capacity, high-bandwidth, and low-latency memory access, the system needs to be equipped with an independent off-chip memory. Taking a communication device as an example, a modem and an application processor are usually paired with an off-chip memory. This causes the communication device to have multiple off-chip memories at the same time, leading to an increase in overall cost. In addition, too much off-chip memory will also increase the area of a printed circuit board (PCB) that integrates various systems, which is not conducive to the miniaturization of communication devices.

If multiple systems are to share off-chip memory, the requirements for low latency, high reliability, and high bandwidth of data transmission are more stringent, and the existing data transmission mode is obviously unable to meet.

Summary of the invention

The technical problem solved by the present invention is how to better realize data transmission with low time delay and high reliability.

To solve the above technical problems, an embodiment of the present invention provides a serial bus data transmission method, including: acquiring data to be transmitted, and packing the data into at least one data packet, the data length of the data packet is optional Configured, the data packet includes a length indication field and at least one data packet unit, and the length indication field is used to indicate the number of the data packet unit; the at least one data packet is transmitted by using the serial bus.

Optionally, the data to be transmitted comes from multiple data sources, wherein at least one data packet unit in the same data packet comes from the same data source, and data packet units in different data packets come from different data sources.

Optionally, the data packet further includes: a packet header, which is used to carry transmission information of the data packet; and a packet body, which is used to carry the at least one data packet unit.

Optionally, the packet header includes: a channel identification field, which is used to indicate a channel for transmitting the data packet; and a CC indication field, which is used to support flow control.

Optionally, the data packet includes a plurality of transmission blocks, wherein each transmission block includes a payload and an error correction code, and the payload carries at least a part of the at least one data packet unit.

Optionally, the error correction code is an ECC error correction code.

Optionally, the data length of each transmission block is 128 bits, wherein the data length of the payload is 119 bits, and the data length of the error correction code is 9 bits.

Optionally, the data length of each data packet unit in the data packet is determined by a configuration register.

In order to solve the above technical problem, an embodiment of the present invention also provides a serial bus data transmission method, including: using the serial bus to receive at least one data packet, the data length of the data packet is configurable, the The data packet includes a length indication field and at least one data packet unit, where the length indication field is used to indicate the number of the data packet unit; the received at least one data packet is unpacked to obtain the transmitted data.

Optionally, the data packet includes a plurality of transmission blocks, wherein each transmission block includes a payload and an ECC error correction code, the payload carries at least a part of the at least one data packet unit, and the unpacking receives The at least one data packet received to obtain the transmitted data includes: for each transmission block in each data packet, calibrating the data contained in the transmission block based on the ECC error correction code in the transmission block Check; if the check result is a one-bit error, then the error is corrected; if the check result is an error greater than one bit, it is reported to the upper layer.

To solve the above technical problem, an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage Module, the modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein the modem and the application processor use the above-mentioned data transmission method for data transmission .

Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

The embodiment of the present invention provides a data transmission method of a serial bus, including: obtaining data to be transmitted, and packing the data into at least one data packet, the data length of the data packet is configurable, and the data The packet includes a length indication field and at least one data packet unit, where the length indication field is used to indicate the number of the data packet unit; the at least one data packet is transmitted using the serial bus.

The solution of this embodiment adopts a simple packaging method to minimize additional expenditure. Specifically, the solution of this embodiment adopts a data packet with a variable data length, which can maximize the data transmission efficiency. The data sending end can pack as much data as possible in a data packet, making it possible to balance efficiency and implementation.

Further, an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage module, the The modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein, the modem and the application processor use the above-mentioned data transmission method for data transmission.

The solution of this embodiment provides an improved communication device, which enables multiple systems with large-capacity, high-bandwidth, and low-latency memory access requirements to share the same physical memory, which helps reduce overall costs and improve system competitiveness. Specifically, the shared storage module is hung under the application processor, the application processor can directly access the shared storage module, and the modem indirectly accesses the shared storage module through the application processor. As a result, multiple large-capacity, high-bandwidth, low-latency systems can share an off-chip physical memory. Furthermore, through a specially designed data packet format and corresponding packing/unpacking methods, the delay of data transmission is reduced to a range acceptable to the modem, which makes it possible to improve data transmission efficiency and bandwidth, which is beneficial to better reduce delay.

Description of the drawings

FIG. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention;

2 is a flowchart of a first serial bus data transmission method according to an embodiment of the present invention;

Figure 3 is a schematic diagram of the structure of the short packet in Figure 2;

Figure 4 is a schematic diagram of the structure of the long bag in Figure 2;

5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention;

Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the structure of the data packet in FIG. 6;

8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention;

Fig. 9 is a schematic diagram of the principle of a modem according to an embodiment of the present invention.

Detailed ways

As mentioned in the background art, each system of the existing communication device is independently configured with off-chip physical memory, the overall cost is high, and the PCB area is large, which is not conducive to miniaturization.

Although the prior art also has a solution based on dual-port memory (memory) to realize shared memory. However, the interface of dual-port memory is mainly parallel, and the speed is usually not high. The maximum bandwidth that the existing dual-port memory can provide is about 6.4Gbps, which is far lower than the requirements of systems that require large-capacity, high-bandwidth, and low-latency memory access. Generally speaking, high bandwidth means that the bandwidth requirement of the system to access the off-chip physical memory is above 16Gbps; low latency means that the system access to the off-chip physical memory requires a delay of less than 1000ns.

The inventor of the present application found through analysis that the existing high-speed transmission technology generally uses 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. On the other hand, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI Express, also known as PCIE) and USB packaging are more complicated.

In order to make the above objectives, features and beneficial effects of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention.

The communication device may be a user equipment such as a mobile phone.

Specifically, referring to FIG. 1, the communication device 1 described in this embodiment may include: an application processor 11; a modem 12; and a shared storage module 13. The application processor 11 is coupled to the shared storage module 13 and can directly To access the shared memory module 13, the modem 12 is coupled to the application processor 11 and indirectly accesses the shared memory 13 through the application processor 11.

Wherein, directness can be relative to indirectness, that is, the data access of the application processor 11 to the shared memory module 13 does not need to be transferred through other systems, while the data access of the modem 12 to the shared memory module 13 needs to pass through other systems. (Such as application processor 11) transit.

It should be pointed out that the direct access described in this embodiment does not mean that the application processor 11 and the shared storage module 13 are directly connected by a data line. In actual applications, the application processor 11 and the shared storage module 13 may be connected through an interface or the like. At this time, it can also be considered that the application processor 11 directly accesses the shared storage module 13.

In a specific implementation, the application processor 11 may include: a storage control unit 111, the storage control unit 111 communicates with the shared storage module 13, and the storage control unit 111 may be configured to receive the modem 12 And access the shared storage module 13 according to the access request.

Further, the storage control unit 111 may also be used to feed back the access result of the shared storage module 13 to the modem 12.

For example, the data transmission in the application processor 11 is performed based on the first bus (bus) 112, and the data transmission in the modem 12 is performed based on the second bus 121. The standard data format used for data transmission on the first bus 112 and the standard data format used for data transmission on the second bus 121 may be the same or different. The application processor 11 and the modem 12 can each use a data transmission protocol specified by an existing protocol for data transmission.

The first bus 112 can be understood as a common channel in the application processor 11. Similarly, the second bus 121 can be understood as a common channel in the modem 12.

Further, data transmission between the storage control unit 111 and the shared storage module 13 can also be based on a bus, and the standard data format used for data transmission is the same as the standard data format used for data transmission on the first bus 112. The standard data format used for data transmission on the second bus 121 may be the same or different.

Further, the application processor 11 may include a first processing module (Processor) 113, and the first processing module 113 may access the shared storage module 13 through the first bus 112 and the storage control unit 111 according to system operation requirements.

Further, the modem 12 may include a second processing module 122, and the second processing module 122 may send an access request through the second bus 121 to request access to the shared storage module 13 according to the needs of system operation. The access request is transmitted to the first bus 112 through the coupling relationship between the modem 12 and the application processor 11, and then sent to the shared storage module 13 through the storage control unit 111.

Next, the coupling relationship between the modem 12 and the application processor 11 and the corresponding data transmission mode will be described in detail.

In a specific implementation, the application processor 11 and the modem 12 can communicate with each other through a serial bus 14. Specifically, the serial bus 14 adopts a private data format when transmitting data, and the private data format is different from the aforementioned first bus 112, second bus 121, and the storage control unit 111 and the shared storage module 13. The said standard data format.

Thus, through a specially designed data packet format and corresponding packing/unpacking methods, the delay of data transmission is reduced to the acceptable range of the modem 12, which makes it possible to improve the data transmission efficiency and bandwidth, which is beneficial to better reduce the delay.

For example, referring to FIG. 1, the application processor 11 and the modem 12 respectively include an interface unit (link). For ease of distinction, the interface unit of the application processor 11 is marked as the first interface unit 114, and the interface unit of the modem 12 is marked as As the second interface unit 123.

The first interface unit 114 and the second interface unit 123 are used to connect to the serial bus 14 and convert the data format of the data between the private data format and the respective standard data format of the application processor 11 and the modem 12.

In a typical application scenario, the second processing module 122 initiates a read command, and the read command is sequentially transmitted to the storage control unit through the second bus 121, the serial bus 14, the first interface unit 114, and the first bus 112. 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.

When the shared storage module 13 feeds back the data pointed to by the read command, the data is gradually transferred to the second processing module 122 via the reverse path of the aforementioned path.

During the transmission process, when the data is transmitted to the first interface unit 114, the first interface unit 114 may change the data format of each data packet in the data from the data format adopted by the application processor 11 The standard data format is converted to the private data format adopted by the serial bus 14. Then it is transmitted to the second interface unit 123 via the serial bus 14.

In response to receiving the data based on the private data format, the second interface unit 123 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the modem 12. Then, it is transmitted to the second processing module 122 through the second bus 121.

In another typical application scenario, the second processing module 122 initiates a write command, and the write command and the data to be written into the shared memory module 13 sequentially pass through the second bus 121, the serial bus 14, the first interface unit 114, The first bus 112 is transmitted to the storage control unit 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.

During the transmission process, when the data is transmitted to the second interface unit 123, the second interface unit 123 can convert the data format of each data packet in the data from the standard data format adopted by the modem 12 To the private data format used by the serial bus 14. Then, it is transmitted to the first interface unit 114 via the serial bus 14.

In response to receiving the data based on the private data format, the first interface unit 114 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the application processor 11. Then, it is transferred to the storage control unit 111 through the first bus 112 for data writing.

In a specific implementation, the shared memory module 13 may be a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM for short, or DDR for short).

The data transmitted by the serial bus 14 can be packaged into at least one data packet. Next, several different data transmission processes of the serial bus 14 will be described in detail.

In a specific implementation, referring to FIG. 2, the first data transmission method of the serial bus 14 in the embodiment of the present invention may include the following steps:

Step S101: Obtain data to be transmitted, and pack the data into at least one data packet, the data packet being a long packet or a short packet, and the long packet and the short packet have different data lengths;

Step S102: Use the serial bus to transmit the at least one data packet.

Specifically, with reference to FIG. 1, when the data to be transmitted is transmitted from the first interface unit 114 to the second interface unit 123, the steps S101 and S102 may be executed by the first interface unit 114. Conversely, when the data to be transmitted is transmitted by the second interface unit 123 to the first interface unit 114, the steps S101 and S102 may be executed by the second interface unit 123.

Further, the at least one data packet may be all long packets, or all short packets, or a combination of long packets and short packets. In practical applications, long packets and/or short packets can be flexibly selected according to the size of the data to be transmitted to obtain the at least one data packet.

In a specific implementation, the data length of the payload in the short packet may be determined according to the width of a single data transmitted by the serial bus 14.

Specifically, the width of the single data may be the width of most single data transmitted on the serial bus 14.

In response to the aforementioned two problems, this implementation minimizes additional expenditures by designing a simple packaging method. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, this implementation defines two data packets of different lengths for transmitting data of different lengths. The data sending end (such as the first interface unit 114 or the second interface unit 123) can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted.

Taking the advanced eXtensible Interface (AXI for short) bus protocol as an example, the width of a single data is usually 73 bits when transmitting data based on AXI. Then, if data transmission is performed according to the existing 128 bits as the basic unit, a lot of bits will obviously be wasted.

Based on this, in this implementation, the data length of the payload of the short packet is determined to be 77 bits. Further, the overall data length of the short packet may be 112 bits. On the basis of ensuring that sufficient transmission information and a 77-bit payload are effectively accommodated, and is an entire packet, the overall data length of the data packet is reduced as much as possible. Among them, the whole packet means that the data length of the data packet is an integral multiple of 16, which is defined by the physical layer.

In a specific implementation, referring to FIG. 3, the short packet 3 may include: a header 31, used to carry the transmission information of the data packet; and a packet body 32, used to carry at least a part of the data.

Specifically, the packet body 32 may include a payload 321, and the length of the packet body 32 may be determined according to the width of a single data transmitted by the serial bus 14. For example, the data length of the payload 321 is 77 bits.

Further, the packet header 31 may include a channel identification field (Channel Identification, ChID for short) 311, which is used to indicate a channel for transmitting the data packet (short packet 3 in this embodiment).

Further, the packet header 31 may also include a credit counter (Credit Counter, CC for short) indication field 312, which is used to support flow control. For example, the CC indication field 312 may include a CC identification (CCID) and a credit value (Credit). Wherein, the CC identifier is used to indicate the channel to which the short packet 3 belongs, and the credit value is used to indicate the credit value of the channel.

Further, the packet header 31 may include multiple sets of CC indication fields 312. For example, FIG. 3 shows three sets of CC indication fields 312, which are respectively denoted as CCID0 and Credit0 groups, CCID1 and Credit1 groups, and CCID2 and Credit2 groups. Among them, the CC indicator fields 312 of different groups correspond to different channels.

Further, the short packet 3 may also include an ECC error correction code 33. Correspondingly, when the receiving end of the data packet (short packet 3 in this embodiment) checks the short packet 3 based on the ECC error correction code 33, if the check result is that a one-bit error occurs, the error is corrected If the check result is an error greater than one bit, it is reported to the upper layer. For example, the upper layer may be the application layer of the communication device 1.

In the short packet 3 shown in FIG. 3, the data length of the ECC error correction code 33 may be 9 bits, and the data length of the packet header 31 may be 26 bits. Thus, the packet body 32 collectively constitutes a short packet 3 with a total length of 112 bits.

In a variation, for data transmitted using a standard such as the PCIE protocol, the data length of the payload 321 of the packet body 32 can be adjusted according to the width of the single data to be transmitted. The data length of the corresponding short packet 3 can also be adjusted appropriately.

In a specific implementation, the data length of the payload in the long packet may be N times the data length of the payload in the short packet, and N is a positive integer greater than or equal to 2.

For example, referring to FIG. 4, the data length of the payload 421 in the long packet 4 may be three times the data length of the payload 321 in the short packet 3 shown in FIG. In this way, 4 groups of 73-bit data can be packed in the long packet 4.

Specifically, similar to the structure of the short packet 3, the long packet 4 may also include a packet header 41, a packet body 42, and an ECC check code 43.

Wherein, the packet header 41 may be used to carry the transmission information of the long packet 4. For example, the header 41 may include a channel identification field (ChID) and a CC indication field.

Further, the packet header 41 may also include a data line width indication field (Data Width, DW for short), which is used to indicate the width of the data line used by the data source for this transmission.

Further, the packet header 41 may also include a data position indication field (Position, Pos for short), which is used to indicate the position of the data packet (long packet 4 in this embodiment) transmitted this time in the data line.

Further, the payload 421 of the long packet 4 may include multiple intervals, and each interval has a corresponding ECC error correction code 43.

For example, referring to FIG. 4, the payload 421 may include 3 intervals, and the data length of each interval is 86 bits, 103 bits, and 103 bits, respectively. Each interval is followed by an ECC error correction code 43 corresponding to the interval.

The data length of the ECC error correction code 43 is 9 bits, and the data length of the packet header 41 is 17 bits. Therefore, the length of the long packet 4 is 112×3=336 bits.

In a specific implementation, the data to be transmitted may come from multiple data sources, and the step S101 may include the step of separately packaging data from different data sources to obtain the at least one data packet.

Correspondingly, the step S102 may include the step of using the same physical path of the serial bus 14 to transmit the at least one data packet, wherein the data packets of different data sources are distinguished based on different channel identification fields (ChID).

That is, data from different data sources will not be packaged into one data packet, but when transmitted through the serial bus 14, multiple channels of data can be packaged based on the channel identification field (ChID) and then transmitted using a set of physical channels.

Fig. 5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention.

Specifically, in conjunction with FIG. 1 and FIG. 2, when the first interface unit 114 uses the solution described in the embodiment shown in FIG. 2 to package data and transmits it through the serial bus 14, the second interface unit 123 as the data receiving end can execute this implementation Example solution to receive the short packet 3 and/or the long packet 4. Conversely, when the second interface unit 123 uses the solution described in the embodiment shown in FIG. 2 to pack data and transmits it via the serial bus 14, the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the short message. Pack 3 and/or Long Pack 4.

Specifically, referring to FIG. 5, the data transmission method may include the following steps:

Step S201: Use the serial bus to receive at least one data packet, where the data packet is a long packet or a short packet, and the long packet and the short packet have different data lengths;

Step S202: Unpack the at least one received data packet to obtain transmitted data.

Those skilled in the art understand that the steps S201 to S202 can be regarded as execution steps corresponding to the steps S101 to S102 in the embodiment shown in FIG. 2 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related descriptions of the embodiments shown in FIG. 2 to FIG. 4, which will not be repeated here.

Further, in the step S202, the standard data format for data transmission in the application processor 11 to which the first interface unit 114 belongs as the data receiving end, or the second interface unit 123 as the data receiving end belongs to The standard data format used for data transmission in the transfer demodulator 12 is to perform unpacking processing on the at least one received data packet. And convert the received data format of the at least one data packet into a corresponding standard data format.

In a specific implementation, when or after the step S202 is performed, the data transmission method of this embodiment may further include the step of: for each received data packet, the data packet is adjusted based on the ECC error correction code. Perform verification; if the verification result is that a one-bit error occurs, then the error is corrected; if the verification result is that an error greater than one bit occurs, then it is reported to the upper layer.

The inventor of the present application found through analysis that existing data transmission schemes generally use Cyclic Redundancy Check (CRC) for error detection. Although CRC can check for errors after data transmission, CRC cannot correct data errors. Once data errors are found, existing technical solutions generally use data retransmission to remedy. The retransmission not only causes a large data delay, but the implementation is also very complicated.

In the shared memory scenario described in this embodiment, the short packet 3 and the long packet 4 are transmitted in a one-bit error correction and two-bit error detection (SEC-DED ECC) mode. In this way, the data receiving end can immediately correct the one-bit error that occurs without retransmission. Further, since the probability of two or more bits error is already low, it can be processed by the upper layer. As a result, the low-latency effect of data transmission through the serial bus 14 is more significant.

In a variation, the ECC error correction code can be replaced with another type of error correction code for verification by the data receiving end.

Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention.

Specifically, referring to FIG. 6, the data transmission method of the serial bus 14 in this embodiment may include the following steps:

Step S301: Obtain the data to be transmitted, and pack the data into at least one data packet, the data length of the data packet is configurable, and the data packet includes a length indication field (Length) and at least one data packet Unit, the length indication field is used to indicate the number of data packet units;

Step S302: Use the serial bus to transmit the at least one data packet.

With reference to FIG. 1, when the data to be transmitted is transmitted from the first interface unit 114 to the second interface unit 123, the steps S301 and S302 may be executed by the first interface unit 114. Conversely, when the data to be transmitted is transmitted by the second interface unit 123 to the first interface unit 114, the steps S301 and S302 may be executed by the second interface unit 123.

As a result, the transmission efficiency can be maximized.

Specifically, referring to FIG. 7, the data packet 5 with variable data length described in this embodiment may include a packet header 51 and a packet body 52.

The packet header 51 may be used to carry the transmission information of the data packet 5. For example, similar to the short packet 3 and the long packet 4 in the embodiments shown in FIG. 2 to FIG. 4, the packet header 51 may include a channel identification field (ChID) and a CC indicator field.

The packet body 52 may be used to carry at least one data packet unit 521. In FIG. 7, Data0, Data1,..., Datan are taken as examples for exemplary display. The packet header 51 may further include the length indication field (Length), and Length=n indicates that the number of data packet units 521 carried by the packet body 52 is n.

The data length of different data packet units 521 may be the same or different. For example, the data length of each data packet unit 521 in the data packet 5 may be determined by a configuration register.

The data to be transmitted can come from multiple data sources. Among them, at least one data packet unit 521 in the same data packet 5 can come from the same data source, and the data packet unit 521 in different data packets 5 can come from different data sources. . That is, data from different data sources are packed into different data packages 5.

Further, when transmitting the data packet 5, at the physical layer, starting from the header 51 of the data packet 5, a transmission block 53 can be obtained by packing per unit data length. In other words, at the physical layer level, the data packet 5 may include multiple transmission blocks 53, and the data length of each transmission block 53 is fixed. Since the data length of the data packet 5 is configurable, the number of transmission blocks 53 included in different data packets 5 may be different.

For example, the unit data length may be 119 bits. That is, starting from the header 51 of the data packet 5, there is a packet for every 119 bits. These 119 bits may not have the header 51, and a certain data packet unit 521 may even be interrupted.

Furthermore, there may be a situation in which the last few or part of the last data packet unit 521 of the previous data packet 5 may be packed with the header 51 and/or at least a part of the data packet unit 521 of the next data packet 5 Into a transmission block 53.

In a specific implementation, the transmission block 53 may include a payload 531 and an error correction code 532. The data length of the payload 531 is 119 bits.

At the physical layer, the payload 531 of the transmission block 53 is obtained by packing every 119 bits from the header 51 of the data packet 5, and then the corresponding error correction code 532 is added to form the transmission block 53.

For example, the error correction code 532 may be an ECC error correction code.

In this embodiment, the length of the physical layer transmission block used is 128 bits. That is, the data length of the transmission block 53 adopts 128 bits common to the existing transmission protocol, wherein the data length of the payload 531 is 119 bits for transmitting data, and the ECC error correction code 532 is 9 bits.

Further, the at least one data packet 5 may be packaged end to end as a whole.

Fig. 8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention.

Specifically, in conjunction with FIG. 1 and FIG. 6, when the first interface unit 114 uses the solution described in the embodiment shown in FIG. 6 to pack data and transmits it through the serial bus 14, the second interface unit 123 as the data receiving end can execute this implementation Example scheme to receive the at least one data packet 5. Conversely, when the second interface unit 123 uses the solution described in the embodiment shown in FIG. 2 to package data and transmits it via the serial bus 14, the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the at least One data packet 5.

Specifically, referring to FIG. 8, the data transmission method may include the following steps:

Step S401: Use the serial bus to receive at least one data packet, the data length of the data packet is configurable, the data packet includes a length indication field and at least one data packet unit, and the length indication field is used for Indicating the number of data packet units;

Step S402 unpacks the received at least one data packet to obtain the transmitted data.

Those skilled in the art understand that the steps S401 to S402 can be regarded as the execution steps corresponding to the steps S301 to S302 in the embodiment shown in FIG. 6 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related description of the embodiment shown in FIG. 6 and FIG. 7, which will not be repeated here.

Further, in the step S402, it can be used as the standard data format for data transmission in the application processor 11 to which the first interface unit 114 belongs to the data receiving end, or the second interface unit 123 as the data receiving end belongs to In the standard data format for data transmission in the transfer demodulator 12, the received at least one data packet 5 is unpacked. And the received data format of the at least one data packet 5 is converted into a corresponding standard data format.

In a specific implementation, when or after the step S402 is performed, the data transmission method of this embodiment may further include the step: for each transmission block 53 in each data packet 5, based on the transmission block 53 The ECC error correction code 532 in the transmission block 53 checks the data contained in the transmission block 53 (carried in the payload 531); if the check result is one bit error, then the error is corrected; if the check result is more than one bit The error will be reported to the upper level.

In the shared memory scenario described in this embodiment, the transmitted data packet 5 uses a one-bit error correction and two-bit error detection (SEC-DED ECC) mode. In this way, the data receiving end can immediately correct the one-bit error that occurs without retransmission. Further, since the probability of two or more bits error is already low, it can be processed by the upper layer. As a result, the low-latency effect of data transmission through the serial bus 14 is more significant.

In a specific implementation, the communication device 1 may further include: an additional sharing module (not shown), the additional sharing module may be coupled to the application processor 11 and indirectly accessed through the application processor 11 Mentioned shared storage module 13.

For example, the additional sharing module may be an off-chip accelerator.

For another example, the additional shared module may also be an embedded neural network processor (Neural-network Processing Unit, NPU for short).

That is, the shared memory solution in this embodiment is not only applicable to the scenario where the application processor 11 and the modem 12 share the shared memory module 13, but also applicable to the scenario where more systems share the shared memory module 13 .

Further, on the basis of the above-mentioned solution of multiple chips (such as the application processor 11 and the modem 12) sharing an external memory (such as the shared storage module 13) shown in FIGS. 1 to 8, in order to solve the high latency and There are conflicts between the real-time requirements of the modem 12, and the solution of this embodiment also provides an improved modem, which aims to solve the problem that the access delay of the external memory is too large, which severely restricts the real-time performance requirements of the system.

Specifically, by analyzing the access mode of the external memory (such as the shared storage module 13) and the access characteristics of the functional modules of the modem 12 (such as the MCU and the hardware accelerator), the access delay performance is improved. In turn, the access to the shared storage module 13 related to cache misses is improved, and the access to the shared storage module 13 that is not cached is improved.

In a specific implementation, referring to FIG. 9, the modem 6 may include: a buffer module 62 for buffering data accessed by the modem 6.

Further, the modem 6 may further include a function module 61, and the buffer module 62 buffers the data accessed by the function module 61.

Further, the modem 6 may be coupled to an external processing device (not shown in FIG. 9), the function module 61 indirectly accesses the shared storage module 13 through the external processing device to obtain data, and the external processing device is connected to the shared storage module 13 The storage module 13 is coupled to and can directly access the shared storage module 13.

Therefore, by adding a buffer module 62 inside the modem 6, the data accessed by each functional module 61 is buffered, so as to reduce the frequency of the modem 6 accessing the shared memory module 13. As a result, a better balance can be achieved between the high latency of the external memory and the real-time requirements of the modem.

Further, the modem 6 described in this embodiment may be applied to the shared memory scenario shown in FIG. 1, and the modem 12 shown in FIG. 1 may adopt the specific structure of the modem 6 described in this embodiment. Correspondingly, the external processing device is the application processor 11 shown in FIG. 1.

In a specific implementation, the functional module 61 may include a Microcontroller Unit (Microcontroller Unit, MCU for short). Further, the MCU may include multiple sub-units, as shown in processor cluster #1 to processor cluster #N in the figure, and N is greater than or equal to 1.

In a specific implementation, the functional module 61 may include a hardware accelerator. Similar to the MCU, the hardware accelerator may also include multiple subunits, as shown in hardware accelerator #1 to hardware accelerator #M in the figure, and M is greater than or equal to 1.

In a specific implementation, when reading data, when any functional module 61 in the modem 6 reads data, it can read the cache module 62 first, if it hits, return the reading result, if it misses, continue to pass The application processor 11 accesses the shared storage module 13.

Further, the data buffered by the buffer module 62 may be data accessed by the functional module 61 of the modem 6 with high frequency in history.

For example, the historical access results of the functional module 61 in the shared storage module 13 are statistically analyzed by means of simulation or experiment, and the historical high-frequency access data of the functional module 61 is comprehensively analyzed according to the frequency and the amount of data accessed. The data is cached in the cache module 62 in advance for the function module 61 to access.

In order to further optimize the efficiency of data transmission, the data cached in the cache module 62 may be data that has been accessed by the functional module 61 of the modem 6 with high frequency in history and has a small amount of data.

In a specific implementation, the cache module 62 may include a plurality of first cache sub-modules 621, and different first cache sub-modules 621 may correspond to different functional modules 61.

For example, each processor cluster may be configured with a corresponding first cache sub-module 621.

For another example, each hardware accelerator may also be configured with a corresponding first cache submodule 621.

For each of the functional modules 61, when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it is hit, it returns the reading result, if it is not hit, it continues to pass the The application processor 11 accesses the shared storage module 13.

Take processor cluster #1 as an example. When the processor cluster #1 reads data, it first reads the first cache submodule 621 corresponding to it. The application processor 11 accesses the shared storage module 13.

Correspondingly, for the data obtained by the processor cluster #1 accessing the shared storage module 13 through the application processor 11, the data can be cached in the first cache submodule 621 corresponding to the processor cluster #1 to For later use.

In a specific implementation, the cache module 62 may further include a second cache sub-module 622, and the second cache sub-module 622 may correspond to multiple functional modules 61.

For example, the second buffer sub-module 622 may be coupled to the bus 63 in the modem 6 to buffer data transmitted on the bus 63. Wherein, the bus 63 may be the second bus 121 in FIG. 1.

Correspondingly, for each of the functional modules 61, when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it hits, it returns the reading result, and if it misses, it reads the corresponding first cache sub-module 621. The second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it is still missed.

Taking hardware accelerator #1 as an example, when the hardware accelerator #1 reads data, it first reads the first cache submodule 621 corresponding to it. The second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it still misses.

Correspondingly, for the data obtained by the hardware accelerator #1 accessing the shared storage module 13 through the application processor 11, the data may be preferentially cached to the first cache submodule 621 corresponding to the hardware accelerator #1 for preparation Use later. However, if the first cache submodule 621 corresponding to the hardware accelerator #1 is full at this time, the data may be cached in the second cache submodule 622.

In a specific implementation, the second buffer submodule 622 may be directly coupled to an interface unit for connecting the serial bus between the modem 6 and the external processing device. For example, the second buffer sub-module 622 may be coupled to the second interface unit 123 in FIG. 1 to buffer the data received by the second interface unit 123.

In a specific implementation, the processor cluster may include a coherency interface for implementing memory coherency management among the first cache sub-module 621, the second cache sub-module 622, and the shared storage module 13.

In a specific implementation, the first cache sub-module 621 may preferentially cache the data accessed by the corresponding functional module 61. Further, if the first cache sub-module 621 is full, the data accessed by the functional module 61 corresponding to the first cache sub-module 621 is cached to the second cache sub-module 622.

In a specific implementation, the second buffer sub-module 622 may preferentially buffer the data that has been accessed by the functional module 61 of the modem 6 with high frequency in history. For example, for pre-cached data, it can be preferentially placed in the public cache space (i.e., the second cache submodule 622) for later use.

In a specific implementation, the number and size of each of the first cache sub-module 621 and the second cache sub-module 622 may be divided and determined according to the statistical results of the corresponding functional module 61 and the modem 6's overall access to the shared storage module 13. of. That is, the size of each of the first cache sub-module 621 and the second cache sub-module 622 can be flexibly adjusted (Size Tuning).

Further, for the functional module 61 with a higher access requirement, a larger first cache submodule 621 may be allocated in a targeted manner. Alternatively, a plurality of first buffer sub-modules 621 are temporarily allocated to the functional module 61 to make full use of the buffer space of the modem 6.

In a specific implementation, the capacity of the second cache sub-module 622 may be greater than the capacity of the first cache sub-module 621. Further, the delay performance requirement of the second cache sub-module 622 may be slightly lower than the delay performance requirement of the first cache sub-module 621.

In a specific implementation, the first cache sub-module 621 may be an L1-level random access memory (Random Access Memory, RAM for short). The second cache sub-module 622 may be a relatively low-level but large-capacity RAM.

Alternatively, the first cache sub-module 621 may also be an L2 level RAM.

In a specific implementation, the modem 6 itself may be configured with a traditional cache (Cache) 64. In order to improve the access delay performance of the external memory (such as the shared memory module 13), the solution of this embodiment is provided with an additional amount of cache module 62 (such as RAM) in the modem 6 to reduce access to data with a small amount of data but with a higher frequency. External access requirements.

Specifically, in addition to the traditional cache (Cache), a part of the first cache sub-module 621 is additionally configured in the MCU.

Similarly, in the hardware accelerator, a part of the first cache sub-module 621 can also be configured according to requirements.

Similarly, the bus 63 can also be externally provided with part of the second cache sub-module 622 (RAM and Cache).

The solution of this embodiment can be widely applied to various types of external memories to improve the access delay performance.

Although the present invention is disclosed as above, the present invention is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

A serial bus data transmission method is characterized in that it includes:

Obtain the data to be transmitted, and pack the data into at least one data packet, the data length of the data packet is configurable, the data packet includes a length indication field and at least one data packet unit, and the length indication The field is used to indicate the number of data packet units;

The at least one data packet is transmitted using the serial bus.
The data transmission method according to claim 1, wherein the data to be transmitted comes from multiple data sources, wherein at least one data packet unit in the same data packet comes from the same data source, and the data in different data packets The data packet unit comes from different data sources.
The data transmission method according to claim 1, wherein the data packet further comprises:

The packet header is used to carry the transmission information of the data packet;

The packet body is used to carry the at least one data packet unit.
The data transmission method according to claim 3, wherein the packet header comprises:

The channel identification field is used to indicate the channel for transmitting the data packet;

The CC indication field is used to support flow control.
The data transmission method according to claim 1, wherein the data packet includes a plurality of transmission blocks, wherein each transmission block includes a payload and an error correction code, and the payload carries the at least one data packet unit At least part of it.
The data transmission method according to claim 5, wherein the error correction code is an ECC error correction code.
The data transmission method according to claim 5, wherein the data length of each transmission block is 128 bits, wherein the data length of the payload is 119 bits, and the data length of the error correction code is 9 bits.
The data transmission method according to claim 1, wherein the data length of each data packet unit in the data packet is determined by a configuration register.
A serial bus data transmission method is characterized in that it includes:

Use the serial bus to receive at least one data packet, the data length of the data packet is configurable, the data packet includes a length indication field and at least one data packet unit, and the length indication field is used to indicate the The number of data packet units;

Unpack the received at least one data packet to obtain the transmitted data.
The data transmission method according to claim 9, wherein the data packet includes a plurality of transmission blocks, wherein each transmission block includes a payload and an ECC error correction code, and the payload carries the at least one data packet In at least a part of the unit, the unpacking the at least one received data packet to obtain the transmitted data includes:

For each transmission block in each data packet, verify the data contained in the transmission block based on the ECC error correction code in the transmission block;

If the check result is a one-bit error, then the error is corrected;

If the check result is that there is an error greater than one bit, it is reported to the upper layer.
A communication device, characterized in that it comprises:

Application processor

modem;

Shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage module, the modem and the application processor are coupled through a serial bus and indirectly through the application processor Access the shared memory;

Wherein, the modem and the application processor use the method of any one of claims 1 to 10 for data transmission.