CN100444353C - Manufacturing method and device of semiconductor with multiple transistors - Google Patents
Manufacturing method and device of semiconductor with multiple transistors Download PDFInfo
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- CN100444353C CN100444353C CNB2005101090580A CN200510109058A CN100444353C CN 100444353 C CN100444353 C CN 100444353C CN B2005101090580 A CNB2005101090580 A CN B2005101090580A CN 200510109058 A CN200510109058 A CN 200510109058A CN 100444353 C CN100444353 C CN 100444353C
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Abstract
The invention relates to a semi-conductor device with several transistors and relative production. Wherein, said method comprises that providing a substrate with first conductive layer; the first conductive layer comprises the first electrode area and at least one second electrode layer; the first electrode layer is electrically connected to one of second electrode layer; forming the first semi-conductor layer to cover the second electrode area; forming one dielectric layer to cover the first electrode area and the first semi-conductive layer; forming the second semi-conductor layer at the dielectric layer of first electrode area; forming the second conductive layer; the second conductive layer comprises one third electrode area opposite to the second electrode area and on the dielectric layer; forming at least one fourth electrode layer opposite to the first electrode area and on the second semi-conductive layer. The invention can reduce the consumption of wiring hole, and reduce the cost.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of have a plurality of transistorized semiconductor devices and manufacture method thereof.
Background technology
In logical circuit, the basic framework of circuit is inverter (inverter).No matter be complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor therefore; CMOS) circuit formed of inverter, N type metal-oxide semiconductor (NMOS) inverter, P type metal-oxide semiconductor (PMOS) inverter or resistive load inverter assemblies such as (resistive load inverter) all might need source electrode to grid (source-to-gate) (promptly with buffer or the source/drain output input as next stratum), source electrode to source/drain or grid to grid (for example: interconnective demand inverter module).In traditional circuit production method, be to finish interconnects (interconnection) in the mode of setting up fairlead (via).
The generation type of traditional interconnects is as follows.
In a prior art, by optical etching technology (Photolithography) and oxygen plasma etching (oxygen plasma etching) with patterning Polyvinyl carbazole (polyvinyl pyrrolidone; PVP) film is to produce the fairlead of two interconnects interlayers.Then, utilize evaporation or ink-jetting process,, be patterned between transistorized source electrode and drain electrode, to make organic transistor with micromolecule or macromolecule organic semiconducting materials.(see also H.Klauk, M.Halik, U.Zschieschang, F.Eder, G.Schmid, and C.Dehm, " Pen tacene organic transistors and ringoscillators on glass and on flexible polymeric substrates ", AppliedPhysics Letters, Vol.82, Issue 23, P4175-P4177,9June 2003).
Another prior art is then printed carbon ink (carbon ink) in advance at the position of desire formation interconnects, and then finishes assembly.(see also A.Knobloch, A.Manuelli, A.Bernds, and W.Clemens, " Fullyprintedintegrated circuits from solution processablepolymers ", Journal of Applied Physics, Vol.96, Issue 4, P2286-P2291,15August 2004)
A prior art is arranged on the substrate both sides with metal wire (metal line) again, links to each other with fairlead again.(see also B.Crone, A.Dodabalapur, Y.-Y.Lin, RW Fi las, Z.Bao, A.LaDuca, R.Sarpeshkar, HE Katz, W.Li, " Large-scale complementary integratedcircuits based onorganic transistors ", Nature, Vol.403, P521-P523,2000)
In another prior art, utilized and covered shady shielding (shadow mask) patterning techniques and make.(see also PF Baude, DA Ender, MA Haase, TW Kelley, DV Muyres, and SDTheiss, " Pentacene-based radio-frequency identification circuitry ", Applied Physics Letters, Vol.82, Issue 22, P3964-P3966,2June 2003)
Yet in organic electronic, the making of fairlead need be passed through laser drill (laser drill), or realizes by optical etching technology and plasma etching.Thus, cost and complexity be will significantly increase, simplification and low cost that the organic electronic development is pursued run counter to.
Summary of the invention
Subject matter to be solved by this invention is to provide a kind of have a plurality of transistorized semiconductor devices and manufacture method thereof, to reduce the demand of fairlead in the integrated circuit.
Therefore,, the invention provides a kind of manufacture method of semiconductor device, include the following step: provide a substrate for reaching above-mentioned purpose; Form one first conductive layer on substrate, wherein this first conductive layer includes the first region and second electrode district, wherein one of in the first region electrically connect second electrode district; Form one first semiconductor layer to cover second electrode district; Form a dielectric layer to cover the first region and first semiconductor layer; Form one second semiconductor layer on the dielectric layer of corresponding the first region; And form one second conductive layer, wherein this second conductive layer includes corresponding second electrode district and is positioned at third electrode district on the dielectric layer and corresponding the first region and be positioned at the 4th electrode district on second semiconductor layer.
Moreover the present invention also provides a kind of manufacture method with a plurality of transistorized semiconductor devices, includes the following step: a substrate is provided; Form one first conductive layer on substrate, wherein this first conductive layer includes the first region and second electrode district; Form one first semiconductor layer to cover second electrode district; Form a dielectric layer to cover the first region and first semiconductor layer; Form one second semiconductor layer on the dielectric layer of corresponding the first region; And form one second conductive layer, wherein this second conductive layer includes: corresponding second electrode district and be positioned at a third electrode district on the dielectric layer, be positioned at the 4th electrode district on second semiconductor layer with corresponding the first region, wherein one of in third electrode district electrically connect the 4th electrode district.
And, can obtain a plurality of transistorized semiconductor devices that have that semiconductor device that first electrode one of electrically connects in second electrode or third electrode district one of electrically connect in the 4th electrode district according to above-mentioned manufacture method.
The present invention can reduce the demand of fairlead significantly, and then has reduced the laser drill amount in the electronic component manufacture process, thereby has reduced production cost.
Description of drawings
Figure 1A～1F is the sectional view of manufacture method of the semiconductor device of one embodiment of the invention;
Fig. 2 is the vertical view of the complete structure of Figure 1B; And
Fig. 3 is the vertical view of the complete structure of Fig. 1 F.
Wherein, Reference numeral:
110 substrates, 120 first conductive layers
122 the first regions, 124 second electrode districts
126 second electrode districts, 130 first semiconductor layers
140 dielectric layers, 150 second semiconductor layers
160 second conductive layers, 162 third electrode districts
164 the 4th electrode districts 166 the 4th electrode district
Embodiment
Main conception of the present invention is according to actual demand, and the electrode of desiring to electrically conduct of two assemblies is made in same one deck, and the end points that directly will connect links with conductive layer, significantly reducing the demand of fairlead (via), and then reduces cost.
Below enumerate specific embodiment describing content of the present invention in detail, and with accompanying drawing as aid illustration.The symbol of mentioning in the explanation please refer to Reference numeral.
With reference to Figure 1A～1F, be the flow chart of the manufacture method of semiconductor device according to an embodiment of the invention.Shown in Figure 1A, at first, provide a substrate 110.
Wherein, the material of substrate is preferably a kind of insulating material, for example: polymer, plastics or glass etc.It can be rigidity or flexible, and can be the standard printed circuit base material that comprises epoxy resin or pottery, wherein can be with siliceous or silicon dioxide (SiO
2) the insulating barrier setting thereon.
Then, form first conductive layer 120 on substrate 110, wherein this first conductive layer 120 has the first region 122 and more than one second electrode district 124,126, shown in Figure 1B.
The material of this first conductive layer can be any conductive material, and its conductivity can be between 10
-2～10
7S/cm.The material of this first conductive layer can be high-conductive metals such as gold (Au), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), platinum (Pt), neodymium (Nd) or its compound, or is conductive polyaniline (polyaniline; PANI) or poly-dioxoethyl thiophene: poly-p styrene sulfonic acid (polyethylenedioxythiophene:polysterene sulfonic acid; Conducting polymer such as PEDOT:PSS), again or be tin indium oxide (indium tin oxide; ITO) or indium zinc oxide conductive oxides such as (IZO).First conductive need be considered the matching degree of itself and first semiconductor layer and whole assembly except the material of selecting high conductivity.
Form first semiconductor layer 130, to cover second electrode district 124,126, shown in Fig. 1 C.
The material of this first semiconductor layer can comprise hole mobile material (being p type semiconductor layer) or electron transport material (being n type semiconductor layer).Hole mobile material can be pentaphene (Pentacene), poly-(the own thiophene of 3-) (poly (3-hexylthiophene); P3HT) P-type material such as or derivatives thereof, or sneak into the material of cathode materials such as carbon nano-tube (Carbon Nanotube), silicon nanowires (Si nanowire), carborundum/silicon nanocone, silicon-carbon nitrogen nano-pillar or aluminum nitride nanometer awl in P-type material.And electron transport material can be n type materials such as F16CuPc (copper hexadecafluorophthalocyanine), PTCDI or derivatives thereof, perhaps sneaks into the material of cathode materials such as carbon nano-tube, silicon nanowires, carborundum/silicon nanocone, silicon-carbon nitrogen nano-pillar or aluminum nitride nanometer awl in n type material.
Then, form dielectric layer 140 in the top of the first region 122 and first semiconductor layer 130, shown in Fig. 1 D.Promptly on exposed substrate, first and second electrode district, a dielectric layer 140 is set comprehensively.
The dielectric constant of this dielectric layer is greater than 2.5.And, its material can be polyvinyl alcohol (PVA), the insulating material of PVP (PVP) or polyacrylonitrile macromolecules such as (PAN), or its possible composite, again or such as silicon dioxide (SiO2), silicon nitride (SiN), alundum (Al (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), the inorganic material of zirconium dioxide (ZrO2) and tantalum pentoxide materials such as (Ta2O5), or in high molecular insulating material or its possible composite, add such as silicon dioxide, silicon nitride, alundum (Al, titanium dioxide, hafnium oxide, the material of inorganic material such as zirconium dioxide and tantalum pentoxide.The optimized choice of the material of dielectric layer will be with reference to the matching degree of technology, and the leakage rate of this dielectric layer is to the influence of assembly.
On the dielectric layer 140 of corresponding the first region 122, form second semiconductor layer 150 again, shown in Fig. 1 E.
The material of this second semiconductor layer can comprise hole mobile material (being p type semiconductor layer) or electron transport material (being n type semiconductor layer).In this, hole mobile material can be P-type materials such as pentaphene, P3HT or derivatives thereof, or sneaks into the material of cathode materials such as carbon nano-tube, silicon nanowires, carborundum/silicon nanocone, silicon-carbon nitrogen nano-pillar or aluminum nitride nanometer awl in P-type material.And electron transport material can be n type materials such as F16CuPc, PTCDI or derivatives thereof, or sneaks into the material of cathode materials such as carbon nano-tube, silicon nanowires, carborundum/silicon nanocone, silicon-carbon nitrogen nano-pillar or aluminum nitride nanometer awl in n type material.
At last, form second conductive layer 160, wherein second conductive layer 160 has a third electrode district 162 and more than one the 4th electrode district 164,166, shown in Fig. 1 F.Wherein, the material of this second conductive layer 160 can be any conductive material, and its conductivity can be between 10
2～10
7S/cm.In this, the material of second conductive layer can be high-conductive metals such as gold (Au), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), platinum (Pt), neodymium (Nd) or its compound, or is conductive polyaniline (polyaniline; PANI) or the fen of poly-dioxoethyl plug: poly-p styrene sulfonic acid (polyethylene dioxythiophene:polysterene sulfonic acid; Conducting polymer such as PEDOT:PSS), again or be tin indium oxide (indium tin oxide; ITO) or indium zinc oxide conductive oxides such as (IZO).
For convenience of description, forming two semiconductor subassemblies, third electrode district 162 is positioned on the dielectric layer 140 of zone line of corresponding second electrode district 124,126; And the 4th electrode district 164,166 lay respectively on second conductive layer 150 of two side areas of corresponding the first region 122.
In this embodiment, can will be electrical connected (as shown in Figure 2) one of in the first region 122 and second electrode district 124,126, perhaps with being electrical connected (as shown in Figure 3) one of in third electrode district 162 and the 4th electrode district 164,166, with electrically connect two semiconductor subassemblies.In other words, when the first region 122 and third electrode district 162 as grid, and second electrode district 124,126 and the 4th electrode district 164,166 are in order to as source/drain the time, can obtain the interconnective two-transistor assembly of grid, to form the semiconductor device of a new kenel to source/drain.
At this, though describe with the framework of grid to source/drain, in like manner also can be by the electrode district of adjusting conductive layer and the setting that changes semiconductor layer, and form source electrode to grid, source electrode to source/drain or grid interconnective two semiconductor subassemblies to states such as grids.
Moreover the formation of each layer structure (i.e. first conductive layer, first semiconductor layer, dielectric layer, second semiconductor and second conductive layer) can be by depositing or be coated with its material comprehensively, and then according to the actual demand patterning, to form required structure.
For example, can shield according to actual demand utilization tradition litho then and apply pattern, carrying out patterning, and then form the structure of required first conductive layer and second conductive layer by comprehensively deposition or coating conductive material.In addition, also can utilize other technology to satisfy the demand of patterning.
In addition,, only have two transistorized semiconductor devices in this and describe, have a plurality of transistorized semiconductor devices yet also can form by same concept with formation for asking convenient explanation.In other words, the electrode that a plurality of transistors need be linked is arranged at same one deck, and utilizes conductive layer that the interconnective end points of desire is linked, and therefore can significantly reduce the demand of fairlead in the integrated circuit, and then reduce cost.
Though the present invention with aforesaid preferred embodiment openly as above; but be not in order to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention must be looked this specification appended claims person of defining and is as the criterion.
Claims (28)
1, a kind of manufacture method with a plurality of transistorized semiconductor devices is characterized in that, includes the following step:
One substrate is provided;
Form one first conductive layer on this substrate, wherein this first conductive layer includes:
One the first region; And
At least one second electrode district;
Wherein this first region one of electrically connects in this second electrode district by this first conductive layer;
Form one first semiconductor layer to cover this second electrode district;
Form a dielectric layer to cover this first region and this first semiconductor layer;
Form one second semiconductor layer in on should this dielectric layer of the first region; And
Form one second conductive layer, wherein this second conductive layer includes:
One third electrode district is to should second electrode district and be positioned on this dielectric layer; And
At least one the 4th electrode district, to should the first region and be positioned on this second semiconductor layer, wherein this first and this third electrode district respectively as two transistorized grids, and this second and the 4th electrode district respectively as two transistorized source/drains.
2, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, the material of this substrate is a kind of insulating material.
3, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, this first and the conductivity of this second conductive layer between 10
-2～10
7S/cm.
4, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, this first and the material of this second conductive layer be selected from high-conductive metal, conducting polymer or conductive oxide.
5, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, the dielectric constant of this dielectric layer is greater than 2.5.
6, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, the material of this dielectric layer is selected from insulating polymeric material, inorganic material or its combination.
7, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 1 is characterized in that, this first and the material of this second semiconductor layer be hole mobile material or electron transport material.
8, a kind of manufacture method with a plurality of transistorized semiconductor devices is characterized in that, includes the following step:
One substrate is provided;
Form one first conductive layer on this substrate, wherein this first conductive layer has a first region and at least one second electrode district;
Form one first semiconductor layer to cover this second electrode district;
Form a dielectric layer to cover this first region and this first semiconductor layer;
Form one second semiconductor layer in on should this dielectric layer of the first region; And
Form one second conductive layer in this second semiconductor layer with on should this dielectric layer of second electrode district, wherein, this second conductive layer includes:
One third electrode district is to should second electrode district and be positioned on this dielectric layer; And
At least one the 4th electrode district is to should the first region and be positioned on this second semiconductor layer;
Wherein, this third electrode district one of electrically connects in the 4th electrode district by this second conductive layer, this first and this third electrode district respectively in order to as two transistorized grids, and this second and the 4th electrode district respectively in order to as two transistorized source/drains.
9, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, the material of this substrate is a kind of insulating material.
10, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, this first and the conductivity of this second conductive layer between 10
-2～10
7S/cm.
11, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, this first and the material of this second conductive layer be selected from high-conductive metal, conducting polymer or conductive oxide.
12, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, the dielectric constant of this dielectric layer is greater than 2.5.
13, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, the material of this dielectric layer is selected from insulating polymeric material, inorganic material or its combination.
14, the manufacture method with a plurality of transistorized semiconductor devices as claimed in claim 8 is characterized in that, this first and the material of this second semiconductor layer be selected from hole mobile material or electron transport material.
15, a kind of have a plurality of transistorized semiconductor devices, it is characterized in that, includes:
One substrate;
One conductive layer is positioned on this substrate, and this conductive layer comprises one first electrode and at least one second electrode, wherein electrically connects this first electrode by this conductive layer one of in this second electrode:
One first semiconductor layer is covered on this second electrode;
One dielectric layer is covered on this first electrode and this first semiconductor layer;
One second semiconductor layer is positioned on should this dielectric layer of first electrode;
One third electrode is positioned on should this dielectric layer of second electrode; And
At least one the 4th electrode is positioned on should this second semiconductor layer of first electrode, wherein this first and this third electrode be respectively two transistorized grids, and this second and the 4th electrode be respectively two transistorized source/drains.
16, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this substrate is a kind of insulating material.
17, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that the conductivity of this first to the 4th electrode is between 10
-2～10
7S/cm.
18, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this first to the 4th electrode is selected from high-conductive metal, conducting polymer or conductive oxide.
19, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that the dielectric constant of this dielectric layer is greater than 2.5.
20, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this dielectric layer is selected from insulating polymeric material, inorganic material or its combination.
21, as claimed in claim 15 have a plurality of transistorized semiconductor devices, it is characterized in that, this first and the material of this second semiconductor layer be selected from hole mobile material or electron transport material.
22, a kind of have a plurality of transistorized semiconductor devices, it is characterized in that, includes:
One substrate;
One first electrode is positioned on this substrate;
At least one second electrode is positioned on this substrate;
One first semiconductor layer is covered on this second electrode;
One dielectric layer is covered on this first electrode and this first semiconductor layer;
One second semiconductor layer is positioned on should this dielectric layer of first electrode; And
One conductive layer, comprise a third electrode and at least one the 4th electrode, wherein this third electrode is positioned on should this dielectric layer of second electrode, the 4th electrode lays respectively on should this second semiconductor layer of first electrode, this third electrode one of electrically connects in the 4th electrode by this conductive layer, this first and this third electrode be respectively two transistorized grids, and this second and the 4th electrode be respectively two transistorized source/drains.
23, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this substrate is a kind of insulating material.
24, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that the conductivity of this first to the 4th electrode is between 10
-2～10
7S/cm.
25, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this first to the 4th electrode is selected from high-conductive metal, conducting polymer or conductive oxide.
26, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that the dielectric constant of this dielectric layer is greater than 2.5.
27, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that the material of this dielectric layer is selected from insulating polymeric material, inorganic material or its combination.
28, as claimed in claim 22 have a plurality of transistorized semiconductor devices, it is characterized in that, this first and the material of this second semiconductor layer be selected from hole mobile material or electron transport material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101090580A CN100444353C (en) | 2005-10-17 | 2005-10-17 | Manufacturing method and device of semiconductor with multiple transistors |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101090580A CN100444353C (en) | 2005-10-17 | 2005-10-17 | Manufacturing method and device of semiconductor with multiple transistors |
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| Publication Number | Publication Date |
|---|---|
| CN1953160A CN1953160A (en) | 2007-04-25 |
| CN100444353C true CN100444353C (en) | 2008-12-17 |
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| CNB2005101090580A Expired - Fee Related CN100444353C (en) | 2005-10-17 | 2005-10-17 | Manufacturing method and device of semiconductor with multiple transistors |
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| CN108539018A (en) * | 2018-01-24 | 2018-09-14 | 重庆大学 | A kind of OFET pipes driving and preparation method thereof based on pervasive insulating layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1255697A (en) * | 1992-05-29 | 2000-06-07 | 株式会社半导体能源研究所 | Electronic device, matrix device, photoelectric displaying device and semiconductor memory with film transistor |
| US6331476B1 (en) * | 1998-05-26 | 2001-12-18 | Mausushita Electric Industrial Co., Ltd. | Thin film transistor and producing method thereof |
| US20050176194A1 (en) * | 2004-01-29 | 2005-08-11 | Casio Computer Co., Ltd. | Transistor arrray, manufacturing method thereof and image processor |
-
2005
- 2005-10-17 CN CNB2005101090580A patent/CN100444353C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1255697A (en) * | 1992-05-29 | 2000-06-07 | 株式会社半导体能源研究所 | Electronic device, matrix device, photoelectric displaying device and semiconductor memory with film transistor |
| US6331476B1 (en) * | 1998-05-26 | 2001-12-18 | Mausushita Electric Industrial Co., Ltd. | Thin film transistor and producing method thereof |
| US20050176194A1 (en) * | 2004-01-29 | 2005-08-11 | Casio Computer Co., Ltd. | Transistor arrray, manufacturing method thereof and image processor |
Non-Patent Citations (2)
| Title |
|---|
| Large-scale complementary integrated circuits based on organic transistors.. B. Crone et al.Nature,Vol.403 . 2000 |
| Large-scale complementary integrated circuits based on organic transistors.. B. Crone et al.Nature,Vol.403 . 2000 * |
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|---|---|
| CN1953160A (en) | 2007-04-25 |
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