CN100444149C - Symmetrical multiple processor blade server - Google Patents
Symmetrical multiple processor blade server Download PDFInfo
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- CN100444149C CN100444149C CNB2006101715384A CN200610171538A CN100444149C CN 100444149 C CN100444149 C CN 100444149C CN B2006101715384 A CNB2006101715384 A CN B2006101715384A CN 200610171538 A CN200610171538 A CN 200610171538A CN 100444149 C CN100444149 C CN 100444149C
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Abstract
The invention discloses a symmetry multi-processor blade server, belonging to blade server technical field, for resolving the defects of prior blade server which has inadequate CPU number, to fail to meet applications. The invention can provide a multi-path operation condition with 8 paths, 16 paths or 32 paths, or the like to meet large operation need of user. The invention comprises at least two calculation blades, while each calculation blade is at provided with a CPU chip group, wherein each calculation blade is provided with an ultra-process expander, the CPU chip groups of each operation blade and the CPU chip groups of different calculation blades are connected via the ultra-process expander. The invention more particularly can be used for the application with massive data.
Description
Technical field
The present invention relates to a kind of blade server, particularly relate to a kind of symmetric multiprocessor (SymmetricalMulti-Processing) blade server.
Background technology
Owing to require the relative minicomputer of blade server must have convenient expansion, highly versatile, cheap characteristics, can not calculate on the blade at the monolithic of blade server again too much CPU is set, the calculating blade of therefore existing blade server mainly adopts 2 road CPU design, has only a spot of employing 4 road CPU design, but in the application that super large data volumes such as science calculating are handled, have 8 the tunnel, many CPU computing equipment more than 16 tunnel even 32 tunnel could satisfy the various needs of using, at present the monolithic that exists calculates the defective of the CPU negligible amounts in the blade, has restricted the application of blade server in a lot of fields.
Summary of the invention
The objective of the invention is at existing blade server CPU lazy weight, can't satisfy the defective of various application demands, a kind of symmetric multiprocessor blade server is provided, and it can provide the environment of the many CPU computing more than 8 tunnel, 16 tunnel even 32 tunnel, satisfies user's various macrooperation amount demands.
In order to reach the foregoing invention purpose, the technical solution used in the present invention is:
A kind of symmetric multiprocessor blade server, comprise that at least two are calculated blade, on the described every calculating blade cpu chip group is set at least, wherein, calculate on the blade at every and to be provided with the hyperthread expanding element, interconnect by the hyperthread expanding element between every cpu chip group of calculating on the blade and between the cpu chip group of various computing blade.
In the optimal technical scheme provided by the invention, described cpu chip group comprises cpu chip, system request queue, crossing door bolt arbitration logic unit, described cpu chip is connected with system request queue is two-way, described arbitration logic unit is connected with system request queue is two-way, and arbitration logic unit is two-way is connected for described hyperthread expanding element and crossing door bolt.
In the further optimal technical scheme provided by the invention, described cpu chip group comprises super transmission unit and Memory Controller Hub, and arbitration logic unit is two-way is connected with described crossing door bolt respectively for described super transmission unit and Memory Controller Hub.
In the further optimal technical scheme provided by the invention, described calculating blade is 2 to 8, and every described calculating blade is provided with 1 to 2 described cpu chip group.
Technique scheme of the present invention can produce following technique effect:
Compare with the prior art blade server, the present invention has overcome the defective that the CPU negligible amounts can not be met consumers' demand, the many CPU that realized blade server handle, make a CPU number in the blade server reach 8,16 even 256, can satisfy user's intensive application demand.Owing to adopt Hyper-Threading that each CPU that calculates on the blade is carried out the multiprocessor connection, realize that the many CPU of blade server handle, its arithmetic speed was greatly improved, satisfied the requirement of using to CPU quantity, make the present invention keep expansion convenience, highly versatile and the cheap characteristic of prior art blade server again, by adopting the experiment of circulation accumulation calculating method as can be known, the CPU of one of every increase and former CPU same model, its arithmetic speed can increase about 70% during than single CPU.
Description of drawings
Fig. 1 is a cpu chip group line synoptic diagram of the present invention;
Fig. 2 is each assembly line synoptic diagram of the present invention;
Fig. 3 is a data handling procedure synoptic diagram of the present invention.
Reference numeral:
The 1--CPU chipset.
Embodiment
Under the design philosophy of technique scheme of the present invention, the present invention can have multiple, is illustrated below by specific embodiment.
Embodiment one
One embodiment of the present invention as shown in Figure 1, comprise that two are calculated blade, on the described every calculating blade two cpu chip groups 1 are set, calculate on the blade at every and to be provided with the hyperthread expanding element, interconnect by the hyperthread expanding element between every cpu chip group of calculating on the blade and between the cpu chip group of various computing blade.
In the present embodiment, cpu chip group and hyperthread expanding element adopt Intel Xeon product E M64T, designated instruction in the blade server internal memory, extracted by the cpu chip group, this cpu chip group is carried out communication and arbitration by other cpu chip groups in hyperthread expanding element and the blade server, the selected cpu chip group of carrying out designated instruction, send designated instruction to chosen cpu chip group by the hyperthread expanding element, chosen cpu chip group is carried out designated instruction and is carried out computing or transmit data with I/O.
Embodiment two
A kind of preferred implementation of the present invention as shown in Figure 2, comprise that two are calculated blade, on the described every calculating blade two cpu chip groups are set, described cpu chip group comprises cpu chip, system request queue, crossing door bolt arbitration logic unit, described cpu chip is connected with system request queue is two-way, described arbitration logic unit is connected with system request queue is two-way, and arbitration logic unit is two-way is connected for described hyperthread expanding element and crossing door bolt.
In the present embodiment, cpu chip group and hyperthread expanding element adopt AMD Opteron product A MD 64, designated instruction in the blade server internal memory, extracted by the cpu chip group by Memory Controller Hub, this cpu chip group is carried out communication and arbitration by other cpu chip groups in hyperthread expanding element and the blade server, the selected cpu chip group of carrying out designated instruction, send designated instruction to chosen cpu chip group by the hyperthread expanding element, chosen cpu chip group is carried out designated instruction and is carried out computing or transmit data by super transmission unit and I/O.
Embodiment three
Another kind of preferred implementation of the present invention as shown in Figure 2, comprise that two are calculated blade, on the described every calculating blade two cpu chip groups are set, described cpu chip group comprises cpu chip, system request queue, crossing door bolt arbitration logic unit, super transmission unit and Memory Controller Hub, described cpu chip is connected with system request queue is two-way, described arbitration logic unit is connected with system request queue is two-way, arbitration logic unit is two-way is connected for described hyperthread expanding element and crossing door bolt, and arbitration logic unit is two-way is connected with described crossing door bolt respectively for described super transmission unit and Memory Controller Hub.
In the present embodiment, cpu chip group and hyperthread expanding element adopt AMD Opteron product A MD 64, and as shown in Figure 3, the designated instruction in the blade server internal memory is extracted by cpu chip by Memory Controller Hub; According to each system request queue information, crossing door bolt arbitration logic unit arbitration is also pointed to chosen CPU; By the hyperthread expanding element, instruction to be named is sent to directed CPU; The CPU operation information is set in the system request queue of directed CPU; Chosen cpu chip is carried out designated instruction and is carried out computing or transmit data by super transmission unit and I/O.
Embodiment four
This embodiment is a further preferred implementation of the present invention, compare with embodiment three, the difference of present embodiment be in, select for use 8 to calculate blades, each calculates blade and is provided with 1 cpu chip group.
Should be noted that at last: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the field are to be understood that: still can make amendment or be equal to replacement the specific embodiment of the present invention, and do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (2)
1, a kind of symmetric multiprocessor blade server, comprise that at least two are calculated blade, on the described every calculating blade cpu chip group is set at least, it is characterized in that, calculate on the blade at every and to be provided with the hyperthread expanding element, interconnect by the hyperthread expanding element between every cpu chip group of calculating on the blade and between the cpu chip group of various computing blade;
Described cpu chip group comprises cpu chip, system request queue, crossing door bolt arbitration logic unit, super transmission unit and Memory Controller Hub, described cpu chip is connected with system request queue is two-way, described arbitration logic unit is connected with system request queue is two-way, and arbitration logic unit is two-way is connected for described hyperthread expanding element and crossing door bolt; Arbitration logic unit is two-way is connected with described crossing door bolt respectively for described super transmission unit and Memory Controller Hub.
2, a kind of symmetric multiprocessor blade server as claimed in claim 1 is characterized in that, described calculating blade is 2 to 8, and every described calculating blade is provided with 1 to 2 described cpu chip group.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101715384A CN100444149C (en) | 2006-12-30 | 2006-12-30 | Symmetrical multiple processor blade server |
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| CNB2006101715384A CN100444149C (en) | 2006-12-30 | 2006-12-30 | Symmetrical multiple processor blade server |
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| CN101059792A CN101059792A (en) | 2007-10-24 |
| CN100444149C true CN100444149C (en) | 2008-12-17 |
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| CN102929363B (en) * | 2012-10-25 | 2016-08-31 | 浪潮电子信息产业股份有限公司 | A kind of method for designing of high-density blade server |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050076107A1 (en) * | 2003-09-24 | 2005-04-07 | Goud Gundrala D. | Virtual management controller to coordinate processing blade management in a blade server environment |
| CN2713539Y (en) * | 2004-07-12 | 2005-07-27 | 广达电脑股份有限公司 | Blade server |
| US20060020767A1 (en) * | 2004-07-10 | 2006-01-26 | Volker Sauermann | Data processing system and method for assigning objects to processing units |
| CN1869869A (en) * | 2005-05-24 | 2006-11-29 | 英业达股份有限公司 | Blade server system |
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- 2006-12-30 CN CNB2006101715384A patent/CN100444149C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050076107A1 (en) * | 2003-09-24 | 2005-04-07 | Goud Gundrala D. | Virtual management controller to coordinate processing blade management in a blade server environment |
| US20060020767A1 (en) * | 2004-07-10 | 2006-01-26 | Volker Sauermann | Data processing system and method for assigning objects to processing units |
| CN2713539Y (en) * | 2004-07-12 | 2005-07-27 | 广达电脑股份有限公司 | Blade server |
| CN1869869A (en) * | 2005-05-24 | 2006-11-29 | 英业达股份有限公司 | Blade server system |
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Effective date of registration: 20220725 Address after: 100193 No. 36 Building, No. 8 Hospital, Wangxi Road, Haidian District, Beijing Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Patentee after: DAWNING INFORMATION INDUSTRY Co.,Ltd. Address before: 100084 Beijing Haidian District City Mill Street No. 64 Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |