CN100438360C - Method and equipment for realizing parallel correlator utilizing block integral in spread spectrum communication - Google Patents
Method and equipment for realizing parallel correlator utilizing block integral in spread spectrum communication Download PDFInfo
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- CN100438360C CN100438360C CNB2005100815465A CN200510081546A CN100438360C CN 100438360 C CN100438360 C CN 100438360C CN B2005100815465 A CNB2005100815465 A CN B2005100815465A CN 200510081546 A CN200510081546 A CN 200510081546A CN 100438360 C CN100438360 C CN 100438360C
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Abstract
This invention provides a method and a device for applying separate integration to realize parallel correlators in frequency-spread communication, in which, a device for processing frequency-spread signals includes an IF signal pre-process unit and multiple parallel separate integrators, the IF signal pre-process unit can generate a pre-integrated result based on the input signal and local reference signals in a preset rate to divide it into multiple groups and each of which includes a pre-integrated result with preset numbers,the multiple parallel separate integrators communicate with said IF signal pre-process unit and each one can receive multiple sets of results continuously and operates the pre-integrated results of the preset numbers of the set relatively with multiple segments of offset false random noise codes so as to get multiple partial relative operation results till to receive the results of preset number of the next group.
Description
Technical field
The present invention relates to the spread spectrum digital receiver, relate to the realization of the parallel correlator in global positioning system (GPS) receiver more specifically.
Background technology
Need under noise circumstance in the communications applications of high reliability, spread spectrum communication has its superiority.According to Shannon's theorems, can reduce the demand of high s/n ratio by widened spectrum, this just shows and adopts spread spectrum technic can transmit and detect weak signal.Be spread-spectrum, high speed Pseudo-Random Noise Code (PRN) often is used to modulate narrow band signal to produce broadband signal.Broadband signal is modulated so that transmit data by inter-area traffic interarea.Information data rate is usually far below code element (chip) speed of PRN sign indicating number, and usually data and chip signal along synchronous.
From the information data of spread-spectrum signal, gps signal for example can transfer the signal that receives to the signal of lower frequency and then searched earlier by multiply by a local carrier signal that produces.Local carrier signal can be produced by the local oscillator after suitable tuning.If the frequency of local carrier signal is identical with the original narrowband carrier of reception with phase place, received signal and local carrier signal multiply each other and must multiplier output signal be exactly the bipolarity broadband traffic.This bipolarity broadband traffic is the product of bipolarity PRN sign indicating number and information data sequence.Then, the PRN sign indicating number that produces by the consistent this locality of PRN sign indicating number sequential of wideband data be multiply by and receiving removes the P RN sign indicating number of reception.So just can obtain data message.The above is the signal despreading process.
Gps signal is by the spread-spectrum signal of gps satellite in L1, L2 and the transmission of L5 frequency.Current commercial GPS receiver uses L1 frequency (1575.42MHZ) usually.The several signals that send on the L1 carrier wave are: thick catch code (C/A sign indicating number), P sign indicating number and navigation data.The detailed data of satellite orbit is included in the navigation data.The C/A sign indicating number is mainly used in the location purposes in the commercial receiver.The C/A sign indicating number is used to judge pseudorange (apparent distance of satellite), and the GPS receiver then utilizes this pseudorange to judge the position of satellite.The C/A sign indicating number is a kind of in the PRN sign indicating number, describes before its function.Radiofrequency signal behind C/A sign indicating number coding becomes spread-spectrum signal.Each satellite all has a unique C/A sign indicating number, and this C/A sign indicating number that circulates repeatedly.The C/A sign indicating number is one 0 and 1 (binary system) sequence.Each 0 or 1 is considered to one " chip ".The C/A sign indicating number has 1023 chips long, and sends with the speed of per second 1.023 million chips, and for example, the one-period of C/A sign indicating number continues signa.Each chip also can think to have two states :+1 and-1.
One group of data of being collected by the GPS receiver comprise the signal from several satellites.Signal from different satellites passes through different channel propagations.Usually, the GPS receiver is handled the signal from several channels simultaneously.Each signal all has one to have the C/A sign indicating number of different zero-times and different Doppler frequency shift amounts.Therefore, for searching for certain satellite-signal, the GPS receiver carries out two dimension search usually, on each possible frequency the different C/A sign indicating number of each zero-time is searched for." different zero-time " herein can be understood as the result of C/A code phase time-delay.In the GPS receiver, adopt the starting point of catching method search C/A sign indicating number and the Doppler frequency shift of the frequency of carrier wave, particularly signal.For whether the signal of search in certain characteristic frequency point and specific C/A sign indicating number time-delay place exists, the GPS receiver is tuned to this frequency, and input signal and known PRN sign indicating number carry out related operation, and the amount of delay of known PRN sign indicating number is relevant with the time of advent of input signal.If do not search signal, then continue search and have the C/A sign indicating number that the next one may be delayed time.Usually, each possible time-delay of C/A sign indicating number obtains by mobile C/A sign indicating number 1/2 chip.Because the C/A sign indicating number comprises 1023 chips, searches for a fixed frequency and need detect 2046 possible time-delays.After all possible time-delay has detected, continue the next possible frequency of search.Because will search for thousands of frequencies and sign indicating number time-delay, the speed of acquisition procedure is just extremely important.
Fig. 1 has illustrated the block diagram of GPS receiver 100 of prior art.Usually, the GPS receiver comprises two parts: RF (radio frequency) front-end module 101 and baseband signal processing module 103.The gps signal that gps satellite transmits is received by antenna 102, and by RF tuner 104 and frequency synthesizer 105, received signal (also being considered to input signal) is converted to the signal with desired output frequency with gps signal (radiofrequency signal).Then, analog/digital converter (ADC) 106 with predetermined sampling frequency will change signal digitalized.Be considered to intermediate frequency (IF) signal through conversion and digitized signal.This intermediate-freuqncy signal then is sent to the baseband signal processing module 103 that comprises several signal processing stages.The IF signal is sent to trapping module 110, and as previously mentioned, Doppler frequency shift search and C/A sign indicating number phase shift search are carried out in trapping module 110.At acquisition phase, carry out the integration that related operation is finished the IF signal according to IF signal and C/A sign indicating number.Tracking module 112 uses carrier-tracking loop and code tracking loop by IF signal trace gps signal, thereby obtains the navigation data that comprises in the gps signal.Then, navigation data computing module 114 and position computation module 116 utilize navigation data to calculate user's position.
For reaching higher performance, adopt parallel correlator to carry out parallel search usually.Yet, use a large amount of parallel correlators to need a large amount of logical resources and to the frequency requirement height of related operation, if be not optimized, the process of catching is difficult in ASIC and goes up and realize.Therefore, the present invention is mainly based on the optimization of the trapping module of realizing parallel correlator.
Summary of the invention
The method and apparatus that the invention provides a kind of I of employing F Signal Pretreatment technology and block integral technology is realized the function of equivalent parallel correlator.Therefore, band spread receiver just makes that at acquisition phase the related operation frequency is lower, the door computing is less, power consumption reduces.
The invention provides a kind of method of in circuit, handling spread-spectrum signal with a plurality of block integral devices, wherein this circuit uses an input signal, local carrier signal and Pseudo-Random Noise Code, and this input signal is digitized with a predetermined sampling frequency.This method comprises: a) produce pre-integral result according to input signal and local carrier signal with set rate, b) the pre-integral result with one group of predetermined quantity sends to each block integral device, c) reception has the Pseudo-Random Noise Code of code phase separately in each block integral device, d) according to this group predetermined quantity pre-integral result and one section Pseudo-Random Noise Code, operating part related operation in each block integral device, e) in each block integral device, obtain the result of part correlation computing, f) this part correlation operation result is added among the previous partial integration result, g) will sends to the Pseudo-Random Noise Code skew precalculated position in each block integral device.This method repeating step d) to g) send to each block integral device up to next pre-integral result of organizing predetermined quantity.The further repeating step b of this method) to h) up in each block integral device, obtaining a plurality of complete related operation results; Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
The present invention also provides the equipment of a kind of processing with the digitized spread-spectrum signal of predetermined sampling frequency.This equipment comprises an intermediate-freuqncy signal pretreatment unit and a plurality of parallel block integral device of communicating by letter with the intermediate-freuqncy signal pretreatment unit.This intermediate-freuqncy signal pretreatment unit produces pre-integral result according to input signal and local carrier signal with set rate.Each block integral device receives the pre-integral result of many group predetermined quantities continuously, for the pre-integral result of every group of predetermined quantity, thereby the pre-integral result that each block integral device will be organized predetermined quantity carries out the part correlation computing with the Pseudo-Random Noise Code of multistage after skew respectively obtains a plurality of part correlation operation results, sends in each block integral device up to pre-integral result of next group predetermined quantity; Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
The present invention also provides a kind of receiver of receiving spread frequency signal.This receiver comprises a tuner, an analog-digital converter, an equipment and a memory cell of handling spread-spectrum signal.Tuner is converted to intermediate frequency with the spread-spectrum signal that receives from original frequency.The analog-digital converter that is connected to tuner is converted to digital output signal with predetermined sampling frequency with intermediate-freuqncy signal.The equipment of handling spread-spectrum signal is connected to analog-digital converter.This equipment comprises an intermediate-freuqncy signal pretreatment unit and a plurality of parallel block integral device of communicating by letter with the intermediate-freuqncy signal pretreatment unit.This intermediate-freuqncy signal pretreatment unit produces pre-integral result according to digital input signals and local carrier signal with set rate.Each block integral device receives the pre-integral result of many group predetermined quantities continuously, pre-integral result for every group of predetermined quantity, thereby the pre-integral result that each block integral device will be organized predetermined quantity carries out the part correlation computing with the Pseudo-Random Noise Code of multistage after skew respectively obtains a plurality of part correlation operation results, sends in each block integral device up to pre-integral result of next group predetermined quantity.This equipment also comprises a control logic that is connected to memory cell and these a plurality of block integral devices.This control logic reads a previous partial correlation results from memory cell, current partial correlation results is added in the previous partial correlation results, again with modified previous partial correlation results write storage unit.Memory cell is connected to control logic and storage computation result.Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
Description of drawings
Other characteristic of the present invention and advantage will be in following detailed descriptions and are more obvious in conjunction with illustrated explanation, and wherein same numbers is represented similar elements, and wherein:
Figure 1 shows that the prior art block diagram of band spread receiver.
Figure 2 shows that the structure chart of existing trapping module.
Figure 3 shows that the demonstrative structure figure of the trapping module of one embodiment of the invention.
Figure 4 shows that the detailed exemplary block diagram of trapping module shown in Figure 3.
Figure 5 shows that the exemplary flow chart of the processing spread-spectrum signal of one embodiment of the invention.
Embodiment
Fig. 2 has illustrated at the structure chart of the existing trapping module of a particular channel.Trapping module shown in Figure 2 comprises that 1023 parallel integral kernels from integral kernel 200-0 to integral kernel 200-1022 serial number, one produce the channel of C/A sign indicating number-N C/A sign indicating number generator 202, a local oscillator 204 and a search engine module 206 that produces carrier signal.Each integral kernel 200 is finished related operation with IF signal, local carrier signal, C/A sign indicating number as input.At integral kernel 200-0, related operation comprises the IF signal times with local carrier signal and C/A sign indicating number.The related operation result then is sent to search engine module 206.Search engine module 206 judges whether the related operation result exceeds a predetermined threshold and judge whether to find specific Doppler frequency shift and the phase shift of C/A sign indicating number.For finding the starting point of C/A sign indicating number, method commonly used is for the search of each C/A sign indicating number, the C/A sign indicating number to be moved 1/2 chip.At integral kernel 200-1, carry out similar related operation, the different C/A sign indicating numbers of just delivering to integral kernel 200-1 are moved 1/2 chip.1/2 chip offset module 208 is used for the C/A sign indicating number is moved 1/2 chip.As previously mentioned, a C/A sign indicating number cycle comprises 1023 chips.Therefore, for certain frequency, the C/A code phase search of finishing the whole cycle needs 2046 correlations computings.1023 integral kernels of Fig. 2 signal have covered the half period of C/A code phase search.Therefore, for covering the whole cycle of C/A code phase search, need carry out catching for twice to finish whole catching to the IF signal.
Though parallel correlator provides a kind of processing of catching of relative high speed, in the reality, be difficult to realize 1023 parallel integrators on the hardware.For reaching the parallel integration of equivalence, some prior aries or increase hardware size or select high related operation frequency.The invention provides the function that a kind of advantageous method realizes the parallel integrator of a large amount of equivalences, and required related operation frequency is lower, hardware size is less.For simplicity, mainly disclose the realization of parallel integrator of 1023 equivalences or parallel correlator here emphatically.Yet, it should be recognized by those skilled in the art that employing can realize the parallel integrator of any amount in the method for this detailed description.
Fig. 3 has illustrated the demonstrative structure figure of trapping module of the present invention.Intermediate frequency (IF) Signal Pretreatment unit 302 receives at least three signals: 306 and one of local reference signals (carrier signal) that 304, one of input signals (IF signal) are sent by signal generator (local oscillator) 310 are by sign indicating number clock generator (PRN yardage word control generator claims PRN sign indicating number NCO again) 312 clock signals of sending 308.Thereby the speed that IF Signal Pretreatment unit 302 is used for will importing IF signal 304 to the pre-integration of IF signal from sample rate conversion for than low rate.
As previously mentioned, the IF signal need multiply by local carrier signal and PRN sign indicating number at trapping module.Because the C/A sign indicating number did not change in the time period of 1/2 chip, therefore can earlier IF signal 304 be multiply by local carrier signal 306 in the time period and obtain pre-integral result at 1/2 chip, then more pre-integral result be multiply by the PRN sign indicating number.If the sample frequency of input IF signal 304 is 16.368MHZ, because the one-period of C/A sign indicating number is 1 millisecond, IF signal 304 comprises 8 data samplings in a data length of 1/2 chip.IF Signal Pretreatment unit 302 is used for 8 corresponding sampled data points points of 8 sampled datas of IF signal 304 and carrier signal 306 are multiplied each other, and the product addition is drawn a pre-integral result.Like this, 8 dot-product computings are just carried out with 1/2 spreading rate, and just the generation frequency of pre-integral result is 2.046MHZ.Because PRN yardage word control generator 312 produces C/A sign indicating number clock with 1/2 spreading rate, therefore can utilize PRN yardage word control generator 312 that the generation of pre-integral result is controlled at set rate, for example 1/2 spreading rate.An advantage of the present invention is that IF signal processing unit 302 can be converted to input signal the lower signal of frequency.When the preliminary treatment input signal produces with lower frequency, each block integral device just has the enough time to finish a plurality of related operations with time division way, rather than as only carrying out a related operation among Fig. 2, therefore, a plurality of related operations are shared same logical resource, will be described in detail below.
The pre-integral result that IF Signal Pretreatment unit 302 produces is divided into many groups, every group of pre-integral result that comprises predetermined quantity.The pre-integral result that IF signal processing unit 302 will be organized predetermined quantity more with predetermined space send to mutual parallel connection all block integral devices [314-0 ..., 314-7] in.For the pre-integral result of every group of predetermined quantity, each block integral device receives the corresponding sign indicating number section of the pre-integral result of this group predetermined quantity and the PRN sign indicating number that sign indicating number generator 316 produces simultaneously, and carries out a plurality of part correlation computings.Related operation of the present invention is a kind of inner product operation, and this inner product operation is by multiply by each pre-integral result each 1/2 chip and with the result of product addition and then produce inner product value.In one embodiment, IF Signal Pretreatment unit 302 can be with every group, for example, 33 pre-integral results send to the block integral device [314-0 ..., 314-7].In next group before 33 pre-integral results are ready to, each block integral device has 33 * (1/2 chip time span) time durations that 33 pre-integral results that receive are carried out the part correlation computing.If each part correlation computing is carried out with the frequency identical with sample frequency, as 16.368MHZ, each block integral device is finished 256 part correlation computings at least in 33 * (1/2 chip time span) time durations.Therefore, 4 block integral devices just are enough to carry out 1023 related operations.Because each pre-integral result comprises two components: one tunnel in-phase signal (I signal) and one tunnel orthogonal signalling (Q signal), the related operation of carrying out 1023 I signals and Q signal needs 2 component masses integrators, and a component masses integrator is handled one road signal.Therefore, 8 block integral devices have been provided among this embodiment.
Advantageously, the related operation frequency that adopts here is far below frequency that traditional correlator adopted.Certainly, the present invention also can adopt higher related operation frequency.In addition, IF Signal Pretreatment unit 302 and parallel block integral device [314-0, ..., 314-7] can be operated under the pipeline mode, that is to say, the block integral device [314-0 ..., 314-7] when handling the pre-integral result when last group of predetermined quantity, and IF Signal Pretreatment unit 302 produces the pre-integral result that next organizes predetermined quantity.
Yet, will be appreciated that the generation frequency of sample frequency, pre-integral result, related operation frequency, to send to the quantity of pre-integral result of block integral device and the number of block integral device all be relevant at every turn.It will be appreciated by those skilled in the art that these parameters can also be arranged to different values except value described herein.For example, the related operation frequency can be higher than 16.368MHZ, and the generation frequency of pre-integral result can be set to 1/4 spreading rate.In addition, the PRN sign indicating number is not limited to the C/A sign indicating number, also can adopt the PRN sign indicating number of other types.
First memory cell (dual-port SRAM) 320 is connected between control logic 318 and control and the coding module 322, as shown in Figure 3, is used for storage area related operation result and continuous integral result.Continuous integral is the computing that a kind of analog result with single related operation adds up in a period of time and then improves signal to noise ratio and enhancing receiver Detection of weak ability.Each block integral device can carry out continuous integral in tentation data length.
The control and coding module 322 processing that are connected between first memory cell 320 and second memory cell 324 are delivered to second memory cell 324 from the continuous integral result of first memory cell 320 and the result that will handle.Control and coding module 322 can be carried out following operation: to the continuous integral result encode, further processing signals and be used to strengthen the discontinuous integral operation of small-signal intensity.
Fig. 4 has illustrated the detailed structure view of Fig. 3 trapping module, and considers I signal and Q signal.Signal generator 410 produces two quadrature carrier signals: a sinusoidal signal and a cosine signal.Cosine signal obtains by the phase shift of offset of sinusoidal signal.Phase-shift operations is carried out by ∏/2 phase shift modules 434.IF signal pre-processing module 402 comprises two adder and multipliers (MAC) unit 430 and 432.The pre-integral operation result that pre-integral operation and generation contain in-phase component is carried out according to sinusoidal signal and input IF signal in first adder and multiplier (MAC) unit 430.The pre-integral operation result that pre-integral operation and generation contain quadrature component is carried out according to cosine signal and same input IF signal in second adder and multiplier (MAC) unit 432.Each MAC is the clock signal of receiving code clock generator (PRN sign indicating number NCO) 412 generations, and MAC 430 and 432 just produces pre-integral result with 2 times of PRN bit rates like this, just produces pre-integral result with 1/2 spreading rate.
Consider I signal and Q signal, two component masses integrators are respectively applied for handles I signal and Q signal.Block integral device 414-4,414-5,414-6 and 414-7 handle I road signal and finish 1023 related operations altogether, and each block integral device is carried out 256 related operations; And block integral device 414-0,414-1,414-2 and 414-3 processing Q road signal are finished 1023 related operations altogether, and each block integral device is carried out 256 related operations.For I road or Q road signal, because each block integral device operational mode is basic identical, the different C/A sign indicating number phase shifts that just send in each block integral device are 256 * (1/2 yard skew).
To be described based on a block integral device below.Block integral device 414-0 receives the pre-integral result (for example, 33 pre-integral results) of one group of predetermined quantity and comprises one section C/A sign indicating number of 33 1/2 chips.Parallel adder and multiplier among the block integral device 414-0 (parallel MAC) unit 436 can be in a clock cycle (being the inverse of related operation frequency) calculate inner product (also claiming the part correlation computing) between 33 pre-integral results and 33 the 1/2C/A sign indicating numbers, the part correlation operation result can also be added in the previous part correlation operation result.Previous part correlation operation result is the inner product between previous 33 pre-integral results and 33 the 1/2C/A chips, and 33 1/2C/A chip phase differ (256+33) * 1/2 chip with current C/A sign indicating number respectively.Clock frequency can be identical with sample frequency, for example, and foregoing 16.368M HZ or higher.Inner product is calculated and to be also referred to as the part correlation computing, because each in two input signals all is the part of signal period." parallel adder and multiplier " used herein is meant can executed in parallel multiplying and each MAC with these result of product summations, the part correlation operation result that can also add up.Block integral device 414-0 also comprises at least two memory register R0438 and the R1 440 that is connected between parallel MAC unit 436 and the control logic 418.Advantageously, two memory registers can be operated in pipeline system, so that alternately storage is from the previous part correlation operation result of first memory cell 420 and the current part correlation operation result of memory parallel MAC unit 436.The operation of two memory registers is by control logic 418 controls.
After the part correlation operation result produced, sign indicating number generator 416 was offset 1/2 chip with the C/A sign indicating number.The C/A sign indicating number is offset after 1/2 chip, and block integral device 414-0 begins next part correlation computing, and the C/A sign indicating number of same 33 pre-integral results and skew is added among the corresponding previous related operation result as input and with current part correlation operation result.Block integral device 414-0 repeats above-mentioned steps up to receiving 33 pre-integral results of next group.Because the time interval that continuous two groups 33 pre-integral results arrive is 264 clock cycle, promptly 33 * 8, for fixing 33 pre-integral results, each block integral device just has 256 part correlation computings of enough Time Calculation.Block integral device 414-0 receives 33 pre-integral results of many groups continuously up to obtaining 256 complete related operation results.
256 related operations are carried out in a block integral device with time division way, and such 256 related operations just can be shared a parallel MAC unit.Therefore, a block integral device can be thought and is equivalent to 256 correlators, thereby reduce required logical resource.In addition, the only is-symbol computing of multiplying in the related operation that parallel MAC unit calculates because the C/A sign indicating number have only+1 and-1 two states.Will be appreciated that these advantages should give the credit to the pre-integral processing of pre-integral unit 402 execution of IF signal and by the pre-integral unit 402 of IF signal these pre-integral results are divided into a plurality of piecemeals.
Sign indicating number generator 416 comprises a PRN sign indicating number generator 442 that produces parallel C/A sign indicating number with twice C/A spreading rate.Produce the clock signal control that speed is sent by PRN sign indicating number NCO 412.Each C/A sign indicating number that sends to the different block integral devices on I road or Q road all has different starting points.Yet the block integral device on the block integral device on I road and corresponding with it Q road receives has same code C/A sign indicating number mutually.For example, block integral device 414-0 receives the identical C/A sign indicating number that does not have phase shift with 414-4.It is 256 * (1/2 chip offset) identical C/A sign indicating number that block integral device 414-1 and 414-5 receive phase shift.It is 2 * 256 * (1/2 chip offset) identical C/A sign indicating number that block integral device 414-2 and 414-6 receive phase shift.It is 3 * 256 * (1/2 chip offset) identical C/A sign indicating number that block integral device 414-3 and 414-7 receive phase shift.
Respective components among control logic 418 among Fig. 4, first memory cell (dual-port SRAM) 420, control and coding module 422 and second memory cell (dual-port SRAM) 424 and Fig. 3 is similar.Therefore, for simplicity's sake, just repeat no more here.
Fig. 5 has illustrated to handle the flow chart 500 of spread-spectrum signal in the circuit with a plurality of block integral devices, wherein this circuit adopts one with the digitized input signal of predetermined sampling frequency, a local reference signal and a Pseudo-Random Noise Code.In step 502, after IF Signal Pretreatment unit received a digitized signal, in step 504, IF Signal Pretreatment unit produced pre-integral result according to received signal and local reference signal with set rate (for example, twice PRN spreading rate).When producing pre-integral result, in step 506, IF Signal Pretreatment unit sends to the pre-integral result of one group of predetermined quantity (for example 33) in each block integral device.When each block integral device received the pre-integral result of this group predetermined quantity, in step 508, each block integral device also receives had the Pseudo-Random Noise Code of code phase separately.In step 510, the pre-integral result of one section Pseudo-Random Noise Code that each block integral device will receive and this group predetermined quantity (for example 33) carries out the part correlation computing as input.In step 512, after in each block integral device, obtaining the part correlation operation result, in step 514, partial correlation results is added in the previous partial correlation results, and wherein previous partial correlation results is according to pre-integral result and one section corresponding Pseudo-Random Noise Code of last group of predetermined quantity obtain earlier.After each block integral device was finished the part correlation computing, in step 516, the Pseudo-Random Noise Code that sends in each block integral device was moved the precalculated position.After the Pseudo-Random Noise Code skew,, detect the pre-integral result whether each block integral device receives next group predetermined quantity in step 518.If do not receive the pre-integral result of next group predetermined quantity in each block integral device, arrive step 516 with regard to repeating step 510, otherwise execution in step 520 promptly detects whether obtain a plurality of complete related operation results in each block integral device.If do not obtain a plurality of complete related operation results in each block integral device, arrive step 518 with regard to repeating step 506, otherwise execution in step 522 is promptly to the complete further signal processing of related operation result.
In the enforcement, gps signal is received by the antenna 102 that is connected to receiver 100, and by tuner 104 it is converted to intermediate frequency from original frequency.Intermediate-freuqncy signal then transfers digital signal by analog-digital converter 106 to predetermined sampling frequency.Be sent to IF Signal Pretreatment unit 103 through digitized digital IF signal.IF Signal Pretreatment unit 103 is carried out IF signal and local carrier signal pre-integral operation and is produced pre-integral result with set rate as input.The pre-integral result of the many groups predetermined quantity that is produced by IF Signal Pretreatment unit 103 is received continuously by a plurality of parallel block integral devices 314.Pre-integral result for one group of predetermined quantity, thereby the pre-integral result that each block integral device 314 will be organized predetermined quantity carries out the part correlation computing with the PRN sign indicating number of multistage after skew respectively obtains a plurality of part correlation operation results, receives the pre-integral result of next group predetermined quantity up to block integral device 314.Each block integral device 314 continues to receive the many group pre-integral results of predetermined quantity and the part correlation operation result that adds up, up to obtaining a plurality of complete related operation results.Results of intermediate calculations is stored in first memory cell 320.For in each block integral device, obtaining a plurality of complete related operation results, control logic 318 is used for reading a previous part correlation operation result from first memory cell 320, with current part correlation operation result and previous part correlation operation result addition, and modified previous partial correlation results write first memory cell 320 again.In addition, block integral device 314 is also carried out the continuous integral computing to improve signal to noise ratio.Continuous integral result is sent to control and coding module 322 is done further processing, for example to continuous integral result coding, further processing signals and carry out discontinuous integral operation.Second memory cell 324 is used to store the result from control and coding unit 322.
Method in Fig. 5 context can also be carried out a series of machine readable instructions by the arithmetic section of for example computing equipment and realize.Though steps in sequence is wherein listed, this method also can be implemented with different orders or as the event-driven process.These instructions can be stored in various types of one-level, secondary or three grades of media that have signal or storage.This medium comprises, for example, and the accessible RAM (not shown) of the element of computing equipment or be stored in RAM in the computer equipment element.The instruction that no matter is included in RAM, disk or other secondary storage media can be stored in the various machine-readable data storage media, DASD memory (as conventional " hard disk drive " or RAID array) for example, tape, electronically erasable read only memory are (for example, ROM, EPROM or EEPROM), flash card, light storage device (for example, CD-ROM, WORM, DVD, digital optical tape), tape punch card or comprise numeral and other suitable data storage mediums of analogue transmission medium.
Here term of Cai Yonging and form of presentation just are used for describing, and should not be limited to these terms and statement.Use these terms and statement and do not mean that the equivalent features of getting rid of any signal and description (or wherein part), will be appreciated that the various modifications that may exist also should be included in the claim scope.Other modifications, variation and replacement also may exist.Accordingly, claim should be considered as covering all these equivalents.
Claims (43)
1, a kind of method of handling spread-spectrum signal, it is characterized in that: this processing method is carried out at a circuit with a plurality of block integral devices, this circuit uses one with the digitized input signal of predetermined sampling frequency, a local carrier signal and a Pseudo-Random Noise Code, and described method comprises step:
A) produce pre-integral result according to input signal and local carrier signal with set rate;
B) the pre-integral result with one group of predetermined quantity sends in each block integral device;
C) reception has the Pseudo-Random Noise Code of code phase separately in each block integral device;
D) according to this group predetermined quantity pre-integral result and one section this Pseudo-Random Noise Code operating part related operation in each block integral device;
E) in each block integral device, from the part correlation computing, obtain the part correlation operation result;
F) if there is previous related operation result, then the part correlation operation result is added on the previous partial arithmetic result, wherein previous related operation result is according to pre-integral result and one section corresponding Pseudo-Random Noise Code of last group of predetermined quantity obtain earlier;
G) Pseudo-Random Noise Code is offset the precalculated position;
H) repeating step d) to g) be sent in each block integral device up to next pre-integral result of organizing predetermined quantity; With
I) repeating step b) to h) in each block integral device, obtain a plurality of complete related operation results, wherein complete related operation result is used for further signal processing;
Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
2, the method for processing spread-spectrum signal according to claim 1 is characterized in that: described method further comprises:
Pre-integral result is divided into in-phase component and quadrature component; And difference execution in step b) to i).
3, the method for processing spread-spectrum signal according to claim 1 is characterized in that: the frequency of carrying out described part correlation computing is equal to or greater than described sample frequency.
4, the method for processing spread-spectrum signal according to claim 1 is characterized in that: described input signal is the intermediate-freuqncy signal that is transferred to by spread-spectrum signal.
5, the method for processing spread-spectrum signal according to claim 1 is characterized in that: described Pseudo-Random Noise Code is thick catch code, and thick catch code comprises 1023 chips, and the cycle of thick catch code is 1 millisecond.
6, the method for processing spread-spectrum signal according to claim 1 is characterized in that: described set rate is the twice of pseudorandom chip speed.
7, the method for processing spread-spectrum signal according to claim 6 is characterized in that: described pseudorandom chip speed is slightly to catch spreading rate.
8, the method for processing spread-spectrum signal according to claim 1 is characterized in that: the step of the pre-integral result of described generation comprises step:
Each data point of input signal be multiply by each data point separately of local carrier signal; With
In a data length, each result of product is produced a pre-integral result mutually.
9, the method for processing spread-spectrum signal according to claim 8 is characterized in that: described data length is half of described pseudo noise code leaf length, and described data length comprises a plurality of data points, and the number of a plurality of data points depends on described predetermined sampling frequency.
10, the method for processing spread-spectrum signal according to claim 1 is characterized in that: described precalculated position is the phase deviation of half described pseudorandom chip.
11, a kind of equipment of handling with the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described equipment comprises:
An intermediate-freuqncy signal pretreatment unit that produces pre-integral result according to input signal and local carrier signal with set rate; With
The parallel block integral device that a plurality of and described intermediate-freuqncy signal pretreatment unit is communicated by letter, each block integral device receives the pre-integral result of many group predetermined quantities continuously, pre-integral result for every group of quantity, thereby the pre-integral result that each block integral device will be organized predetermined quantity carries out the part correlation computing with the Pseudo-Random Noise Code of multistage after through skew respectively obtains a plurality of part correlation operation results, delivers in the described block integral device up to pre-integral result of next group predetermined quantity;
Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
12, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described equipment also comprises:
A control logic that is connected to a described a plurality of block integral device and a memory cell, wherein said control logic reads previous part correlation operation result from described memory cell, current part correlation operation result is added on the previous partial arithmetic result, more modified previous part correlation operation result is write described memory cell.
13, processing according to claim 11 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described equipment also comprises a signal generator that produces the local carrier signal of two quadratures, and described signal generator is communicated by letter with described intermediate-freuqncy signal pretreatment unit.
14, processing according to claim 13 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described intermediate-freuqncy signal pretreatment unit also comprises:
A calculating contains first multiplier accumulator unit of the pre-integral result of in-phase component, first multiplier accumulator unit multiplies each other each data point of input signal and each corresponding data point of two one of them signals of quadrature local carrier signal in a data length, and with each result of product addition so that produce a pre-integral result that contains in-phase component;
A calculating contains second multiplier accumulator unit of the pre-integral result of quadrature component, second multiplier accumulator unit multiplies each other each data point of input signal and each corresponding data point of another local carrier signal in a data length, and with each result of product addition so that produce a pre-integral result that contains quadrature component.
15, processing according to claim 14 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described data length is half of described pseudo noise code leaf length, described data length comprises a plurality of data points, and the number of data point depends on described predetermined sampling frequency.
16, processing according to claim 14 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described a plurality of block integral devices are divided into two groups, the described pre-integral result that contains in-phase component of first group of received, the described pre-integral result that contains quadrature component of second group of received.
17, processing according to claim 11 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described equipment further comprises a sign indicating number clock generator that links to each other with described intermediate-freuqncy signal pretreatment unit, and described sign indicating number clock generator is controlled described pre-integral result and produced with set rate.
18, processing according to claim 17 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described equipment further comprises a sign indicating number generator that links to each other with the sign indicating number clock generator, and described sign indicating number generator is parallel to be produced and a plurality ofly have the Pseudo-Random Noise Code of corresponding code phase and each Pseudo-Random Noise Code with corresponding code phase is sent in the corresponding block integral device.
19, processing according to claim 18 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described sign indicating number generator can be offset the precalculated position with Pseudo-Random Noise Code, and each skew for Pseudo-Random Noise Code, the corresponding sub-block integrator will be organized the pre-integral result of predetermined quantity and the Pseudo-Random Noise Code operating part related operation of skew, obtain one of them result in described a plurality of part correlation operation result.
20, processing according to claim 19 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described precalculated position is the phase deviation of half described pseudorandom chip.
21, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described input signal transfers digital signal with described predetermined sampling frequency to by analog-digital converter.
22, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: the frequency of carrying out described part correlation computing is equal to or greater than described sample frequency.
23, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described Pseudo-Random Noise Code is thick catch code, and thick catch code comprises 1023 chips, and the cycle of thick catch code is 1 millisecond.
24, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described set rate is the twice of pseudorandom chip speed.
25, processing according to claim 11 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described each block integral device further comprises a parallel multiplier accumulator unit, and described parallel multiplier accumulator unit is according to pre-integral result and corresponding one section Pseudo-Random Noise Code operating part related operation of one group of predetermined quantity.
26, processing according to claim 12 is with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency, it is characterized in that: described each block integral device further comprises at least two memory registers that are connected between described parallel multiplier accumulator unit and the described control logic, two memory registers are alternately stored from the previous part correlation operation result of memory cell and the current part correlation operation result of storage, described control logic is controlled the operation of described at least two memory registers of each block integral device, and described at least two memories series connection connects.
27, processing according to claim 12 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described memory cell can the storage computation result.
28, processing according to claim 11 is characterized in that with the equipment of the digitized spread-spectrum signal of predetermined sampling frequency: described previous related operation result is according to pre-integral result and corresponding one section Pseudo-Random Noise Code of last group of predetermined quantity obtain earlier.
29, a kind of receiver of receiving spread frequency signal is characterized in that: described receiver comprises:
A tuner that spread-spectrum signal is converted to intermediate frequency from original frequency;
An analog-digital converter that is connected to tuner, described analog-digital converter is converted to digital input signals with intermediate-freuqncy signal with predetermined sampling frequency;
A memory cell;
An equipment that is connected to analog-digital converter and is used to handle spread-spectrum signal comprises:
An intermediate-freuqncy signal pretreatment unit that produces pre-integral result according to described digital input signals and local carrier signal with set rate;
The parallel block integral device that a plurality of and described intermediate-freuqncy signal pretreatment unit is communicated by letter, each block integral device receives the pre-integral result of many group predetermined quantities continuously, pre-integral result for every group of predetermined quantity, thereby the pre-integral result that each block integral device will be organized predetermined quantity carries out the part correlation computing with the Pseudo-Random Noise Code of multistage after skew respectively obtains a plurality of part correlation operation results, delivers in the described block integral device up to pre-integral result of next group predetermined quantity; With
A control logic that is connected to described memory cell and described a plurality of block integral devices, wherein control logic reads previous part correlation operation result from described memory cell, current part correlation operation result is added on the previous partial arithmetic result, more modified previous part correlation operation result is write described memory cell;
Wherein, described part correlation computing comprises multiplication and add operation, the computing of described multiplying is-symbol.
30, the receiver of receiving spread frequency signal according to claim 29, it is characterized in that: described equipment further comprises a signal generator that produces the local carrier signal of two quadratures, and described signal generator is communicated by letter with described intermediate-freuqncy signal pretreatment unit.
31, the receiver of receiving spread frequency signal according to claim 30 is characterized in that: described intermediate-freuqncy signal pretreatment unit further comprises:
A calculating contains first multiplier accumulator unit of the pre-integral result of in-phase component, first multiplier accumulator unit multiplies each other each data point of input signal and each corresponding data point of two one of them signals of quadrature local carrier signal in a data length, and with each result of product addition so that produce a pre-integral result that contains in-phase component;
A calculating contains second multiplier accumulator unit of the pre-integral result of quadrature component, second multiplier accumulator unit multiplies each other each data point of input signal and each corresponding data point of another local carrier signal in a data length, and with each result of product addition so that produce a pre-integral result that contains quadrature component.
32, the receiver of receiving spread frequency signal according to claim 31 is characterized in that: described data length is half of described pseudo noise code leaf length, and described data length comprises a plurality of data points, and the number of data point depends on described predetermined sampling frequency.
33, the receiver of receiving spread frequency signal according to claim 31, it is characterized in that: described a plurality of block integral devices are divided into two groups, the described pre-integral result that contains in-phase component of first group of received, the described pre-integral result that contains quadrature component of second group of received.
34, the receiver of receiving spread frequency signal according to claim 29, it is characterized in that: described equipment further comprises a sign indicating number clock generator that links to each other with described intermediate-freuqncy signal pretreatment unit, and described sign indicating number clock generator is controlled described pre-integral result and produced with set rate.
35, the receiver of receiving spread frequency signal according to claim 34, it is characterized in that: described equipment further comprises a sign indicating number generator that links to each other with the sign indicating number clock generator, and described sign indicating number generator is parallel to be produced and a plurality ofly have the Pseudo-Random Noise Code of corresponding code phase and each Pseudo-Random Noise Code with corresponding code phase is sent in the corresponding block integral device.
36, the receiver of receiving spread frequency signal according to claim 35, it is characterized in that: described sign indicating number generator can be offset the precalculated position with Pseudo-Random Noise Code, and each skew for Pseudo-Random Noise Code, the corresponding sub-block integrator will be organized the pre-integral result of predetermined quantity and the Pseudo-Random Noise Code operating part related operation of skew, obtain one of them result in described a plurality of part correlation operation result.
37, the receiver of receiving spread frequency signal according to claim 36 is characterized in that: described precalculated position is the phase deviation of half described pseudorandom chip.
38, the receiver of receiving spread frequency signal according to claim 29 is characterized in that: the frequency of carrying out described part correlation computing is equal to or greater than described sample frequency.
39, the receiver of receiving spread frequency signal according to claim 29 is characterized in that: described Pseudo-Random Noise Code is thick catch code, and thick catch code comprises 1023 chips, and the cycle of thick catch code is 1 millisecond.
40, the receiver of receiving spread frequency signal according to claim 29 is characterized in that: described set rate is the twice of pseudorandom chip speed.
41, the receiver of receiving spread frequency signal according to claim 29, it is characterized in that: described each block integral device further comprises a parallel multiplier accumulator unit, and described parallel multiplier accumulator unit is according to pre-integral result and corresponding one section Pseudo-Random Noise Code operating part related operation of one group of predetermined quantity.
42, according to the receiver of the described receiving spread frequency signal of claim 41, it is characterized in that: described each block integral device further comprises at least two memory registers that are connected between described parallel multiplier accumulator unit and the described control logic, two memory registers are alternately stored from the previous part correlation operation result of memory cell and the current part correlation operation result of storage, described control logic is controlled the operation of described at least two memory registers of each block integral device, and described at least two memories series connection connects.
43, the receiver of receiving spread frequency signal according to claim 29 is characterized in that: described previous related operation result is according to pre-integral result and one section corresponding Pseudo-Random Noise Code of last group of predetermined quantity obtain earlier.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100815465A CN100438360C (en) | 2005-06-30 | 2005-06-30 | Method and equipment for realizing parallel correlator utilizing block integral in spread spectrum communication |
| HK07107052.3A HK1099614A1 (en) | 2005-06-30 | 2007-07-03 | Method and apparatus for processing spread spectrum signals, and receiver for receiving spread spectrum signals |
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| CNB2005100815465A CN100438360C (en) | 2005-06-30 | 2005-06-30 | Method and equipment for realizing parallel correlator utilizing block integral in spread spectrum communication |
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| CN100438360C true CN100438360C (en) | 2008-11-26 |
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| HK (1) | HK1099614A1 (en) |
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| CN101881818B (en) * | 2009-05-06 | 2012-03-07 | 中国科学院微电子研究所 | Device and method for rapidly detecting feeble signals |
| CN103018753B (en) * | 2012-08-09 | 2014-11-05 | 江苏科技大学 | GPS (Global Position System) signal digital correlator |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1432218A (en) * | 2000-05-16 | 2003-07-23 | 皇家菲利浦电子有限公司 | Method of despreading spread spectrum signal |
| EP1421707A2 (en) * | 2001-08-16 | 2004-05-26 | Motorola, Inc. | Spread spectrum receiver architectures and methods therefor |
| CN2865143Y (en) * | 2005-06-30 | 2007-01-31 | 凹凸科技（中国）有限公司 | Equipment processing spread-spectrum signal and receiver receiving spread-spectrum signal |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1432218A (en) * | 2000-05-16 | 2003-07-23 | 皇家菲利浦电子有限公司 | Method of despreading spread spectrum signal |
| EP1421707A2 (en) * | 2001-08-16 | 2004-05-26 | Motorola, Inc. | Spread spectrum receiver architectures and methods therefor |
| CN2865143Y (en) * | 2005-06-30 | 2007-01-31 | 凹凸科技（中国）有限公司 | Equipment processing spread-spectrum signal and receiver receiving spread-spectrum signal |
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| HK1099614A1 (en) | 2007-08-17 |
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