CN100438036C - Memory device and method for fabricating the same - Google Patents
Memory device and method for fabricating the same Download PDFInfo
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- CN100438036C CN100438036C CNB2005100644419A CN200510064441A CN100438036C CN 100438036 C CN100438036 C CN 100438036C CN B2005100644419 A CNB2005100644419 A CN B2005100644419A CN 200510064441 A CN200510064441 A CN 200510064441A CN 100438036 C CN100438036 C CN 100438036C
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
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- 238000004519 manufacturing process Methods 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 244000287680 Garcinia dulcis Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
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- 239000012535 impurity Substances 0.000 description 1
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- 238000001764 infiltration Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 150000003658 tungsten compounds Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.
Description
Technical field
The present invention relates to a kind of memory device and manufacture method thereof, and more specifically, relate to a kind of memory device and manufacture method thereof that improves data hold time.
Background technology
Because semiconductor device is by miniaturization day by day, each figure molded dimension is also reduced gradually.Especially in memory device such as dynamic random access memory (DRAM) device, because it is integrated on a large scale, the reducing of the interior transistor size in its gate electrode length and born of the same parents district (cell region) acutely reduces pro rata, and as the result that the gate electrode size reduces, the knot of source and leakage plays an important role to electric field and the electromotive force that is applied to transistor bodies in the born of the same parents district.
Fig. 1 is the profile of explanation conventional memory device structure.
As shown in the figure, the field oxide layer 120 that is used for the spacer assembly element is formed in the presumptive area of substrate 110.Then, gate insulation layer 130, first grid conductive layer 140, second grid conductive layer 150 and grid hard mask layer 160 are formed on the substrate 110 successively, and are subjected to grid mask process and etch processes successively, thereby obtain a plurality of grid structures 155.
Then, impurity is injected to form a plurality of bit line contact knot 170A and a plurality of storage node contact knot 170B by ion, afterwards, forms sept (spacer) 171 on each sidewall of grid structure 155.Then, form a plurality of bit line contact plug 190A that connect bit line contact knot 170A and a plurality of storage node contact plug 190B that connect storage node contact knot 170B.This bit line contact plug 190A and this storage node contact plug 190B are respectively applied for bit line and storage node and are connected.It should be noted that Fig. 1 only illustrates single bit line contact knot and single bit line contact plug.
But conventional memory device has the problem of short-channel effect, and promptly because gate electrode is shortened, channel region is subject to from the depletion layer of grid structure, source and drain junction, electric field, reaches the influence of the voltage that current potential provided.As the result of this disadvantageous short-channel effect, threshold voltage sharply reduces, and causes being difficult to the threshold voltage of control store device thus.
Moreover, because of memory device miniaturization, so must inject bit line contact knot 170A and storage node contact knot 170B with high concentration ion.Yet because for the excessive ion that obtains high-dopant concentration injects, the marginal zone A of storage node contact knot 170B will have high-caliber electric field in the born of the same parents district, therefore, the junction leakage of partly locating at the knot of storage node contact knot 170B increases.The increase of this kind junction leakage causes that data hold time reduces, that is the recovery characteristics of memory device is degenerated.
Summary of the invention
Therefore, the present invention's purpose provides a kind of memory device and manufacture method thereof that can increase data hold time by the junction leakage that minimizing produces at storage node contact knot place.
According to an aspect of the present invention, provide a kind of memory device, it comprises: fluted substrate is provided; Be formed on the bit line contact knot of beneath trenches; Be formed on the outer a plurality of storage node contact knots of groove; And a plurality of grid structures, each grid structure is formed on bit line contact knot contacts substrate between tying with a storage node on.
According to a further aspect in the invention, provide a kind of memory device, it comprises: fluted substrate is provided; Be formed on the first contact knot of beneath trenches; Be formed on the outer a plurality of second contact knots of groove; A plurality of grid structures, each grid structure are formed on and are arranged at the first contact knot and contact with one second on the substrate between tying; Tie first contact plug of formation in first contact by filling the space that is produced between the grid structure; And a plurality of second contact plugs of tying formation by filling the space that is produced between the grid structure in second contact.
In accordance with a further aspect of the present invention, provide a kind of method that is used to make memory device, included step is: the etching part substrate is to obtain groove; Form a plurality of grid structures, make each part of grid structure be set in the groove; Thereby use the grid structure to carry out the ion injection and handle the first contact knot and the outer a plurality of second contact knots of formation groove that form beneath trenches as mask; Reach in first contact and tie formation first contact plug and tie a plurality of second contact plugs of formation in corresponding contact.
Description of drawings
By the description of following given preferred embodiment and in conjunction with the accompanying drawings, above-mentioned and other purpose of the present invention and feature will be better understood, wherein:
Fig. 1 is the profile of explanation conventional memory device structure.
Fig. 2 is for illustrating the profile of the memory device structures of making according to first embodiment of the invention.
Fig. 3 A makes the profile of memory device method according to first embodiment of the invention for explanation to 3F.
Fig. 4 is the profile of explanation according to the memory device structures of second embodiment of the invention.
Fig. 5 is the profile of explanation according to the memory device structures of third embodiment of the invention.
Fig. 6 is the profile of explanation according to the memory device structures of fourth embodiment of the invention.
Fig. 7 A makes the profile of memory device method according to fourth embodiment of the invention for explanation to 7G.
Fig. 8 is the profile of explanation according to the memory device structures of fifth embodiment of the invention.
Fig. 9 is the profile of explanation according to the memory device structures of sixth embodiment of the invention.
Embodiment
To describe memory device and manufacture method thereof according to the preferred embodiment of the invention in conjunction with the accompanying drawings in detail.
Fig. 2 is the profile of explanation according to the memory device structures of first embodiment of the invention.
As shown in the figure, field oxide layer 220 is formed in the substrate 210, and forms groove 200 in the presumptive area of substrate.The substrate 210 that is arranged in groove 200 belows is formed with the first contact knot 270A, is formed with a plurality of second contact knot 270B and be arranged in groove 200 outer substrates 210.It should be noted,, only illustrate the single first contact knot 270A among Fig. 2 though form many first contact knot 270A.
A plurality of grid structures 255 are formed on contacting on each part of tying between the 270B at the first contact knot 270A and second of substrate 210.Herein, each grid structure comprises first insulating barrier 230, polysilicon layer 240, metal level 250 and is used for second insulating barrier 260 of hard mask.Moreover each part of selecteed grid structure 255 is set in the groove 200, and the polysilicon layer 240 of those grid structures 255 is caved in groove 200 formation place with metal level 250.
Be formed with sept 271 on grid structure 255 each sidewall.The first contact plug 290A is formed on the first contact knot 270A and goes up and fill the space that is produced between the grid structure 255 that is formed on the groove 200.A plurality of second contact plug 290B are respectively formed on the second contact knot 270B, and fill the corresponding space that is produced between the grid structure 255 that is formed on outside the groove 200.
Although not explanation, bit line is connected to the first contact knot 270A via the first contact plug 290A, and storage node is connected to the second contact knot 270B via the second contact plug 290B.That is the first contact plug 290A and the second contact plug 290B are respectively bit line contact plug and storage node contact plug, and 270A is tied in first contact and the second contact knot 270B is respectively that bit line contact knot contacts knot with storage node.
As mentioned above, according to the made memory device of first embodiment of the invention, transistorized bit line contact knot is formed in the groove (trench) in the born of the same parents district, and storage node contact knot then is formed on outside the groove.Many raceway grooves (channel) are formed between per two bit lines contact knot and the storage node contact knot.Therefore, the sidewall of groove constitutes raceway groove, and the result has prolonged transistorized channel length in the born of the same parents district.Compare the increase between per two storage nodes contact knot and the channel region with conventional memory device.Thereby the level of drain current of storage node contact knot reduces, thereby has increased data hold time.
Fig. 3 A makes the profile of the method for memory device according to first embodiment of the invention for explanation to 3F.Herein, the same reference numbers described in Fig. 2 also is used in these figure.
As shown in Figure 3A, field oxide layer 220 is formed on the silicon-based substrate 210.
Shown in Fig. 3 B, the predetermined portions of substrate 210 is selectively etched to form groove 200.Though the depth D of groove 200 changes according to design rule, the degree of depth of groove 200 is preferably the scope to about 150nm at about 20nm.
Shown in Fig. 3 C, first insulating barrier of being made by Si oxide (silicon oxide) 230 is formed on the top substrat structure of being finished, and forms polysilicon layer 240 and metal level 250 above it in regular turn.At this moment, polysilicon layer 240 has the recessed shape consistent with the profile of groove 200.
Shown in Fig. 3 D, the material that is selected from metal and metal silicide by use forms metal level 250 on polysilicon layer 240.At this moment, has sunk part at polysilicon layer 240 recess metal levels.Then, on metal level 250, be formed for second insulating barrier 260 of hard mask.Usually, second insulating barrier 260 is to be made by silicon nitride.
Shown in Fig. 3 E, via grid mask process and etch processes, first insulating barrier 230, polysilicon layer 240, metal level 250 and second insulating barrier 260 be by the selectivity etching, thereby obtain a plurality of grid structures 255.In order to recover during the etching the damage of substrat structure and to improve the characteristic of first insulating barrier 230, can implement to reoxidize processing.Afterwards, utilize grid structure 255 to carry out ion as mask and inject to handle, forming the first contact knot 270A at the substrate 210 that is positioned at below the groove 200, and 270B are tied in 210 formation a plurality of second of the substrate being positioned at groove 200 outside.
Shown in Fig. 3 F, on each sidewall of grid structure 255, be formed with sept 271.At this moment, sept 271 is to use nitride or oxide to form.Then, be formed for the conductive layer of contact plug above grid structure 255, it is applied CMP continuously and is handled, till conductive layer appears.After CMP handles, on the first contact knot 270A, form the first contact plug 290A, simultaneously, on the second contact knot 270B, form a plurality of second contact plug 290B.Although the single first contact knot 270A and the first contact plug 290A be it should be noted that by graphic extension a plurality of first contact knot 270A and first contact plug 290A are arranged.
Though not graphic extension, the first contact knot 270A is connected with bit line via the first contact plug 290A, and the second contact knot 270B is connected with storage node via the second contact plug 290B.But the first contact knot 270A and the second contact knot 270B can be connected with bit line and storage node respectively under the situation of not utilizing the first contact plug 290A and the second contact plug 290B.
According to the first embodiment of the present invention, the first contact knot 270A that is connected with bit line is formed in the substrate in the groove 200, so the sidewall of groove 200 has constituted transistorized channel region in the born of the same parents district.
Fig. 4 is the profile of explanation according to the memory device structures of second embodiment of the invention.
, comprise identical configuration element described in Fig. 2 herein, therefore, will be omitted about the detailed description of this configuration element according to the memory device of second embodiment.The made memory device difference of memory device that foundation second embodiment is made and foundation first embodiment is: the sidewall B of groove 300 is formed the surface perpendicular to the sunk part of substrate 310, and a plurality of grid structures 355, the first contact knot 370A and the second contact knot 370B are provided so that the part of substrate 310 at the sidewall B place of being set up of groove 300 is arranged to be located at the center of each channel region.
Fig. 5 is the profile of explanation according to the memory device structures of third embodiment of the invention.
, comprise identical configuration element described in Fig. 2 herein, therefore, will be omitted about the detailed description of this configuration element according to the memory device of third embodiment of the invention.Memory device that foundation the 3rd embodiment makes and memory device difference shown in Figure 2 are: the sidewall C forward of groove 400 tilts, that is is narrowing down when extend the bottom of groove 400.
Fig. 6 is the profile of explanation according to the memory device structures of fourth embodiment of the invention.
As shown in the figure, be formed with field oxide 620 in the substrate 610, groove 600 is formed in the presumptive area of substrate 610.Be formed with the first contact knot 670A in the substrate 610 of groove 600 belows, simultaneously, a plurality of second contact knot 670B are formed on the substrate 610 that is arranged in outside the groove 600.It should be noted, although be formed with many first contact knot 670A, the single first contact knot 670A of a graphic extension among Fig. 6.
A plurality of grid structures 655 are formed on the each several part that is arranged at the substrate 610 between the first contact knot 670A and the second contact knot 670B.Herein, each grid structure 655 comprises polysilicon layer 640A, the metal level 650 of first insulating barrier 630, complanation and is used for second insulating barrier 660 of hard mask.Moreover each part of the grid structure 655 through selecting is set in the groove 600.Sept 671 is formed on each sidewall of grid structure 655.The first contact plug 690A is formed on the first contact knot 670A and goes up filling part simultaneously and be arranged on the space that is produced between the grid structure 655 in the groove 600.A plurality of second contact plug 690B are formed on the corresponding second contact knot 670B and fill the corresponding space that is produced between the grid structure 655 that is formed on outside the groove 600 simultaneously.
Though not graphic extension, bit line are to contact knot 670A with first via the first contact plug 690A to be connected, and storage node is to contact knot 670B with second via the second contact plug 690B to be connected.That is the first contact plug 690A and the second contact plug 690B are respectively bit line contact plug and storage node contact plug, and 670A is tied in first contact and the second contact knot 670B is respectively that bit line contact knot and storage node contact knot.
As mentioned above, according to the memory device that fourth embodiment of the invention is made, transistorized bit line contact knot is formed in the groove in the born of the same parents district, and the knot of storage node contact simultaneously is formed on outside the groove.Many raceway grooves are formed between per two bit lines contact knot and the storage node contact knot.Therefore, the sidewall of groove becomes the part of raceway groove, the result, and transistorized channel length is extended in the born of the same parents district.Compare with conventional memory device, the distance between per two storage nodes contact knot and the channel region increases.Thereby, reduced the level of drain current that the storage node contact is tied, so increased data hold time.
Fig. 7 A makes the profile of memory device method according to fourth embodiment of the invention for explanation to 7G.Herein, the same reference numbers described in Fig. 6 is used to identical configuration element among these figure.
Shown in Fig. 7 A, on silicon-based substrate 610, form field oxide layer 620.
Shown in Fig. 7 B, the predetermined portions of substrate 610 is selectively etched to form groove 600.Though the depth D of groove 600 changes according to design rule, the depth D of groove 600 preferably at about 20nm in the 150nm scope.
Shown in Fig. 7 C, first insulating barrier of being made by Si oxide 630 is formed on the above-mentioned substrat structure of finishing, and forms polysilicon layer 640 thereon.Preferably, the thickness of polysilicon layer 640 is equal to or less than approximately
At this moment, polysilicon layer 640 has and the consistent recessed shape of groove 600 profiles.That is polysilicon layer 640 has sunk part, and it causes subsequently the metal level that is formed being caved at the same position place that polysilicon layer 640 is caved in.
But, because the characteristic of the metal that uses has the space to be produced, so the polymer that is produced in etch processes subsequently will infiltrate in this space.As a result, the infiltration of polymer may hinder and etchedly effectively carry out.Be head it off, in the first embodiment of the present invention, proposed a kind of diverse ways, will be described in detail institute's proposition method in conjunction with the accompanying drawings.
Shown in Fig. 7 D, before forming metal level on the polysilicon layer 640, carry out chemico-mechanical polishing (CMP) earlier and handle with removal groove 600, thus the polysilicon layer 640A of acquisition complanation.At this moment, the polishing pad that is used for above-mentioned CMP processing is to be made by high molecular polymer, and the average-size of polishing particles is preferably in about 10nm arrives about 1000nm scope.Moreover the surface of polishing pad forms sponge structure, and its bore dia is less than about 100 μ m, and the concentration range of slurry (slurry) polishing particles is preferably about 0.5 percentage by weight to 5 percentage by weights.
Shown in Fig. 7 E, be formed on the polysilicon layer 640A of complanation based on the above-mentioned metal level 650 of metal or metal silicide.Especially, metal level preferably uses the material that is selected from tungsten or tungsten compound to form.On metal level 650 be formed for second insulating barrier 660 of hard mask thereafter.Typically, second insulating barrier 660 is made by the nitride of silicon.
Shown in Fig. 7 F, via grid mask process and etch processes first insulating barrier 630, complanation polysilicon layer 640A, metal level 650 and second insulating barrier 660 are carried out optionally etching, thereby obtain a plurality of grid structures 655.In order to recover in etch processes the damage of substrat structure and to improve the characteristic of first insulating barrier 660, can carry out reoxidizing processing.Afterwards, using grid structure 655 to carry out ion as mask injects and handles to form the first contact knot 670A and to be arranged in substrate 610 groove 600 outside and form a plurality of second contacts and tie 670B being arranged in substrate 610 below the groove 600.
Shown in Fig. 7 G, on each sidewall of grid structure 655, form sept 671.At this moment, sept 671 is to use nitride or oxide to make.On grid structure 655 be formed for the conductive layer of contact plug and afterwards it continuously implemented CMP handle up to conductive layer appear till thereafter.After CMP handles, on the first contact knot 670A, form the first contact plug 690A, on the second contact knot 670B, form a plurality of second contact plug 690B simultaneously.Although the single first contact knot 270A and the first contact plug 290A be it should be noted that by graphic extension a plurality of first contact knot 670A and first contact plug 690A are arranged.
Though not graphic extension, the first contact knot 670A is connected with bit line via the first contact plug 690A, and the second contact knot 670B is connected with storage node via the second contact plug 690B.Certainly, the first contact knot 670A and the second contact knot 670B can be under the situations of not utilizing the first contact plug 690A and the second contact plug 690B and be connected with bit line and storage node respectively.
According to the fourth embodiment of the present invention, be connected with bit line first contact the knot 670A be formed on the substrate that is arranged in groove 600 belows, so the sidewall of groove 600 has constituted transistorized raceway groove in the born of the same parents district.
Fig. 8 is the profile of explanation according to the memory device structures of fifth embodiment of the invention.
Herein, the memory device of foundation the 4th embodiment comprises the identical configuration element described in Fig. 6, so will be omitted about the detailed description of this configuration element.Yet, according to the 5th embodiment memory device of making and the memory device difference of making according to the 4th embodiment be: the sidewall B of groove 700 is formed perpendicular to the surface of substrate 710 sunk parts and a plurality of grid structure 755, the first contacts knot 770A and the second contact knot 770B is provided so that the part of the substrate 710 at the sidewall B place of being set up is arranged at the center of each channel region.
Fig. 9 is the profile of explanation according to the memory device structures of sixth embodiment of the invention.
Comprise identical configuration element described in Fig. 6 according to the memory device of sixth embodiment of the invention herein.But the difference of memory device that foundation the 6th embodiment makes and memory device shown in Figure 6 is: the sidewall C of groove 800 is that forward tilts, that is, towards groove 800 bottoms the time, narrow down.
According to the present invention first to the 6th embodiment, the predetermined portions of the substrate that is connected with bit line is caved in, thereby the sidewall of the sunk part of substrate becomes the part of raceway groove.As a result, prolong the length of raceway groove, and then caused storage node contact knot place leakage current to reduce.Therefore, can increase the data hold time of memory device.Especially, the second and the 3rd embodiment and the 5th and the 6th embodiment provide the effect of improving about the tolerance limit of misalignment during the gate pattern processing.
The application comprises respectively No.KR2004-0058871 and the relevant theme of submitting to Korean Patent office on July 27th, 2004 and on July 29th, 2004 of two korean patent applications of 2004-0059670, and its full content is incorporated by reference at this.
Although the present invention is described about some preferred embodiment, for a person skilled in the art, it is evident that: under the situation that does not deviate from the spirit and scope of the present invention defined in the following claim, can carry out variations and modifications.
The conventional letter explanation of major part
110,210...810 substrate
120,220...820 field oxide layer
130,230...830, first insulating barrier
140,240...840 polysilicon layer
150,250...850 metal level
155,255...855 grid structure
160,260...860, second insulating barrier
170A, the 270A...870A first contact knot
170B, the 270B...870B second contact knot
171,271...871 sept
190A, 290A...890A first contact plug
190B, 290B...890B second contact plug.
Claims (27)
1. memory device comprises:
Substrate with groove;
Be formed on the bit line contact knot of described beneath trenches;
Be formed on the outer a plurality of storage node contact knots of described groove; And
A plurality of grid structures, its each be formed on the substrate between described bit line contact knot and the storage node contact knot.
2. memory device as claimed in claim 1, wherein said groove has sidewall, and described each sidewall is the part of raceway groove.
3. memory device as claimed in claim 1, the sidewall slope of wherein said groove makes described groove narrow down with downward bottom near described groove.
4. memory device as claimed in claim 1, the sidewall of wherein said groove is formed the surface perpendicular to the sunk part of described substrate.
5. memory device as claimed in claim 1, wherein said grid structure, described bit line contact knot and described storage node contact knot are provided so that the substrate of position at each sidewall place of described groove partly is arranged at the center in respective channels district.
6. memory device as claimed in claim 1, wherein each described grid structure second insulating barrier of comprising first insulating barrier, polysilicon layer, metal level and being used for hard mask.
7. memory device as claimed in claim 1, wherein each described grid structure comprises polysilicon layer, the metal level of first insulating barrier, complanation and is used for second insulating barrier of hard mask.
8. memory device as claimed in claim 6, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.
9. memory device as claimed in claim 7, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.
10. memory device comprises:
Substrate with groove;
Be formed on the first contact knot of described beneath trenches;
Be formed on the outer a plurality of second contact knots of described groove;
A plurality of grid structures, each described grid structure are formed on the substrate between the described first contact knot and the described second contact knot;
First contact plug, its by be filled in the space that produces between the described grid structure be formed on described first the contact tie; And
A plurality of second contact plugs, its by be filled in the space that produces between the described grid structure be formed on described second the contact tie.
11. the memory device as claim 10 further comprises:
Bit line, it contacts knot via described first contact plug and is connected with described first; And
A plurality of storage nodes, it contacts knot via described second contact plug respectively and is connected with described second.
12. as the memory device of claim 10, wherein said groove has sidewall, each described sidewall is the part of raceway groove.
13. as the memory device of claim 10, the sidewall slope of wherein said groove makes described groove narrow down with downward bottom near described groove.
14. as the memory device of claim 10, the sidewall of wherein said groove is formed the surface perpendicular to the sunk part of described substrate.
15. as the memory device of claim 10, wherein said grid structure, the described first contact knot and the described second contact knot are provided so that the substrate at each place, sidewall position of described groove partly is arranged at the center in respective channels district.
16. as the memory device of claim 10, each described grid structure second insulating barrier of comprising first insulating barrier, polysilicon layer, metal level and being used for hard mask wherein.
17. as the memory device of claim 10, wherein each described grid structure comprises polysilicon layer, the metal level of first insulating barrier, complanation and is used for second insulating barrier of hard mask.
18. as the memory device of claim 16, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.
19. as the memory device of claim 17, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.
20. as the memory device of claim 10, further comprise a plurality of septs, it is formed on each sidewall of described grid structure.
21. a method that is used to make memory device, included step is:
The etching part substrate is to obtain groove;
Form a plurality of grid structures, make each part of described grid structure be set in the described groove;
Use described grid structure to carry out ion and inject processing to form the first contact knot in described beneath trenches and to become a plurality of second contacts to tie in described trench profile as mask; And
Tie formation first contact plug and tie a plurality of second contact plugs of formation in described first contact in corresponding contact.
22. as the method for claim 21, the step that wherein forms described a plurality of grid structures may further comprise the steps:
On described substrate, form first insulating barrier, polysilicon layer, metal level and second insulating barrier in regular turn; And
Come described first insulating barrier of patterning, described polysilicon layer, described metal level and described second insulating barrier by carrying out mask process and etch processes.
23. as the method for claim 21, the step that wherein forms described a plurality of grid structures may further comprise the steps;
On described substrate, form first insulating barrier;
On described first insulating barrier, form polysilicon layer;
Carry out planarization process to obtain the polysilicon layer of complanation;
On the polysilicon layer of described complanation, form metal level;
On described metal level, form second insulating barrier; And
Come described first insulating barrier of patterning, the polysilicon layer of described complanation, described metal level and described second insulating barrier by using grid mask process and etch processes.
24. as the method for claim 21, the step that wherein forms described first contact plug and described second contact plug comprises the following steps:
On described grid structure, be formed for the conductive layer of contact plug; And
Described conductive layer is carried out chemical mechanical polish process till described second insulating barrier appears, obtain described first contact plug and described a plurality of second contact plug thus.
25. the method as claim 21 further comprises: the step that before carrying out described ion injection processing, described grid structure is reoxidized processing.
26. as the method for claim 21, wherein said first contact knot and the described second contact knot are formed bit line contact knot and storage node contact knot respectively.
27., after the step that forms described first contact plug and described a plurality of second contact plugs, further comprise the steps: as the method for claim 21
Form bit line, it contacts knot via described first contact plug and is connected with described first; And
Form a plurality of storage nodes, it contacts knot via described second contact plug respectively and is connected with described second.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020040058871 | 2004-07-27 | ||
| KR1020040058871A KR100623591B1 (en) | 2004-07-27 | 2004-07-27 | Memory device and fabricating method for the same |
| KR1020040059670 | 2004-07-29 |
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| CN1728387A CN1728387A (en) | 2006-02-01 |
| CN100438036C true CN100438036C (en) | 2008-11-26 |
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| KR100905776B1 (en) * | 2006-08-25 | 2009-07-02 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100815190B1 (en) * | 2007-03-29 | 2008-03-19 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabrication of the same |
| KR100905830B1 (en) * | 2007-11-16 | 2009-07-02 | 주식회사 하이닉스반도체 | Semiconductor device and manufacturing method thereof |
| CN106910745B (en) * | 2017-03-07 | 2018-03-06 | 睿力集成电路有限公司 | memory and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040036A (en) * | 1988-02-05 | 1991-08-13 | Emanuel Hazani | Trench-isolated self-aligned split-gate EEPROM transistor and memory array |
| US6048767A (en) * | 1991-08-22 | 2000-04-11 | Nec Corporation | Method of forming a semiconductor memory device |
| US6228700B1 (en) * | 1999-09-03 | 2001-05-08 | United Microelectronics Corp. | Method for manufacturing dynamic random access memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100307531B1 (en) * | 1999-08-09 | 2001-11-01 | 김영환 | Mosfet device and memory cell using the same and fabrication method threeof |
| DE19954867C1 (en) | 1999-11-15 | 2000-12-07 | Infineon Technologies Ag | Dynamic random access memory (DRAM) cells arrangement, each cell having one vertical transistor and one capacitor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040036A (en) * | 1988-02-05 | 1991-08-13 | Emanuel Hazani | Trench-isolated self-aligned split-gate EEPROM transistor and memory array |
| US6048767A (en) * | 1991-08-22 | 2000-04-11 | Nec Corporation | Method of forming a semiconductor memory device |
| US6228700B1 (en) * | 1999-09-03 | 2001-05-08 | United Microelectronics Corp. | Method for manufacturing dynamic random access memory |
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| CN1728387A (en) | 2006-02-01 |
| KR100623591B1 (en) | 2006-09-19 |
| KR20060010243A (en) | 2006-02-02 |
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