CN100435279C - Method for fabricating large area, self-supporting semiconductor material with wide forbidden band - Google Patents
Method for fabricating large area, self-supporting semiconductor material with wide forbidden band Download PDFInfo
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- CN100435279C CN100435279C CNB2006101051129A CN200610105112A CN100435279C CN 100435279 C CN100435279 C CN 100435279C CN B2006101051129 A CNB2006101051129 A CN B2006101051129A CN 200610105112 A CN200610105112 A CN 200610105112A CN 100435279 C CN100435279 C CN 100435279C
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- resilient coating
- forbidden band
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Abstract
Purpose of the method is to solve issues such as high defect density, a great lot cracks, and too small thickness of epitaxy material etc. existed in current technique for preparing semiconductor material with wide forbidden band. Technical scheme is as following: first, preparing SOI structure on silicon chip; next, using photo etching, epitaxy technique to fabricate insular buffer layer on SOL of SOI structure so as to form flexible substrate with dual buffers; then, epitaxial developed semiconductor material on the said substrate; afterwards, peeling off flexible substrate with dual buffers or SOI structure layer under epitaxial developed semiconductor material; finally, forming needed large area self supported semiconductor material with wide forbidden band. The invention can release high stress between epitaxy material and silicon chip material caused by crystal lattice mismatch and heat mismatch. The method is applicable to preparing SiC, GaN materials etc.
Description
Technical field
The invention belongs to microelectronics technology, relate to semi-conducting material, element manufacturing technology, the semiconductor material with wide forbidden band manufacture method of a kind of specifically large tracts of land, self-supporting can be used for carrying out the making of thin-film materials such as carborundum SiC, gallium nitride GaN.
Background technology
In recent years with SiC, GaN be the third generation semiconductor material with wide forbidden band of representative owing to have good characteristics such as big energy gap, high critical field strength, high heat conductance, high carrier saturation rate, heterojunction boundary two-dimensional electron gas height, make it be subjected to people and pay close attention to widely.In theory, utilize the devices such as high electron mobility transistor (HEMT), heterojunction bipolar transistor HBT, LED, laser diode LD of these material will have the incomparable excellent properties of existing device, therefore both at home and abroad it has been carried out extensive and deep research and has obtained the achievement that attracts people's attention in succession in recent years.
Yet the major obstacles that present third generation wide bandgap semiconductor material and related device face is exactly not have natural monocrystal material, is difficult to artificial preparation and obtains high-quality, large-sized monocrystal material.Meanwhile, along with more and more higher based on integrated level, the power density of the high power device of third generation semiconductor material with wide forbidden band and microwave power device, its heat dissipation problem is also more and more serious, and is more and more harsher to the requirement of the size of substrate, heat-sinking capability, insulation property.
With the GaN material is example.The end of the eighties, people such as Nakamura proposed to utilize the scheme of two step method epitaxial growth GaN material on Sapphire Substrate, referring to Nakamura S.GaN Growth UsingGaN Buffer L ager.Jpn.J Appl Phys.30 (10), L 1705～L 1707,1991.This scheme is one deck GaN resilient coating of at first growing on Sapphire Substrate, to reduce by sapphire and the caused high defect concentration of GaN lattice mismatch, regrowth GaN material on resilient coating then.Though this scheme can obtain than the GaN material that adopts the single-step process better quality, but because the lattice mismatch of GaN material (0001) aufwuchsplate and Sapphire Substrate (0001) crystal face is up to about 13.8%, so even adopted the defective of this scheme Grown GaN material close still up to 10
8-10
10/ cm
2More than.
People such as Detchprohm in 1993 and Amano have further proposed the scheme of growth GaN material on the ZnO substrate, referring to Detchprohm T, and Amano H, Hiramatsu K, et al.J Cryst Growth.128,384,1993.This scheme be on Sapphire Substrate at first extension layer of ZnO material as the substrate of GaN material epitaxy growth; Utilize the surperficial extension one deck GaN material of the lattice structure of the ZnO material characteristic close with the GaN material then at the ZnO material with lattice constant.Though ZnO material and GaN material have close crystal structure and lattice constant, but because bigger lattice mismatch causes self just having higher defect concentration by epitaxially grown ZnO material between ZnO material and the sapphire material, therefore the defect concentration of the GaN material that grows on the ZnO substrate is still very high.
People such as Hersee in 1999 have proposed to use the scheme of nano heterogeneous extension, referring to Zubia D, and Hersee S D.J Appl Phys Lett.49,140,1996.This scheme is at first made Si nanometer columnar arrays on the Si substrate, direct thereon then extension GaN material.The Si nano-pillar still still can not be bigger because of the relatively poor thick end of GaN material that causes of plasticity of Si substrate because nanometer size effect can discharge the stress that lattice mismatch produces between GaN and substrate to a certain extent.
With the SiC material is example, because the SiC material is difficult to form melt under normal pressure, temperature reaches 2400 directly distillations when spending, thereby is difficult to use traditional fusion method to be prepared.People such as nineteen eighty-three Nishino have proposed the scheme of growth 3C-SiC on the Si substrate, referring to Nishino S, and Powell J A, Will H A.Appl Phys Lett.42,460,1983.Adopt this scheme on Si, at high temperature to grow the quality SiC film of cube phase 3C structure preferably by the CVD technology.But, since the lattice mismatch of SiC and Si substrate up to 20%, thermal mismatching also reaches 8%, causes the residual stress in the SiC film bigger, the SiC material of the big thickness that is difficult to grow.This shows that the growth question that will solve the high-quality semiconductor material with wide forbidden band just has only the new technological approaches of searching.
The content of invention
The objective of the invention is to overcome above-mentioned the deficiencies in the prior art, a kind of method of making high-quality, large scale, self-supporting semiconductor material with wide forbidden band is provided.To solve present third generation semiconductor material with wide forbidden band heteroepitaxial growth technology because the heavily stressed problem that does not have lattice mismatch that suitable substrate causes and thermal mismatching to cause, to be used for the growth of various semiconductor material with wide forbidden band.
The technical scheme that realizes the object of the invention is: at the silicon structure of making on the silicon chip on the insulating barrier, it is soi structure, on this SOI, make island array buffer layer again, finally required large tracts of land, the self-supporting semiconductor material with wide forbidden band of epitaxial growth on the island resilient coating.
Its concrete manufacturing process is as follows:
(1) according to the crystal orientation and the size of the application choice silicon chip of self-supporting epitaxial loayer;
(2) utilize the conventional isolation of notes oxygen SIMOX, wafer bonding BESOI, smart peeling UNIBOND on selected silicon chip, to make buried oxide layer BOX, surface silicon SOL, form soi structure;
(3) on the surface silicon SOL of soi structure, utilize photoetching, epitaxy technique to make the island resilient coating, form the double buffering flexible substrate;
(4) on described double buffering flexible substrate, utilize conventional epitaxy technique growing semiconductor material;
(5) utilize conventional stripping technology that double buffering flexible substrate or soi structure layer below the described semi-conducting material are peeled off, form the semiconductor material with wide forbidden band of large tracts of land, self-supporting.
In the manufacture method of above-mentioned semi-conducting material, the wherein said process of utilizing photoetching process to make the island resilient coating is as follows:
The first step is made mask plate according to the single island size and the spacing of design;
Second goes on foot, and the mask plate of making is placed carry out photoetching, development on the SOL that scribbles photoresist;
The 3rd step, use corrosive liquid that SOL is carried out etching earlier, to guarantee the height on each island, re-use organic solvent and remove photoresist and clean surface, on SOL, form the island resilient coating.
In the manufacture method of above-mentioned semi-conducting material, the wherein said process of utilizing epitaxy technique to make the island resilient coating is: select the material close with the semiconductor material with wide forbidden band that will grow as making the epitaxial material that SOL goes up the island resilient coating, make extension be in the island growth pattern by temperature, the pressure of controlling outer time-delay, adjust growth time and control the size and the spacing on single island, on SOL, form the island resilient coating.
The present invention is owing to the double buffering flexible substrate structure that has adopted based on soi structure and island resilient coating composition, can discharge between epitaxial material and the silicon sheet material because of lattice mismatch, thermal mismatching produce heavily stressed, overcome the too small technical barrier such as can't peel off of the high defect concentration that exists based on the silicon substrate epitaxy technology, a large amount of crackle, epitaxial material thickness, can make high-quality self-supporting semiconductor material with wide forbidden band.Because the semiconductor material with wide forbidden band size that the present invention makes depends primarily on the size of used silicon chip, therefore can realize the making of large scale epitaxial material simultaneously.At present, the size of silicon chip has reached 8～12 inches, much larger than 2～4 inches of existing semiconductor material with wide forbidden band substrate commonly used.
Can construct various high performance semiconductor device based on the semiconductor material with wide forbidden band that the present invention makes, these devices are for powerful microwave power device, its heat-sinking capability is better than the traditional sapphire and the device of silicon substrate, and the grid of device are grown up in the device of SiC substrate commonly used.For photoelectric device since can be on a slice epitaxial material integrated more device, thereby greatly improved the output of device, reduced the cost of individual devices.
Description of drawings
Fig. 1 is manufacturing process figure of the present invention
Fig. 2 is the six side's phase 6H structure SIC material procedure charts that the present invention is based on the double-buffering layer flexible substrate, and this double-buffering layer flexible substrate is to be made of (100) crystal face SOI and Si island resilient coating.
Fig. 3 is cube phase 3C structure GaN material procedure chart that the present invention is based on the double-buffering layer flexible substrate, and this double-buffering layer flexible substrate is to be made of (111) crystal face SOI and AlN island resilient coating.
Embodiment
Below process and the embodiment that present invention will be described in detail with reference to the accompanying.
With reference to Fig. 1, manufacturing process of the present invention is as follows:
The first step is according to the silicon chip of the application choice certain size of self-supporting epitaxial loayer.
The selection of this silicon chip crystal face: select the silicon chip of different crystal faces according to the crystal orientation of epitaxial material, for example, form is the silicon chip that the 6H structure SIC of six side's phases can be selected (100) crystal face; And cube can select the silicon chip of (111) crystal face mutually for the SiC of 3C structure.
The selection of this die size: according to the epitaxy technology of epitaxial material and the size of purposes selection silicon chip.For example, for the metal organic chemical vapor deposition MOCVD epitaxy technology that GaN uses, the size of silicon chip depends on the size of MOCVD reative cell size.In addition, use epitaxial material for test, for the cost that reduces single test can use undersized silicon chip; Use epitaxial material for producing, for the cost that reduces individual devices can be selected large-sized silicon chip.In a word, the selection of die size must be considered the factor of reative cell size and material applications two aspects simultaneously.
In second step, on above-mentioned silicon chip, make BOX, SOL and form soi structure.
The technology of this soi structure: can select conventional SOI technologies such as annotating oxygen isolation SIMOX, wafer bonding BESOI, smart peeling UNIBOND for use according to physical condition.
The thickness of this each layer of SOI: SOL thickness is less than 200 nanometers, and the thickness of BOX is between 10～200 nanometers.
The 3rd step, on above-mentioned soi structure, make the island resilient coating, form double buffering flexible substrate structure.
The manufacture craft of this island resilient coating: optional with different technologies such as photoetching, extension, nanometer self-organizing growths according to epitaxial material and equipment situation, for example, can select the MOCVD epitaxy technique for use for the GaN material, for the optional photoetching process of using of SiC material, can select nanometer self-organizing technology for use for the ZnO material.
The described process of utilizing photoetching process to make the island resilient coating is as follows:
1, makes mask plate according to the single island size and the spacing of design;
2, use photoresist spinner to be attached on photoresist on the silicon chip uniformly;
3, the silicon chip that will smear photoresist is put into thermostatic drying chamber and is toasted;
4, mask plate and the silicon chip of making compressed, under the ultraviolet high-pressure mercury-vapor lamp, expose;
5, the silicon chip after at first will exposing is put into developer solution and is developed.Then silicon chip is put into cleaning fluid and carry out rinsing, obtain required figure;
6, at first, the silicon chip after developing is put into baking box.Then, toast from the back side with infrared lamp;
7, use HF acid and HNO
3Acid solution corrodes silicon chip, to guarantee the height on each island, forms the island resilient coating on SOL.
The described process of utilizing epitaxy technique to make the island resilient coating is as follows:
At first select the material close as making the epitaxial material that SOL goes up the island resilient coating with the semiconductor material with wide forbidden band that will grow, make extension be in the island growth pattern by temperature, the pressure of controlling outer time-delay again, adjust growth time then and control the size and the spacing on single island, make it on SOL, form the island resilient coating.
The 4th step, epitaxial growth semiconductor material with wide forbidden band on double buffering flexible substrate structure.
This growth technology: select different epitaxy technology for use according to material type.For example: the SiC material can use chemical vapor deposition CVD method; The GaN material can use metal organic chemical vapor deposition MOCVD method.The technological process that this step is used is identical with traditional epitaxy technique.
In the 5th step, the double buffering flexible substrate is peeled off.
At first, usage ratio is 1: 10 HF acid and HNO
3Acid solution peels off the nethermost body silicon layer of soi structure; Then, use HF acid to peel off BOX; At last, usage ratio is 1: 10 HF acid and HNO
3Acid solution peels off SOL and island resilient coating.
High-quality large tracts of land, self-supporting semiconductor material with wide forbidden band have been obtained by above processing step.
Embodiment 1
The present invention makes the SiC material of 80 micron six side's phase of 6 inches self-supportings 6H structure.
Substrate is selected for use: commercial commercially available 6 cun (100) crystal face Si sheets.
SOI manufacture craft: adopt and annotate oxygen isolation SIMOX.
The island resilient coating is made: adopt photoetching.
With reference to Fig. 2, the manufacturing process of present embodiment 1 is as follows:
1. make soi structure on the Si sheet of 6 inches (100) crystal faces, promptly using SIMOX technology to make thickness is the SOL layer of 100 nanometers, and thickness is the BOX layer of 100 nanometers.
2. on SOI, pass through photoetching making Si island resilient coating, form the double buffering flexible substrate.
Design at first that single island is of a size of 150 nanometers, spacing is 200 nanometers, according to these data creating exposure mask plates;
Then, use photoresist spinner polyvinyl cinnamate KPR photoresist to be attached on uniformly on the Si sheet of 6 inches (100) crystal faces;
Then, the thermostatic drying chamber of the Si sheet of having smeared 6 inches (100) crystal faces of photoresist being put into 80 ℃ toasts taking-up after 12 minutes;
Then, the mask plate made and the Si sheet of 6 inches (100) crystal faces are compressed, under the ultraviolet high-pressure mercury-vapor lamp, expose;
Then, the silicon chip after the exposure is put into butanone solution develop, the photoresist that removes not sensitization keeps the sensitization part.Then the Si sheet of 6 inches (100) crystal faces is put into acetone and deionized water carries out taking out after the rinsing;
Then, the Si sheet of 6 inches (100) crystal faces after the rinsing is put into baking box, toasted 20 minutes down, toasted 15 minutes from the back side with infrared lamp again at 150 ℃;
At last, usage ratio is 1: 10, and concentration is that 49% HF acid and concentration are 70% HNO
3Acid solution corrodes silicon chip in the time of 25 ℃, and etching depth is 70～80 nanometers, forms the double buffering flexible substrate that island resilient coating and SOI form.
3. use silane, methane respectively as silicon source and carbon source on the double buffering flexible substrate, utilize the CVD method, the control temperature is 1400 ℃, and epitaxial growth thickness is 80 microns SiC material on the double buffering flexible substrate.
4. to the double buffering flexible substrate of epitaxially grown SiC material underneath, peel off according to the following procedure:
At first, usage ratio is that 1: 10 concentration is that 49% HF acid and concentration are 70% HNO
3Acid solution body silicon layer to SOI in the time of 25 ℃ is peeled off, and this corrosion rate is 5.5 microns of per seconds, and the time was 45 seconds, and this body silicon layer is positioned under the BOX;
Then, working concentration is that 12% HF acid solution corrodes BOX when spending for 25 ℃, and this corrosion rate is per second 32 dusts, and the time is 40 seconds;
At last, usage ratio is 1: 10, and concentration is that 49% HF acid and concentration are 70% HNO
3Acid solution is peeled off SOL and Si island resilient coating in the time of 25 ℃, and the time was 5 seconds, forms the SiC material of 80 micron six side's phase of 6 inches self-supportings 6H structure at last.
Embodiment 2
The present invention makes the GaN material of 100 microns cubes of phase 3C of 4 inches self-supportings structure.
Substrate is selected for use: the Si sheet of commercial commercially available 4 inches (111) crystal faces.
SOI manufacture craft: adopt and annotate oxygen isolation SIMOX.
The island resilient coating is made: adopt extension.
With reference to Fig. 3, the manufacturing process of present embodiment 2 is as follows:
1. utilize SIMOX technology to annotate oxygen on silicon chip, making thickness is the SOL layer of 30 nanometers, and thickness is the BOX layer of 120 nanometers, forms soi structure;
2. use trimethyl aluminium, high-purity ammonia to come from nitrogenous source as aluminium on SOL, utilizing the MOCVD method is 450 ℃ in temperature, and pressure is under the condition of 40 holders, makes AlN island resilient coating by epitaxy method, to form the double buffering flexible substrate;
3. use triethyl-gallium, high-purity ammonia as gallium source and nitrogenous source on the double buffering flexible substrate, adopting the MOCVD method is 950 ℃ in temperature, and pressure is that epitaxial growth thickness is 100 microns GaN material on the double buffering flexible substrate under the condition of 40 holders.
4. according to the following procedure the soi structure of institute's Grown GaN material is peeled off:
At first, usage ratio is that 1: 10 concentration is that 49% HF acid and concentration are 70% HNO
3Acid solution, the body silicon layer to SOI in the time of 25 ℃ is peeled off, and its corrosion rate is 5.5 microns of per seconds, and the time was 45 seconds, and this body silicon layer is positioned under the BOX layer;
Then, working concentration is 12% HF acid solution, in the time of 25 ℃ BOX is corroded, and corrosion rate is per second 32 dusts, and the time is 40 seconds, to peel off BOX;
At last, usage ratio is that 1: 10 concentration is that 49% HF acid and concentration are 70% HNO
3Acid solution is peeled off SOL in the time of 25 ℃, and the time was 3 seconds, finally forms the GaN material of 100 microns cubes of phase 3C of 4 inches self-supportings structure.
In addition, except that photoetching and epitaxy technology, can also use the nanometer self-organizing technique to make island resilient coating of the present invention.
For those skilled in the art; after having understood content of the present invention and principle; can be under the situation that does not deviate from the principle and scope of the present invention; the method according to this invention is carried out various corrections and the change on form and the details, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (3)
1. the manufacture method of a large area, self-supporting semiconductor material with wide forbidden band, carry out according to the following procedure:
The first step is according to the crystal orientation and the size of the application choice silicon chip of self-supporting epitaxial loayer;
Second step, utilize the isolation of notes oxygen SIMOX, wafer bonding BESOI, smart peeling UNIBOND on selected silicon chip, to make buried oxide layer BOX, surface silicon SOL, form soi structure;
The 3rd step, on the surface silicon SOL of soi structure, utilize photoetching, epitaxy technique to make the island resilient coating, form the double buffering flexible substrate that island resilient coating and SOI constitute;
In the 4th step, on described double buffering flexible substrate, utilize epitaxy technique growing semiconductor material;
The 5th step, utilize conventional stripping technology that double buffering flexible substrate or soi structure layer below the described semi-conducting material are peeled off, form the semiconductor material with wide forbidden band of large tracts of land, self-supporting.
2. the manufacture method of semi-conducting material according to claim 1 is characterized in that the process of utilizing photoetching process to make the island resilient coating is as follows:
The first step is made mask plate according to the single island size and the island spacing of design;
Second goes on foot, and the mask plate of making is placed carry out photoetching, development on the SOL that scribbles photoresist;
The 3rd step, use corrosive liquid that SOL is carried out etching earlier, to guarantee the height on each island, re-use organic solvent and remove photoresist and clean surface, on SOL, form the island resilient coating.
3. the manufacture method of semi-conducting material according to claim 1, it is characterized in that the process of utilizing epitaxy technique to make the island resilient coating is: select GaN or AlN material as making the epitaxial material that SOL goes up the island resilient coating, make extension be in the island growth pattern by temperature, the pressure of controlling outer time-delay, adjust growth time and control the size and the spacing on single island, on SOL, form the island resilient coating.
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| CN101609800B (en) * | 2009-06-19 | 2010-12-29 | 上海新傲科技股份有限公司 | Method for preparing crystallographic orientation semiconductor substrate |
| DE102017101333B4 (en) | 2017-01-24 | 2023-07-27 | X-Fab Semiconductor Foundries Gmbh | SEMICONDUCTORS AND METHOD OF MAKING A SEMICONDUCTOR |
| CN114207847B (en) * | 2019-08-13 | 2022-09-02 | 苏州晶湛半导体有限公司 | Method for manufacturing nitride semiconductor substrate |
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| US20030183157A1 (en) * | 2002-03-26 | 2003-10-02 | Nec Corporation | Group III nitride based semiconductor substrate and process for manufacture thereof |
| JP2005020026A (en) * | 2004-09-30 | 2005-01-20 | Toyoda Gosei Co Ltd | Gallium nitride based compound semiconductor and semiconductor substrate |
| CN1697140A (en) * | 2004-05-10 | 2005-11-16 | 中国科学院半导体研究所 | Etching technique for preparing ultrathin flexible silicon sustrate through two step method in wet-process etching |
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| US20030183157A1 (en) * | 2002-03-26 | 2003-10-02 | Nec Corporation | Group III nitride based semiconductor substrate and process for manufacture thereof |
| CN1697140A (en) * | 2004-05-10 | 2005-11-16 | 中国科学院半导体研究所 | Etching technique for preparing ultrathin flexible silicon sustrate through two step method in wet-process etching |
| JP2005020026A (en) * | 2004-09-30 | 2005-01-20 | Toyoda Gosei Co Ltd | Gallium nitride based compound semiconductor and semiconductor substrate |
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Application publication date: 20070509 Assignee: Yangzhou Yangjie Electronic Co., Ltd. Assignor: Xidian University Contract record no.: 2016320000107 Denomination of invention: Method for fabricating large area, self-supporting semiconductor material with wide forbidden band Granted publication date: 20081119 License type: Exclusive License Record date: 20160307 |
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