CN100428253C - Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm - Google Patents
Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm Download PDFInfo
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- CN100428253C CN100428253C CNB2006101649217A CN200610164921A CN100428253C CN 100428253 C CN100428253 C CN 100428253C CN B2006101649217 A CNB2006101649217 A CN B2006101649217A CN 200610164921 A CN200610164921 A CN 200610164921A CN 100428253 C CN100428253 C CN 100428253C
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Abstract
This invention belongs to VLSI physical design technique field and relates to one computer aid design method facing analogue circuit board graph, which is characterized by the following: totally according to analogue integration circuit multi-line wide binding for design to satisfy analogue circuit load current status complexity requirement. This invention comprises shortest path index method with multiple line width binding conditions and adopts starting index method to realize automatic line distribution process on network mode.
Description
Technical field
Automatic wiring method of analog integrated circuit belongs to VLSI (very large scale integrated circuit) physical Design field, especially belongs to the technology category of Analogous Integrated Electronic Circuits physical Design, is the important component part in the mimic channel domain The Automation Design process.This method will comprise data structure and the method for searching path that designs at the mimic channel Performance Constraints, and it will determine the final domain of Analogous Integrated Electronic Circuits, and can have influence on the design cycle and the circuit performance of Analogous Integrated Electronic Circuits physical Design.
Background technology
1, the importance and the necessity of the automatic design of analog integrated circuit layout
Human for integrated circuit (Integrated Circuit, research IC) is from digital integrated circuit because with respect to mimic channel, digital integrated circuit is more prone to handle and operation.At the twentieth century initial stage eighties, because the function of digital signal processing algorithm strengthens day by day, and algorithm all realizes on integrated circuit again at an easy rate, thereby makes people produce undue confidence to digital circuit.Even have many experts once to foretell at that time that mimic channel was soon replaced by digital circuit fully, thereby withdraw from historical stage.In fact, such prophesy is that the design and the manufacturing that are based upon integrated circuit have enough abilities, and all signals can be represented on such prerequisite by discretize.In recent years, Analogous Integrated Electronic Circuits and at the notice that the design and the exploitation of the design aids of mimic channel attracted people gradually makes industry pay attention to more for method for designing, the design tool of mimic channel and Related product.Why so big variation takes place to the attitude of Analogous Integrated Electronic Circuits and design tool thereof in people, its main cause is that people are not familiar with fully for the importance of mimic channel before, and has ignored because the chain effect that production technology progress and process modification are brought.And the fact shows, is to have very strong theory and practical significance for the research and development of Analogous Integrated Electronic Circuits and design tool thereof.
At first, people are huge for the demand of Analogous Integrated Electronic Circuits, because its essential instrument that is Analog signals.At nature, although there is the signal of a lot of types to be represented by discrete digital signal, natural signal, the vision of obtaining such as us, audible signal and radio signal commonly used etc. all are analog quantity in essence; And in a lot of complicated high performance systems, it is essential that mimic channel remains.Especially in recent years, industry member is increasing for the demand of Analogous Integrated Electronic Circuits and hybrid digital-analog integrated circuit.Show that according to a statistical report as far back as eighties of last century nineties, nearly 60% CMOS and BiCMOS special IC have been arranged, and (Application Specific Integrated Circuit is that digital-to-analogue is mixed ASIC).According to another the ICE of market researchy corporation world's integrated circuit market development tendency statistics is shown, the share that the market of Analogous Integrated Electronic Circuits accounts for IC product overall market is: accounted for 16% (the integrated circuit overall market is 681.8 hundred million dollars) in 1993, be increased to 17.5% (Analogous Integrated Electronic Circuits market reaches 19,100,000,000 dollars) in 1998, will be by 2002 near about 15%.Along with further developing of the communications industry, new wireless communication system and Video Applications will continue to increase to the demand of mimic channel, thereby the market that makes Analogous Integrated Electronic Circuits is to bigger scale development.
Secondly, the boundary of digital integrated circuit and Analogous Integrated Electronic Circuits is more and more littler, makes digital circuit also have to consider the factor of some simulations.In fact, digital circuit and mimic channel are all realized by transistor, have just utilized the different duty of transistor.So digital circuit and mimic channel be not from haveing nothing to do fully in essence.As far back as 1986, professor Paul.R.Gray of California, USA university with regard to its " egg model " to digital circuit, mimic channel and connect both A/D, relation between the D/A converter has been carried out vivid elaboration.This model is considered as an egg on the whole to above-mentioned three, and digital circuit is likened to yolk, and mimic channel is likened eggshell to, A/D and D/A change-over circuit are likened egg white to, though it is different that this has just embodied the three, mutual infiltration arranged with related again, thereby become an integral body.In recent years, appearance and fast development along with deep submicron process, the simulation factor that needs in the digital integrated circuit to consider gets more and more, because the designer must manage to solve the ghost effect that the simulation behavior of all electronic circuits under deep submicron process brought, such as coupling between line, signal delay, noise with crosstalk etc.So, in fact we can think that the design of digital circuit simulated and changed, in other words, no matter digital circuit or mimic channel, we need to consider some factors of identical simulation aspect.Said as Maxim president of a company John Gifford, " in digital product, will need more, the better mimic channel of performance.”
The 3rd, the increase of Analogous Integrated Electronic Circuits scale has proposed challenge to traditional hand-designed mode, also the design aids towards mimic channel has been proposed new demand simultaneously.Because it is much smaller that the scale of Analogous Integrated Electronic Circuits is compared with digital integrated circuit, more much higher but circuit performance requires than digital circuit, so the designer adopts the mode of hand-designed to finish whole designs to mimic channel usually.At physical design phase, the designer can spend in the plenty of time such as on the uninteresting details such as line, device position, thereby satisfies because circuit performance requires the various constraint conditions brought.(simulation in the circuit design and hybrid circuit composition are more and more for System ona Chip, development SoC), make Design of Simulating Circuits become the bottleneck of entire chip design along with SOC (system on a chip).In addition, the increase of Analogous Integrated Electronic Circuits scale and process reduce also allow designer's layout design can't satisfy the requirement of precision well.Therefore, a lot of Analog Circuit Design Shi Xiwang can have the aid as Design of Digital Integrated Circuit, thus the design cycle of reducing circuit, the error in reducing to design.
As seen, because integrated circuit technique design and fabrication technology fast development, the scale of Analogous Integrated Electronic Circuits constantly changes, its characteristic dimension reduces day by day, the method that traditional craft is carried out physical Design to mimic channel must obtain the help of aid, so (Electronic Design Automation, EDA) instrument also must become the focus that the designer pays close attention to the electric design automation relevant with Analogous Integrated Electronic Circuits.A lot of universities have begun exploration and the exploitation to the Analogous Integrated Electronic Circuits design aids already, as (the University of California at Berkeley of University of California Berkeley, UCB), Ka Naiji-Mei Long university (Carnegie-Mellon University, CMU); A lot of well-known eda software companies have also invested this to sight and have had the product of suitable market potential, as Cadence, and Synopsis etc.However, because the design aids at mimic channel all has suitable difficulty in design and exploitation, even have a lot of problems to be improved on the design theory and to improve, so up to the present, still the product of neither one maturation is used by industry member.Therefore, have very important theory and practical significance for the research and development of Analogous Integrated Electronic Circuits and eda tool thereof, and also will become the focus and the difficult point problem of industry research within a certain period of time.
2, Analogous Integrated Electronic Circuits self routing model
In the process that integrated circuit is connected up, we are different to the description of wiring problem with abstract representation.The method that these different abstraction hierarchies can cause gauze to be expressed in system is also inequality, thereby further brings different data structures.In the Analogous Integrated Electronic Circuits automatic routing system, mainly contain two kinds of cloth line models and be used: no grid model and grid model is arranged, as depicted in figs. 1 and 2.Wherein, Fig. 1 is no grid model, and Fig. 2 is for there being grid model.
In no grid model, the wiring zone is without any restriction, and all unit, module and gauze all are represented as polygon, rely on polygonal apex coordinate to describe all unit and gauze.Obviously, use no grid model biggest advantage to be that it can be easy to handle multi-thread wide constraint when mimic channel is connected up, this also becomes the reason that a lot of existing mimic channel wiring units are selected this cloth line model, is exactly typical wiring unit based on no grid model as existing ANAGRAM I and ANAGRAM II.
But the complicacy of no grid model aspect control but allows a lot of mimic channel wiring systems finally can not finish the target of wiring effectively, and its drawback is mainly reflected in three aspects.The first, as previously mentioned, the performance requirement of Analogous Integrated Electronic Circuits is diversified, we can not be only because no grid model freely treatment mechanism just think its most suitable mimic channel automatic routing system.Under no grid model, owing to lack the constraint of geometric aspects, wiring unit is not easy to handle most important symmetry constraint in mimic channel.The second, owing to lack the tutorial message of similar grid, no grid model makes that the data representation of wiring system is extremely complicated, much can often need complicated description just can be achieved by the information of the simple expression of grid.The 3rd, no grid wiring method is perspective to the utilization shortage of resource, so be easy to cause resources allocation unreasonable.In other words, in the wiring of no grid, if do not controlled, wiring unit uses resource probably wantonly at the beginning, and along with the increase of line screen, the gauze completion rate can descend gradually; And if think to be controlled in advance, this control flow is then very complicated.
In grid model was arranged, the wiring zone was divided by a macrolattice, and the zone has been formed certain constraint.The introducing of grid has been played guiding effect to wiring process, because the existence of topological coordinate in the grid, thereby we can substitute the information that geometric coordinate is expressed gauze and obstacle with topological coordinate at an easy rate.Simultaneously, we do not need to handle and the control polygon in the wiring process, handle and get final product and institute's wired network is abstracted into line segment.Owing to have the control flow of grid model simpler, so in the digital integrated circuit automatic routing system larger, that device shape is regular, the gauze width is single, this model is used in a large number than no grid model.The mimic channel self routing device of very early time as ILAC and LADIES, has also extensively been inherited grid model.
Yet the mimic channel self routing device in later stage has all been abandoned grid model, and most important reason is still because the constraint of grid makes multi-thread wide demand be difficult to satisfy, so the researcher has to select the complicated more no grid model of control flow.Simultaneously, owing to having under the grid model, can there be certain systematic error in physical coordinates to the conversion of topological coordinate, and these errors might make the utilization factor of interconnection resource be subjected to a certain degree influence.
3, the multi-thread wide constraint of Analogous Integrated Electronic Circuits
In Analogous Integrated Electronic Circuits, the width of gauze is unfixed often, and these characteristics become one of main difference of mimic channel and digital circuit.Performance in order to ensure circuit, the designer must consider and performance-relevant several key factors in definite gauze width, comprises the size of loaded current, the interconnection resistance of the gauze resistance in series of ground wire (especially with), shunt capacitance and distributed resistance and distributed capacitance etc.At the physical design phase of circuit, these factors all should be embodied on how much states such as the length of gauze and width, so, because to the difference of the performance requirement of concrete gauze, in Analogous Integrated Electronic Circuits, the width of gauze also changes.Wherein, influence that the factor of gauze width is important three: connection resistances, wire capacitances and current density.
In low-frequency mimic channel, skin effect can be ignored, and the resistance of metal connecting line can estimate with comparalive ease.Under the model of multiple layer metal line, the square resistance representative value of top layer line is 30m Ω/, and the square resistance representative value of lower floor's line is 70m Ω/.When gauze carried very big electric current, the resistance of gauze self also can have influence on determining of gauze width.
Wire capacitances is more complicated more than wire capacitances to the influence of gauze width.In the circuit of reality, can there be capacity plate antenna and edge capacitance between line and the substrate, also there is same electric capacity between line and the line.But because the latter is difficult usually to calculate and to quantize, so we only consider the electric capacity between line and the substrate in wiring process.In the actual calculation process, we use following experimental formula to calculate the size of wire capacitances:
W wherein, h, the value of t is as shown in Figure 6.For typical sizes, the error of calculation of this formula is very little.As can be seen, the gauze width is a principal element for the influence of wire capacitances, so reasonably allowing every gauze that optimal width is arranged in wiring is of crucial importance and necessary in the physical Design of Analogous Integrated Electronic Circuits.
The factor of another one decision gauze width is " electromigration (Electro-Migration) " phenomenon.When current density was very high, the aluminium atom in the line was easy to generate " migration ".In the device working time relatively long after, the room that atomic migration stays finally can cause line to disconnect.For fear of device that brings owing to " electromigration " and chip reliability problem, must limit the maximum current density of gauze institute loaded current in the mimic channel physical Design process.Rule of thumb, common every micron wide wire screen acceptable current density is 1mA, and in the manufacture process of reality, the actual value of gauze width also can be adjusted according to the thickness of metal.For some transient current, also need bigger gauze width.Therefore, the gauze width in the wiring process also can be according to the difference of current density and difference, and this also makes the gauze of Analogous Integrated Electronic Circuits have multi-thread wide feature.
4, the method and the defective of the multi-thread wide constraint of current solution
At present, the layout design of Analogous Integrated Electronic Circuits does not also realize robotization, and industry member also is not used in the automatic or semi-automatic simulation circuit layout design tool of actual production, so the designer relies on the manual layout design of finishing mimic channel substantially.And existing mimic channel automatic routing system great majority do not have the special disposal of consideration to multi-thread wide constraint, and they adopt the method for single live width wiring, use no grid model, and institute's wired network is all connected up according to the live width of maximum.The basic thought of this wiring method and disposal route all derive from the automatic routing system of digital circuit, and the feature at mimic channel does not design, and therefore can not adapt to the multi-thread wide requirement of mimic channel.Though and the method that adopts maximum line width to connect up can guarantee wiring result's correctness, its interconnection resource expends the resource cost much larger than practical wiring.And, though no grid model can provide more flexibly wiring mechanism, the data structure of wiring system and programmed control flow process more complicated, and be unfavorable for solving synchronously other geometrical constraints of mimic channel.
Mimic channel wiring algorithm based on grid reconstruction is another method that solves multi-thread wide constraint, and it is a kind of processing mode based on grid model.This method according to all possible width of gauze to the gauze processing of classifying, the directly corresponding unit grids size of each wiring width.That is to say, in wiring process, need to re-construct repeatedly grid to adapt to the variation of different live widths.Grid reconstruction method can solve multi-thread wide problem effectively in wiring process, and also the method than the maximum line width wiring more economizes on resources, but, grid reconstruction can bring bigger burden to system, because reconstructed mesh all needs all relevant informations are carried out repeating label and processing each time, and when the unit grids size was big, the precision of system handles can be under some influence.
Based on the problem that existing mimic channel automatic routing system exists, the multi-thread wide characteristics that the present invention is directed to mimic channel are improved the core algorithm---path search algorithm---of wiring system, and it has following characteristics:
In order to adapt to the multiple constraint of mimic channel, the present invention has adopted grid model to connect up.On the one hand, the data structure of wiring system and control flow can be simpler under grid model, on the other hand, grid model other key properties to mimic channel arranged, and as symmetry and coupling etc., better adaptability arranged.
In the process of implementing wiring, path search algorithm has played conclusive effect.This improves at the widely used path search algorithm in VLSI self routing field to labyrinth algorithm in the present invention, the step-length that the method for the single expansion step-length of feasible classics can have plurality of optional to select.The introducing of this thought not only can be satisfied multi-thread wide constraint well, this is constrained in considered synchronously in the wiring process and solve, and can also further improve the completion rate of resource utilization and gauze.Simultaneously, compare with grid reconstruction method, this method has obviously reduced the time consumption of system when operation.
Because These characteristics, the present invention has good result when Analogous Integrated Electronic Circuits is implemented wiring.We have adopted the side circuit of industry member as test case, and it can finish self routing according to the requirement that given circuit is described, and can finish the work in user's acceptable time expends.
Description of drawings
Fig. 1: no grid model synoptic diagram;
Fig. 2: the grid model synoptic diagram is arranged;
Fig. 3: the error synoptic diagram of standardization wiring width and practical wiring width;
Fig. 4: labyrinth algorithm synoptic diagram;
Fig. 5: the precision difference in long labyrinth of single step and the long labyrinth of multistep;
Fig. 6: the capacity plate antenna of line and substrate and edge capacitance;
Fig. 7: obstacle and pin synoptic diagram;
Fig. 8: pin mapping synoptic diagram;
Fig. 9: the long labyrinth expansion of multistep synoptic diagram;
Figure 10: wiring result topology synoptic diagram;
Figure 11: wiring results set synoptic diagram;
Figure 12: the automatic Core Generator process flow diagram of mimic channel domain;
Figure 13: the automatic domain example that generates;
Figure 14: the mimic channel automatic routing system based on multiple step length labyrinth algorithm is carried out schematic flow sheet.
Summary of the invention
The objective of the invention is to propose a kind ofly can satisfy multi-thread wide constraint and can further improve resource utilization and gauze completion rate again, thereby reduce the automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm of system operation time.It is characterized in that this method realizes successively according to the following steps on computer platform:
Circuit layout result, gauze information, unbound document and the technical papers that provides with document form is provided to computing machine step (1) program.
The information that step (2) computer program reads in according to step (1) is set up the necessary data structure of wiring process, comprising the gauze tabulation, comprises that in addition the wiring environment of obstacle tabulation is described.
The gauze tabulation that step (3) traversal is obtained by step (2), from the gauze attribute, read gauze width W ireWidth value and gauze spacing WirePitch value, both summations are obtained the grid wiring width NetSize of gauze, and with this value structure grid wiring width S set etOfNetSize.Simultaneously, obtain the minimum feature and the distance between centers of tracks value of metal level, and add this grid wiring width set after the summation according to technological requirement.Then, minimum grid wiring width value in this grid wiring width set is composed to unit grids size variable GridUnitSize as initial value.
Step (4) travels through this grid wiring width S set etOfNetSize according to following steps, under specification error ERROR control, gauze grid wiring width is carried out standardization, thereby obtain the standardization grid wiring width and the required unit grids size of wiring of institute's wired network.Wherein, standardization grid wiring width is k a times of unit grids size, and k is an integer, is 1 during initialization.
Step (4.1) is taken out first current grid wiring width from the set of grid wiring width;
Step (4.2) is made comparisons this current grid wiring width and k times of unit grids size: if this current grid wiring width is greater than k times of unit grids size, then k increases 1 automatically, until current grid wiring width is less than or equal to k times of unit grids size, then judge: if the difference of k times of unit grids size and current grid wiring width is greater than specification error ERROR, then the unit grids size value is modified to half of original value, simultaneously the k value is reset to 1, return step (4.1), current grid wiring width is pointed to described first current grid wiring width again; Otherwise, enter step (4.3);
The value of k times of unit grids size of step (4.3) record is given the standardization grid wiring width variable SNetSize of corresponding gauze with it.
Step (4.4) the described method in (4.1) ~ (4.3) is set by step calculated all remaining grid wiring width in the described grid wiring width set, and gives corresponding standard grid wiring width SNetSize.
The tabulation of step (5) traversal gauze is pressed descending sort to gauze according to the size of standardization grid wiring width, the gauze tabulation OrderedNetList after obtaining sorting.
Step (6) is allocated in advance gauze cloth line position according to the practical wiring layer VirtualLayer of gauze priority and gauze.
Step (7) is set up wiring grid with the unit grids size as the unit grids size, and its border of mark is " unavailable " state.Described grid uses following two-dimentional short array representation, and wherein 0 represents net point " available ", 1 expression net point " unavailable ".
The tabulation of step (8) traversal obstacle, in the enterprising row labels of grid chart, the value of corresponding array is labeled as 1 to all obstacles.
Step (9) travels through the pin tabulation PinList and the pin of equal value tabulation EqualPinList of every gauze according to the following steps, all pin and the pins of equal value of mark on grid chart, and pin is mapped as an available net point carries out to guarantee follow-up wiring algorithm.
Step (9.1) is set up candidate mappings point set SetOfCandidate: the net point that all pin and pins of equal value covered is recorded in the described candidate mappings point set.
Step (9.2) is removed underproof point in the candidate mappings point: judge each candidate point begins to corresponding gauze whether occupied by all net points of pre-assigned wiring layer from actual place layer, if then this net point is removed from the set of candidate mappings point; Otherwise, be retained in the set.
Step (9.3) is set up the map grids point sequence ListOfMappingPoint of each pin: if the point in the candidate collection is covered by pin or pin of equal value, then this point is added into the map grids point sequence, and has high priority; If have only unique point in the candidate collection, then this point is added into the map grids point sequence, and has high priority; Otherwise, other points are assigned to the map grids point sequence of respective pins, and according to this point its priority of distance decision apart from the pin central point, high more the closer to the net point priority at center.Be combined into empty pin for the candidate mappings point set, be labeled as " mapping failure ", but then this gauze wouldn't cloth because of layout or systematic error reason.
Gauze tabulation after the ordering that step (10) traversal step (5) obtains uses multiple step length labyrinth algorithm that gauze is implemented wiring according to the following steps.
Read the current gauze that will connect up the gauze tabulation of step (10.1) after ordering, if gauze is the multiterminal gauze, then it is decomposed into several two-terminal gauzes, and set up subnet tabulation SubNetList, their standardization grid wiring width is k a times of unit grids size, and then k is the largest extension step-length of current gauze;
The described subnet tabulation of step (10.2) traversal, begin gauze is carried out the labyrinth expansion from one of them end points of two-terminal gauze, according to the extended method of multiple step length labyrinth algorithm, current point can be eastwards, south, west, north four direction are expanded selectively, and its step-length is between 1 to k.
If: the topological coordinate of current point is that (CurrentTopoX CurrentTopoY), then when expansion, check whether the unit grids point of ± k/2 vertical with propagation direction is available.If a bit be " unavailable " state arbitrarily along having on the position of maximum m the unit grids of propagation direction, then Kuo Zhan step-length is (m-1), and wherein, m is the arbitrary integer between 1 to k.To write down corresponding expansion cost during expansion, estimate the cost that will take place comprising the cost that expands to current location with when expanding to impact point.Wherein, when vertically expanding, the unit grids point range of described ± k/2 from
Arrive
When along continuous straight runs is expanded, the unit grids point range of described ± k/2 from
Arrive
Step (10.3) begins to carry out the labyrinth expansion according to the described method of step (10.2) from another end points of two-terminal gauze.
When step (10.4) intersects when the net point that goes out from two endpoint extension, stop expansion, begin to backtrack to two end points directions respectively from intersection point, promptly from intersection point, search for the father node of current point successively,, then select the node of described expansion cost minimum if there are a plurality of father nodes, up to two end points backtracking two end line nets, thereby determine final path.
Step (10.5) line screen according to structure in record wiring result, and at grid array acceptance of the bid note institute cloth subnet, and judge: if cloth is intact for all subnets of this gauze, execution in step (10.2); Otherwise cloth is not intact if go back wired network, execution in step (10.1); Otherwise, execution in step (11);
Step (11) is output as layout file to all wiring results by the CIF form.
The present invention is directed to the multi-thread wide constraint of Analogous Integrated Electronic Circuits and design, existing labyrinth algorithm is improved, proposed a kind of new method for searching shortest route.This method has made full use of advantage and the characteristics that grid model is arranged, and is processing target with the gauze, has finished the wiring process that adapts to multiple live width under single grid.This method has been broken traditional labyrinth algorithm only has single step-length in the data expansion process limitation, can determine the expansion step-length in each step according to the concrete condition of wiring, when satisfying the multi-thread wide requirement of mimic channel, can also make full use of the resource of wiring.Simultaneously, multiple step length labyrinth algorithm is owing to adopted less mesh width, the labyrinth algorithm higher (as shown in Figure 5) of the single step-length that its mapping and wiring ratio of precision are traditional.In the route searching process, this method has also been introduced didactic strategy, has accelerated the speed of algorithm, has reduced storage space.This method is used C Plus Plus and with design of object-oriented thought and realization, is had stronger platform versatility, can be at Microsoft Windows, and Linux moves on the platforms such as Sun Solaris.
Embodiment
We use the Analogous Integrated Electronic Circuits of industry member reality as test case, use this method that circuit is implemented wiring.Here we choose a part in this example and carry out specific implementation process and describe, as shown in Figure 7.
(1) circuit layout result, gauze information, unbound document, the technical papers that provides with document form is provided program.
(2) the program information of reading in according to step (1) is set up the necessary data structure of wiring process, comprises that gauze tabulation NetList and wiring environment describe, and comprises obstacle tabulation ObstacleList etc.In this example, the gauze tabulation is for { the obstacle tabulation is { Obstacle1, Obstacle2} for Net1, Net2}.
(3) traversal reads gauze width W ireWidth and gauze spacing WirePitch value by the gauze tabulation that step (2) obtains from the gauze attribute, and summation obtains the wiring width NetSize of gauze, and constructs wiring width S set etOfNetSize with this value.Simultaneously, obtain the minimum feature and the distance between centers of tracks requirement of metal level according to technological requirement, and the adding SetOfNetSize that sues for peace.Give minimum NetSize value tax unit grids size variable GridUnitSize as initial value, compose 1 and give k as initial value.In this example, the gauze width W ireWidth of Net1 is 0.8um, and gauze spacing WirePitch is 0.3um, so its wiring width NetSize is 1.1um; The gauze width W ireWidth of Net2 is 0.5um, and the gauze spacing is 0.3um, so its wiring width NetSize is 0.8um.Technological requirement metal level minimum feature is 0.28um, and the minimum line spacing is 0.28um, so the minimum wiring width is 0.56um.In the program of reality, for convenience of calculation, we all enlarge 1000 times to all sizes, wiring width S set etOfNetSize={1100 then, 800,560}, k=1 during initialization, GridUnitSize=560.
(4) traversal wiring width S set etOfNetSize carries out standardization to the gauze wiring width under specification error ERROR (this error as shown in Figure 3) control, thereby obtains the standardization wiring width and the required unit grids size of wiring of institute's wired network.Wherein, standardization wiring width is the integral multiple (k doubly) of unit grids size.In this example, our specification error ERROR=0.05um, enlarge 1000 times after ERROR=50.
(4.1) from SetOfNetSize, take out current grid wiring width CurrentNetSize;
(4.2) if CurrentNetSize greater than k times of unit grids size GridUnitSize, then k smaller or equal to k times of GridUnitsize, enters step (4.3) up to CurrentNetSize from increasing 1;
(4.3) judge: if the difference of k times of GridUnitSize and CurrentNetSize is greater than specification error ERROR, then the GridUnitSize value is modified to GridUnitSize/2, simultaneously k is reset to 1, CurrentNetSize points to first element again, returns (4.1); Otherwise, enter step (4.4);
(4.4) k times of GridUnitSize value of record given the standardization wiring width variable SNetSize of corresponding gauze with it.
In this example, at first obtain CurrentNetSize=1100, obvious 1100＞1*560, then k increases to 2, this moment 1100＜2*560, and the difference of the two be 2*560-1100=20 (50, SNetSize1=2*560=1120 then.
And then get CurrentNetsize=800, same, when k=2,800＜2*560, but 2*560-800=320＞50 are so GridUnitSize=560/2=280 returns original state again and carries out standardized calculation.
After recomputating, to Net1, the standardization wiring width is SNetSize1=4*280=1120; To Net2, the standardization wiring width is SNetSize2=3*280=840.
(5) tabulation of traversal gauze is pressed descending sort to gauze according to standardization wiring width SNetSize, the gauze tabulation OrderedNetList after obtaining sorting.OrderedNetList={Net1 in this example, Net2}.
(6) according to gauze priority and resource distribution situation gauze cloth line position is allocated in advance, the practical wiring layer of gauze is recorded as VirtualLayer.In this example, two gauze practical wiring layers all are 3, VirtualLayer=3 then, and in the wiring process of reality, gauze can be used third and fourth layer of metal, the 3rd layer of cloth horizontal line section wherein, the 4th layer of vertical line segment of cloth.
(7) set up wiring grid with GridUnitSize for the unit grids size, and its border of mark is " unavailable " state.Here use following two-dimentional this grid of short array representation, wherein 0 represents net point " available ", 1 expression net point " unavailable ".Can in array, be labeled as the gauze that is cabled successfully its integer number value in the wiring process.
(8) traversal obstacle tabulation ObstacleList, in the enterprising row labels of grid chart, corresponding array value is labeled as 1 to all obstacles.In this example, as shown in Figure 7, Obstacle1 and Obstacle2 are labeled in grid chart.
(9) the pin tabulation PinList of every gauze of traversal and pin of equal value tabulation EqualPinList, all pin and the pins of equal value of mark on grid chart, and pin is mapped as an available net point carries out to guarantee follow-up wiring algorithm.Here, as shown in Figure 7, gauze Net1 has two pins, is labeled as Pin11 and Pin12; Gauze Net2 has two pins, is labeled as Pin21 and Pin22.
(9.1) set up candidate mappings point set SetOfCandidate: the net point that all pin and pins of equal value covered is recorded in this set;
(9.2) remove underproof point in the candidate mappings point: judge each candidate point begins to corresponding gauze whether occupied by all net points of pre-assigned wiring layer from actual place layer, if then this net point is removed from the set of candidate mappings point; Otherwise, be retained in the set.
(9.3) set up the map grids point sequence ListOfMappingPoint of each pin: if the point in the candidate collection is covered by pin or pin of equal value, then this point is added into the map grids point sequence, and has high priority; If have only unique point in the candidate collection, then this point is added into the map grids point sequence, and has high priority; Otherwise, other points are assigned to the map grids point sequence of respective pins, and according to this point its priority of distance decision apart from the pin central point, high more the closer to the net point priority at center.Be combined into empty pin for the candidate mappings point set, be labeled as " mapping failure ", but then this gauze wouldn't cloth because of layout or systematic error reason.
In this example, each pin be mapped on the grid point as shown in Figure 8.
(10) traversal OrderedNetList uses multiple step length labyrinth algorithm that gauze is implemented wiring.
(10.1) from OrderedNetList, read current gauze object, if gauze is the multiterminal gauze, then it is decomposed into several two-terminal gauzes, and set up subnet tabulation SubNetList, their standardization wiring width is k a times of unit grids size, and then k is the largest extension step-length of current gauze; In this example, two gauzes all are two end line nets, so do not need to decompose, directly handle gauze and get final product.Wherein, the k value of Net1 is 4, and the k value of Net2 is 3.
(10.2) traversal subnet tabulation SubNetList, begin gauze is carried out the labyrinth expansion from one of them end points of two-terminal gauze, according to the extended method of multiple step length labyrinth algorithm, current point can be eastwards, south, west, north four direction are expanded selectively, and its step-length changes from 1 to k.Suppose the topological coordinate of current point for (CurrentTopoX CurrentTopoY), then needs to judge in expansion process along in propagation direction k the unit grids scope, on the direction vertical with propagation direction from
Arrive
(when vertically expanding) or from
Arrive
When expansion (along continuous straight runs) whether have a few be " available " state.If a bit be " unavailable " state arbitrarily along having on the position of maximum m the unit grids of propagation direction, then Kuo Zhan step-length is (m-1), and wherein, m is the arbitrary integer between 1 to k.To write down corresponding expansion cost during expansion, estimate the cost that will take place when this cost comprises the cost that expands to current location and expands to impact point.In this example, Net1 searches for 4 net points forward by propagation direction at every turn, and inspection vertical with propagation direction ± whether 2 unit grids points available.In expansion for the first time, these points all are available, then expand for the first time 4 units forward.Net2 is then searched for 3 net points forward by propagation direction at every turn, and inspection vertical with propagation direction ± whether 1 unit grids point available.Expansion process as shown in Figure 9.Wherein the position of once advancing is expanded in each some expression.When Pin11 expands to Obstacle2, owing to extended target point is occupied by obstacle, so can only expand 3 units.
(10.3) impact point from the two-terminal gauze begins to carry out the labyrinth expansion according to the method that step (10.2) is described.
(10.4) when the net point that goes out from two endpoint extension intersects, stop expansion, begin to backtrack to two end points directions respectively from intersection point, promptly from intersection point, search for the father node of current point successively,, then select the node of described expansion cost minimum if there are a plurality of father nodes, up to two end points backtracking two end line nets, thereby the result who obtains after this example of definite final path is backtracked as shown in figure 10.
(10.5) line screen according to structure in record wiring result, and at grid array acceptance of the bid note institute cloth subnet.Judge: if cloth is not intact for all subnets of this gauze, execution in step (10.2); Otherwise cloth is not intact if go back wired network, execution in step (10.1); Otherwise, execution in step (11); In this example, need first aftertreatment Net1 and Net2.
(11) all wiring results are output as layout file by the CIF form.This sample result as shown in figure 11, the circuit whole result is as shown in figure 13.
Claims (1)
- Based on the automatic wiring method of analog integrated circuit of multiple step length labyrinth algorithm, it is characterized in that 1, this method realizes successively according to the following steps on computer platform:Circuit layout result, gauze information, unbound document and the technical papers that provides with document form is provided to computing machine step (1) program;The information that step (2) computer program reads in according to step (1) is set up the necessary data structure of wiring process, comprising the gauze tabulation, comprises that in addition the wiring environment of obstacle tabulation is described;The gauze tabulation that step (3) traversal is obtained by step (2), from the gauze attribute, read gauze width W ireWidth value and gauze spacing WirePitch value, both summations are obtained the grid wiring width NetSize of gauze, and with this value structure grid wiring width S set etOfNetSize; Simultaneously, obtain the minimum feature and the distance between centers of tracks value of metal level, and add this grid wiring width set after the summation according to technological requirement; Then, minimum grid wiring width value in this grid wiring width set is composed to unit grids size variable GridUnitSize as initial value;Step (4) travels through this grid wiring width S set etOfNetSize according to following steps, under specification error ERROR control, gauze grid wiring width is carried out standardization, thereby obtain the standardization grid wiring width and the required unit grids size of wiring of institute's wired network; Wherein, standardization grid wiring width is k a times of unit grids size, and k is an integer, is 1 during initialization:Step (4.1) is taken out first current grid wiring width from the set of grid wiring width;Step (4.2) is made comparisons this current grid wiring width and k times of unit grids size: if this current grid wiring width is greater than k times of unit grids size, then k increases 1 automatically, until current grid wiring width is less than or equal to k times of unit grids size, then judge: if the difference of k times of unit grids size and current grid wiring width is greater than specification error ERROR, then the unit grids size value is modified to half of original value, simultaneously the k value is reset to 1, return step (4.1), current grid wiring width is pointed to described first current grid wiring width again; Otherwise, enter step (4.3);The value of k times of unit grids size of step (4.3) record is given the standardization grid wiring width amount SNetSize of corresponding gauze with it;Step (4.4) the described method in (4.1) ~ (4.3) is set by step calculated all remaining grid wiring width in the described grid wiring width set, and gives corresponding standard grid wiring width SNetSize;The tabulation of step (5) traversal gauze is pressed descending sort to gauze according to the size of standardization grid wiring width, the gauze tabulation OrderedNetList after obtaining sorting;Step (6) is allocated in advance gauze cloth line position according to the practical wiring layer VirtualLayer of gauze priority and gauze;Step (7) is set up wiring grid with the unit grids size as the unit grids size, and its border of mark is " unavailable " state; Described grid uses following two-dimentional short array representation, and wherein 0 represents net point " available ", 1 expression net point " unavailable ";The tabulation of step (8) traversal obstacle, in the enterprising row labels of grid chart, the value of corresponding array is labeled as 1 to all obstacles;Step (9) travels through the pin tabulation PinList and the pin of equal value tabulation EqualPinList of every gauze according to the following steps, all pin and the pins of equal value of mark on grid chart, and pin is mapped as an available net point carries out to guarantee follow-up wiring algorithm:Step (9.1) is set up candidate mappings point set SetOfCandidate: all pins and pin of equal value are coveredNet point record in the set of described candidate mappings point;Step (9.2) is removed underproof point in the candidate mappings point: judge each candidate point begins to corresponding gauze whether occupied by all net points of pre-assigned wiring layer from actual place layer, if then this net point is removed from the set of candidate mappings point; Otherwise, be retained in the set;Step (9.3) is set up the map grids point sequence ListOfMappingPoint of each pin: if the point in the candidate collection is covered by pin or pin of equal value, then this point is added into the map grids point sequence, and has high priority; If have only unique point in the candidate collection, then this point is added into the map grids point sequence, and has high priority; Otherwise, other points are assigned to the map grids point sequence of respective pins, and according to this point its priority of distance decision apart from the pin central point, high more the closer to the net point priority at center; Be combined into empty pin for the candidate mappings point set, be labeled as " mapping failure ", but then this gauze wouldn't cloth because of layout or systematic error reason;Gauze tabulation after the ordering that step (10) traversal step (5) obtains, use multiple step length labyrinth algorithm that gauze is implemented wiring according to the following steps:Read the current gauze that will connect up the gauze tabulation of step (10.1) after ordering, if gauze is the multiterminal gauze, then it is decomposed into several two-terminal gauzes, and set up subnet tabulation SubNetList, their standardization grid wiring width is k a times of unit grids size, and then k is the largest extension step-length of current gauze;The described subnet tabulation of step (10.2) traversal, begin gauze is carried out the labyrinth expansion from one of them end points of two-terminal gauze, according to the extended method of multiple step length labyrinth algorithm, current point can be eastwards, south, west, north four direction are expanded selectively, and its step-length is between 1 to k;If: the topological coordinate of current point is that (CurrentTopoX CurrentTopoY), then when expansion, check whether the unit grids point of ± k/2 vertical with propagation direction is available; If a bit be " unavailable " state arbitrarily along having on the position of maximum m the unit grids of propagation direction, then Kuo Zhan step-length is (m-1), and wherein, m is the arbitrary integer between 1 to k; To write down corresponding expansion cost during expansion, estimate the cost that will take place comprising the cost that expands to current location with when expanding to impact point; Wherein, when vertically expanding, the unit grids point range of described ± k/2 fromArrive
When along continuous straight runs is expanded, the unit grids point range of described ± k/2 from
Arrive
Step (10.3) begins to carry out the labyrinth expansion according to the described method of step (10.2) from another end points of two-terminal gauze;When step (10.4) intersects when the net point that goes out from two endpoint extension, stop expansion, begin to backtrack to two end points directions respectively from intersection point, promptly from intersection point, search for the father node of current point successively,, then select the node of described expansion cost minimum if there are a plurality of father nodes, up to two end points backtracking two end line nets, thereby determine final path;Step (10.5) line screen according to structure in record wiring result, and at grid array acceptance of the bid note institute cloth subnet, and judge: if cloth is intact for all subnets of this gauze, execution in step (10.2); Otherwise cloth is not intact if go back wired network, execution in step (10.1); Otherwise, execution in step (11);Step (11) is output as layout file to all wiring results by the CIF form.
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