CN100422970C - Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment - Google Patents
Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment Download PDFInfo
- Publication number
- CN100422970C CN100422970C CNB2006100988312A CN200610098831A CN100422970C CN 100422970 C CN100422970 C CN 100422970C CN B2006100988312 A CNB2006100988312 A CN B2006100988312A CN 200610098831 A CN200610098831 A CN 200610098831A CN 100422970 C CN100422970 C CN 100422970C
- Authority
- CN
- China
- Prior art keywords
- data
- packet
- buffer
- spi
- pointer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000002093 peripheral effect Effects 0.000 title claims description 68
- 239000000872 buffer Substances 0.000 claims abstract description 101
- 238000012986 modification Methods 0.000 claims description 4
- 230000004048 modification Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 101000823103 Equus caballus Alpha-1-antiproteinase 4 Proteins 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses a method to receive the PCI Express bus data by a high-speed serial interface device. It includes: many buffers are set out of the serial interface; the serial external interface device receives the data by one of the Buffer when it receives the data of PCI Express bus data, also it can monitor the storage state of the buffer; when the Buffer is full of the data, it will change to the Buffer without data to receive the data continuously.
Description
Technical field
The present invention relates to the method for quick peripheral assembly interconnecting (PCI Express) bus data transmission, relate in particular to the method that a kind of Serial Peripheral Interface (SPI) equipment receives PCI Express bus data.
Background technology
Quick peripheral assembly interconnecting (PCI Express) technology is to propose on the basis of periphery component interconnection (PCI, Peripheral Component Interconnect) technology and grow up.The PCIExpress bussing technique has plurality of advantages, such as: transmission speed is fast, flexible expansion, low power consumption is supported synchronous data transmission, have packet and layer protocol framework, each physical link contains the multiple spot tunnel, can keep the integrality of end-to-end data transmission, has error reporting and processing capacity, conserve space keeps and the PCI compatibility at software layer.Because PCI Express bussing technique has above-mentioned plurality of advantages, thus admitting of industry obtained rapidly, and be known as bus standard of future generation by everybody.
The maximum characteristics of PCI Express bussing technique are to adopt point-to-point mode connected in series, allow to set up between each equipment independently data transmission channel.Need not so also just arrive the high bandwidth that other interfacing equipments are unable to reach easily again to the total system bandwidth on demand.
Serial Peripheral Interface (SPI) (SPI, Serial Peripheral Interface) is a kind of high-speed synchronous serial communication interface of new development in recent years, and this interface can be finished the transmission of data by a clock cable and two data lines.By SPI microprocessor controller (MCU, MicroprocessorControl Unit) and various peripherals are communicated with exchange message with serial mode.At present, the SPI interface is integrated in the multiple flush bonding processor widely.
In a lot of system designs, need to send data to a Serial Peripheral Interface (SPI) equipment of accord with PCI Express bus protocol by PCI Express bus interface, such as: the 4th grade of Serial Peripheral Interface (SPI) (SPI-4).After Serial Peripheral Interface (SPI) equipment receives PCI Express bus data bag, each packet is all needed to resolve, and then copy to the region of memory that sets in advance in order to using.When Serial Peripheral Interface (SPI) equipment receives PCI Express bus data in enormous quantities, will cause the Serial Peripheral Interface (SPI) equipment performance to descend, even obliterated data.
Summary of the invention
In view of this, the technical matters that the present invention solves provides the method that a kind of Serial Peripheral Interface (SPI) equipment receives PCI Express bus data, can make Serial Peripheral Interface (SPI) equipment receive the PCIExpress bus data in enormous quantities.
The present invention includes:
Serial Peripheral Interface (SPI) equipment is provided with a plurality of impact damper Buffer;
When needs received quick peripheral assembly interconnecting PCI Express bus data, Serial Peripheral Interface (SPI) equipment received data by one of them Buffer, and the store status of monitoring Buffer;
When this Buffer is filled with data, the Buffer of current reception data is switched to the Buffer that does not have data, continue to receive data at new current Buffer.
Wherein, Serial Peripheral Interface (SPI) equipment judges whether be filled with data among the Buffer by the Buffer status register, when the Buffer status register is first preset value, and expression Buffer full of data; When the Buffer status register is second preset value, there are not data among the expression Buffer;
Serial Peripheral Interface (SPI) equipment judges whether the data that receive meet the condition of pre-seting, and for qualified data pointer is set;
Revise described pointer, the valid data with in the described data of described pointed connect amended pointer by chained list;
Serial Peripheral Interface (SPI) equipment reads described valid data by chained list.
Wherein, Serial Peripheral Interface (SPI) equipment switches register by Buffer the Buffer of current reception data is switched to the Buffer that does not have data.
Wherein, further comprise:
After Buffer is filled with data, the data among this Buffer of Serial Peripheral Interface (SPI) device processes, after handling the data of this Buffer, the status register of this Buffer is set to second preset value.
Wherein, described PCI Express bus data is a PCI Express bus data bag.
Wherein, described PCI Express bus data is to meet packet and the corresponding address information that presets form.
Wherein, further comprise:
Wherein, when described PCI Express bus data was PCI Express bus data bag, this packet met the condition of pre-seting if the address in the packet that receives is within its address realm that pre-sets; Otherwise this packet does not meet the condition of pre-seting.
Wherein, Serial Peripheral Interface (SPI) equipment is that packet is provided with pointer according to following step:
The address list item of Serial Peripheral Interface (SPI) equipment pointer is set to the first address of this packet, and the big or small list item of pointer is set to length and this data packet head message length sum of the valid data of this packet.
Wherein, the method for the described pointer of Serial Peripheral Interface (SPI) apparatus modifications is: the address list item of pointer is set to first address and this data packet head message length sum of this packet, and the big or small list item of pointer is set to the length of the valid data of this packet.
Wherein, when described PCI Express bus data be that the address that if described address information is a Peripheral Interface Device to pre-set, then described packet meets the condition of pre-seting when meeting the packet that presets form and corresponding address information; Otherwise described packet does not meet the condition of pre-seting.
Wherein, Serial Peripheral Interface (SPI) equipment is that packet is provided with pointer according to following step:
Serial Peripheral Interface (SPI) equipment is saved in packet the storage space of application, the address list item of pointer is set to the first address information of described storage space, and the big or small list item of pointer is set to the length and the data packet head message length sum of valid data in this packet.
Wherein, the method for the described pointer of Serial Peripheral Interface (SPI) apparatus modifications is: the address list item of pointer is set to first address and this data packet head message length sum of this packet, and the big or small list item of pointer is set to the length of the valid data of this packet.
Wherein, programming device is converted to packet and the corresponding address information that presets form with its PCI Express bus data bag that receives, and described packet and address information are sent to Serial Peripheral Interface (SPI) equipment.
In the present invention, Serial Peripheral Interface (SPI) equipment is provided with a plurality of impact dampers, for each Buffer is provided with status register respectively, and Buffer switching register is set; When needs received quick peripheral assembly interconnecting PCIExpress bus data, Serial Peripheral Interface (SPI) equipment received data by one of them Buffer, and detected the status register of this Buffer; When the status register of this Buffer is indicated this Buffer full of data, switch register by Buffer the Buffer of current reception data is switched to other Buffer, continue to receive data at new current Buffer.As can be seen, switch the reception data, can improve operating factor of memory space, thereby can make Serial Peripheral Interface (SPI) equipment receive the PCIExpress bus data in enormous quantities by a plurality of Buffer.The present invention also for the PCI Express bus data that receives is provided with pointer, makes pointer directly point to valid data simultaneously, and connects pointer by chained list.And then can make Serial Peripheral Interface (SPI) equipment by operation to chained list, directly obtain the valid data in the PCI Express bus data.
Description of drawings
Fig. 1 a is by switching the process flow diagram that impact damper receives PCI Express bus data;
Fig. 1 b is the process flow diagram of embodiment 1;
Fig. 2 is the pointer structure synoptic diagram of storage space;
Fig. 3 is the synoptic diagram of chained list among the embodiment 1;
Fig. 4 is the synoptic diagram after chained list is modified among the embodiment 1;
Fig. 5 is the process flow diagram of the embodiment of the invention 2;
Fig. 6 is the synoptic diagram that programming device sends data among the embodiment 2;
Fig. 7 is the process flow diagram of SPI-4 interfacing equipment deal with data among the embodiment 2.
Embodiment
In the present invention, Serial Peripheral Interface (SPI) equipment switches reception PCI Express bus data by a plurality of Buffer, and in conjunction with Fig. 1 a, its detailed process comprises:
Step 101:
Serial Peripheral Interface (SPI) equipment is provided with a plurality of impact dampers, for each Buffer is provided with status register respectively, and Buffer switching register is set.
Wherein, when the value in the status register of Buffer is " 1 ", full of data among the expression Buffer; When the value in the status register of Buffer is " 0 ", there are not data among the expression Buffer.
Step 102:
When needs received quick peripheral assembly interconnecting PCI Express bus data, Serial Peripheral Interface (SPI) equipment received data by one of them Buffer.
Step 103:
Whether the status register that detects this Buffer is full, and promptly whether the value of the status register of this Buffer is " 1 ", if then execution in step 104; Otherwise, execution in step 105.
Step 104:
Switch register by Buffer the Buffer of current reception data is switched to the Buffer that does not have data, continue to receive data at new current Buffer.
Step 105:
The Buffer of current reception data continues to receive data, and continues to detect the status register of this Buffer.
When receiving new data, can handle the data among the Buffer that receives full data, in time the space is discharged after handling data, and the value of status register is set to " 0 ", wait for Data Receiving next time, thereby help the recycling of Buffer, save spatial cache.
Below, be example with the SPI-4 interfacing equipment, 1 pair of this method is done further and is specified in conjunction with the embodiments.
Referring to Fig. 1 b, a kind of Serial Peripheral Interface (SPI) equipment receives the method for quick peripheral assembly interconnecting bus data, comprising:
Step 11:
PCI Express bus interface equipment is prepared to send data to the SPI-4 interfacing equipment, and with the size of these data, the relevant informations such as destination address of the internal memory that deposit send together, and its detailed process comprises:
PCI Express bus interface equipment is prepared to send data to the SPI-4 interfacing equipment, the size of these data, and the 1K Bit data, this deposit data is 0000～03FF at the storage space of SPI-4 interfacing equipment.
Step 12:
PCI Express bus interface equipment advances corresponding data encapsulation the packet of a plurality of accord with PCI Express bus protocols, corresponding address information, size of data and other relevant information are encapsulated in the header of packet into, then described packet is all sent to the SPI-4 interfacing equipment, its detailed process comprises:
At first, the 1K Bit data that PCI Express bus interface equipment will leave 0000～03FF address space of SPI-4 interfacing equipment in encapsulates into 3 packets: 256 bytes are encapsulated into packet 1, and corresponding address information is 0000～00FF; 512 bytes are encapsulated into packet 2, and corresponding address information is 0100～02FF; 256 bytes are encapsulated into packet 3, and corresponding address information is 0300～03FF.
Then, be respectively packet 1, packet 2 and packet 3 encapsulation header information, comprise the first address of the address information of corresponding data in the header, promptly 0000,0100 and 0300, valid data size in the packet, i.e. 256 bytes, 512 bytes and 256 bytes, and other relevant informations.
At last, packet 1, packet 2 and packet 3 are sent to the SPI-4 interfacing equipment.
Step 13:
The SPI-4 interfacing equipment receives data by a plurality of impact dampers (Buffer), and its process comprises:
The SPI-4 interfacing equipment sets in advance a plurality of Buffer, is Buffer0, Buffer1 and Buffer2, and is that each Buffer is provided with status register respectively and Buffer switches register.The value of the status register by Buffer, whether can know among the Buffer full of data, if full of data among the Buffer of current reception data, then switch register pair current Buffer is switched to the Buffer that does not have data, continue to receive data at new current Buffer by Buffer.
For example: when data arrived, the SPI4 interfacing equipment at first received data by Buffer0, monitored the status register of the Buffer0 of current reception data simultaneously, to obtain the state of Buffer0.
After the Buffer0 of current reception data is filled with data, the SPI4 interfacing equipment will switch the Buffer that register will receive data by Buffer and switch to Buffer1, continue to receive data by Buffer1.
The SPI4 interfacing equipment will switch the Buffer that register will receive data by Buffer and switch to Buffer2 after Buffer1 is filled with data, continue to receive data by Buffer2.
When Buffer1 or Buffer2 reception data, the SPI-4 interfacing equipment will be handled the data that received.After Buffer2 was filled with data, the SPI-4 interfacing equipment also finished to the data processing among the Buffer0, and the SPI4 interfacing equipment will switch the Buffer that register will receive data by Buffer and switch to Buffer0, continue to receive data by Buffer0.
By said process, realized the recycling of Buffer, improved resource utilization.
Wherein, the status register of monitoring the Buffer of current reception data can be undertaken by hardware (or software or software and hardware combining), its method is a querying method, i.e. the status register of periodic queries Buffer is to know whether full of data of this Buffer; Or be interrupt method, promptly when the Buffer full of data, Buffer status register photos and sending messages is given equipment, so that full of data among this Buffer of device learns.
Wherein, the quantity of Buffer and size can be provided with according to actual conditions, no longer repeat here to illustrate.
Step 14:
The data storage that receives is arrived its inner storage space, and each storage space is connect by chained list, its detailed process comprises:
Data size information in the header of the packet that the SPI-4 interfacing equipment receives by parsing is known the size of valid data in this packet.The SPI-4 interfacing equipment knows by the first address information in the resolution data header packet information whether this packet is packet to be received, if then this packet is left in the storage space that sets in advance; Otherwise, abandoning this packet, its detailed process comprises:
After the SPI-4 interfacing equipment receives packet 1, resolve its header and can know that the size of these packet valid data is 256 bytes, and know described valid data first address information to be deposited 0000.If described valid data treat that the storage addresses space is positioned at address space 0000～03FF that the SPI-4 interfacing equipment is reserved, then the SPI-4 interfacing equipment leaves packet 1 among address space 0000～00FF in; Otherwise, abandon this packet.And the pointer of packet 1 is set, and being pointer 0, the address list item of pointer 0 is the first address of storage packet 1,0000; The big or small list item of this pointer is the size of valid data in the packet 1,256 bytes.
In like manner, the SPI-4 interfacing equipment is left in packet 2 among address space 0100～02FF, packet 3 is left among address space 0300～03FF, and the pointer of packet 2 and packet 3 is set respectively, be pointer 1 and pointer 2.Wherein, the structure of described each pointer as shown in Figure 2.
By chained list 3 pointers are tied, thereby 3 packets are tied, described chained list as shown in Figure 3.
Step 15:
The SPI-4 interfacing equipment is handled described chained list, generates new chained list, and its detailed process comprises:
In conjunction with Fig. 2 and Fig. 3, the address list item of pointer 0 in this chained list is changed to: the header length of first address+packet 1, i.e. 0000+ header length.
In like manner, the address list item of pointer 1 is changed to: 0100+ header length, the address list item of pointer 2 is changed to: 0300+ header length, the synoptic diagram of new chained list as shown in Figure 4.
When the SPI-4 interfacing equipment needs deal with data, can pass through this chained list, directly read corresponding valid data.
In embodiment 1, PCI Express packet is sent straight to Serial Peripheral Interface (SPI) equipment, i.e. the SPI-4 interfacing equipment.In actual conditions, also can be by between the data link of PCI Express interfacing equipment and Serial Peripheral Interface (SPI) equipment, being connected in series programming device, make programming device resolve and obtain wherein valid data to the PCIExpress packet in advance.Programming device sends to Serial Peripheral Interface (SPI) equipment with described valid data by the form that sets in advance again then, thereby makes Serial Peripheral Interface (SPI) equipment can obtain to pre-set the packet of form.
Below, be example with the SPI-4 interfacing equipment, 2 pairs of these methods are done further and are specified in conjunction with the embodiments.
Referring to Fig. 5, a kind of Serial Peripheral Interface (SPI) equipment receives the method for quick peripheral assembly interconnecting bus data, comprising:
Step 51:
Between the data link of PCI Express interfacing equipment and SPI-4 interfacing equipment, be connected in series field programmable gate array (FPGA, Field Programmable Gate-Array), the mode of FPGA to SPI-4 interfacing equipment transmission data is set.
Step 52:
When the SPI-4 interfacing equipment need be when PCI Express bus interface equipment obtains data, to send data request information to PCI Express bus interface equipment, the size and the FPGA that comprise request transmission data in this message deposit the address space information that these data are reserved, and its detailed process is:
The SPI-4 interfacing equipment sends data request information to PCI Express bus interface equipment, comprises in this message that request sends the size of data, and 1K Bit data and FPGA deposit the address space information that these data are reserved, 0000～03FF.
At this moment, because the SPI-4 interfacing equipment is to PCI Express bus interface equipment request msg the time, known 0000～03FF address space that the data of this 1K bit will be stored at FPGA, and the SPI-4 interfacing equipment knows that FPGA transmits data with the form of 256 bit data block to it, so the SPI-4 interfacing equipment can be known this 1K Bit data and will be divided into the data block of 4 256 bits by FPGA, and can know that the first address of 4 data blocks is: A1=0000, A2=0100, A3=0200, A4=0300.
Step 53:
PCI Express bus interface equipment advances corresponding data encapsulation the packet of a plurality of accord with PCI Express bus protocols, corresponding address information, size of data and other relevant information are encapsulated in the header of packet into, then described packet is all sent to FPGA, its detailed process is identical with the described detailed process of step 12 among the embodiment 1, no longer repeat specification here.
Step 54:
After FPGA receives packet from PCI Express bus interface equipment, the data header packet information is resolved, know the storage address space of valid data in the size of this packet and this packet, and leave packet in corresponding address space, its process is specially:
After FPGA receives packet 1, resolve its header, know the first address of length He this deposit data of valid data in this packet, the valid data of 256 bytes are left in the address space of 0000～00FF;
By that analogy, after FPGA receives packet 2 and packet 3, resolve the header of described two packets, then, leave the valid data of 512 bytes of packet 2 address space of 0100～02FF in, the valid data of 256 bytes of packet 3 are left in the address space of 0300～03FF.
Step 55:
The 1K Bit data that FPGA will leave address space 0000～03FF in is divided into the data block of a plurality of equal lengths, and obtains to deposit the corresponding first address information of each data block, and its detailed process comprises:
The 1K Bit data that FPGA will leave address space 0000～03FF in is divided into the data block of 4 256 bytes: data block M1, and its corresponding address information is 0000～00FF, and first address A1 is 0000; Data block M2, its corresponding address information is 0100～01FF, first address A2 is 0100; Data block M3, its corresponding address information is 0200～02FF, first address A3 is 0200; Data block M4, its corresponding address information is 0300～03FF, first address A4 is 0300.
Step 56:
Each data block is packaged into packet respectively, and the sequence information of this packet of mark in the header of each packet sends to the SPI-4 interfacing equipment with described each packet, and its process is specially:
Data block M1, M2, M3, M4 are packaged into 4 packets respectively, are packet D1, packet D2, packet D3 and packet D4, and the sequence information of each packet is encapsulated in the header of corresponding each packet.In the present embodiment, it is 44 bits that the data packet head message length is set, and each length of data package all is 300 bits so, header 44 bits wherein, valid data 256 bits.
Packet D1, packet D2, packet D3 and packet D4 and the corresponding first address A1 of each packet, A2, A3, A4 are transferred to the SPI-4 interfacing equipment by the mode of presetting, and its concrete transmission mode as shown in Figure 6.
Wherein, pse-D is data that preset form, and system does not store it, and can carry out other operation when receiving pse-D; Pse-A is data that preset form, can judge that by it subsequent data block is last data block of this transmission.
Step 57:
The SPI-4 interfacing equipment receives data by a plurality of Buffer, and its detailed process is identical with the described detailed process of step 13 among the embodiment 1, no longer repeat specification here.
Step 58:
The SPI-4 interfacing equipment is handled the data that receive, and its detailed process comprises:
The SPI-4 interfacing equipment knows by the first address information in the resolution data header packet information whether this packet is packet to be received, if, apply for that then storage space also leaves this packet in this storage space in, this packet of pointed is set, each packet is tied by chained list; Otherwise, abandon this packet, referring to Fig. 7, its detailed process comprises:
701, the SPI-4 interfacing equipment is resolved the data that receive, and judges that whether these data are the first address A1 of the address space of the FPGA store data preset, and promptly 0000, if then carry out backward from 702; Otherwise, carry out backward from 703.
702, with the next data of described data, i.e. pse-D, be set to invalid data, and utilize the transmission time application storage space M1 of pse-D, and pointer 1 is set, the address list item of pointer 1 is set to the first address of storage space M1, and the big or small list item of pointer 1 is set to 256 bits.
703, whether the data that judge to receive are A2, promptly 0100, if then carry out backward from 704; Otherwise, carry out backward from 705.
704, leave packet D1 in storage space M1, apply for storage space M2 simultaneously, pointer 2 is set, the address list item of pointer 2 is set to the first address of storage space M2, and the big or small list item of pointer is set to 256 bits.
705, whether the data that judge to receive are A3, promptly 0200, if then carry out backward from 706; Otherwise, carry out backward from 707.
706, leave packet D2 in storage space M2, apply for storage space M3 simultaneously, pointer 3 is set, the address list item of pointer 3 is set to the first address of storage space M3, and the big or small list item of pointer 3 is set to 256 bits.
707, whether the data that judge to receive are A4, promptly 0300, if then carry out backward from 708; Otherwise, carry out backward from 709.
708, leave packet D3 in storage space M3, apply for storage space M4 simultaneously, pointer 4 is set, the address list item of pointer 4 is set to the first address of storage space M4, and the big or small list item of pointer 4 is set to 256 bits.
709, whether the data of reception are pse-A, if then carry out 710; Otherwise, carry out 711.
710, leave packet D4 in storage space M4, finish this data transfer.First address in the address list item of pointer 1, pointer 2, pointer 3 and pointer 4 is all increased by 44 bits, and promptly the length of each data packet head information is tied 4 pointers by chained list.When the SPI-4 interfacing equipment needs deal with data, can pass through this chained list, directly read corresponding valid data.
711, this data transfer is made mistakes or is invalid data transmission, abandons this data transfer.
In embodiment 2, the programming device that is provided with between the data link of PCI Express interfacing equipment and HSSI High-Speed Serial Interface equipment is FPGA, also can CPLD (CPLD in the actual conditions, Complex Programmable Logic Device), can also be other microprocessor, just no longer repeat here for example to understand.
In embodiment 1 and embodiment 2, though all be to be example with the SPI-4 interfacing equipment, method of the present invention can be applied to other HSSI High-Speed Serial Interface equipment that does not possess the data parsing function equally, no longer repeats here for example to understand.
Claims (13)
1. the method for a Serial Peripheral Interface (SPI) equipment reception quick peripheral assembly interconnecting bus data is characterized in that, comprising:
Serial Peripheral Interface (SPI) equipment is provided with a plurality of impact damper Buffer;
When needs received quick peripheral assembly interconnecting PCI Express bus data, Serial Peripheral Interface (SPI) equipment received data by one of them Buffer, and the store status of monitoring Buffer;
When this Buffer is filled with data, the Buffer of current reception data is switched to the Buffer that does not have data, continue to receive data at new current Buffer;
Serial Peripheral Interface (SPI) equipment judges whether the data that receive meet the condition of pre-seting, and for qualified data pointer is set;
Revise described pointer, the valid data with in the described data of described pointed connect amended pointer by chained list;
Serial Peripheral Interface (SPI) equipment reads described valid data by chained list.
2. method according to claim 1 is characterized in that, Serial Peripheral Interface (SPI) equipment judges whether be filled with data among the Buffer by the Buffer status register, when the Buffer status register is first preset value, and expression Buffer full of data; When the Buffer status register is second preset value, there are not data among the expression Buffer.
3. method according to claim 2 is characterized in that, Serial Peripheral Interface (SPI) equipment switches register by Buffer the Buffer of current reception data is switched to the Buffer that does not have data.
4. method according to claim 2 is characterized in that, further comprises:
After Buffer was filled with data, the data among this Buffer of Serial Peripheral Interface (SPI) device processes after handling the data of this Buffer, emptied this Buffer, and the status register of this Buffer is set to second preset value.
5. method according to claim 1 is characterized in that, described PCI Express bus data is a PCI Express bus data bag.
6. method according to claim 1 is characterized in that, described PCI Express bus data is to meet packet and the corresponding address information that presets form.
7. method according to claim 1, it is characterized in that, when described PCI Express bus data was PCI Express bus data bag, this packet met the condition of pre-seting if the address in the packet that receives is within its address realm that pre-sets; Otherwise this packet does not meet the condition of pre-seting.
8. method according to claim 7 is characterized in that, Serial Peripheral Interface (SPI) equipment is that packet is provided with pointer according to following step:
The address list item of Serial Peripheral Interface (SPI) equipment pointer is set to the first address of this packet, and the big or small list item of pointer is set to length and this data packet head message length sum of the valid data of this packet.
9. method according to claim 8, it is characterized in that, the method of the described pointer of Serial Peripheral Interface (SPI) apparatus modifications is: the address list item of pointer is set to first address and this data packet head message length sum of this packet, and the big or small list item of pointer is set to the length of the valid data of this packet.
10. method according to claim 1, it is characterized in that, when described PCI Express bus data is that the address that if described address information is a Peripheral Interface Device to pre-set, then described packet meets the condition of pre-seting when meeting the packet that presets form and corresponding address information; Otherwise described packet does not meet the condition of pre-seting.
11. method according to claim 10 is characterized in that, Serial Peripheral Interface (SPI) equipment is that packet is provided with pointer according to following step:
Serial Peripheral Interface (SPI) equipment is saved in packet the storage space of application, the address list item of pointer is set to the first address information of described storage space, and the big or small list item of pointer is set to the length and the data packet head message length sum of valid data in this packet.
12. method according to claim 11, it is characterized in that, the method of the described pointer of Serial Peripheral Interface (SPI) apparatus modifications is: the address list item of pointer is set to first address and this data packet head message length sum of this packet, and the big or small list item of pointer is set to the length of the valid data of this packet.
13. method according to claim 6, it is characterized in that, programming device is converted to packet and the corresponding address information that presets form with its PCI Express bus data bag that receives, and described packet and address information are sent to Serial Peripheral Interface (SPI) equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100988312A CN100422970C (en) | 2006-07-13 | 2006-07-13 | Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100988312A CN100422970C (en) | 2006-07-13 | 2006-07-13 | Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1889067A CN1889067A (en) | 2007-01-03 |
| CN100422970C true CN100422970C (en) | 2008-10-01 |
Family
ID=37578346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100988312A Expired - Fee Related CN100422970C (en) | 2006-07-13 | 2006-07-13 | Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100422970C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1115547A (en) * | 1994-01-18 | 1996-01-24 | 大宇电子株式会社 | Adaptive bit stream demultiplexing apparatus in a decoding system |
| CN1503120A (en) * | 2002-11-20 | 2004-06-09 | 智慧第一公司 | Continuous multi-buffering random number generator and random number generation method |
| US20050154804A1 (en) * | 2004-01-08 | 2005-07-14 | Heath Stewart | Switch for bus optimization |
-
2006
- 2006-07-13 CN CNB2006100988312A patent/CN100422970C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1115547A (en) * | 1994-01-18 | 1996-01-24 | 大宇电子株式会社 | Adaptive bit stream demultiplexing apparatus in a decoding system |
| CN1503120A (en) * | 2002-11-20 | 2004-06-09 | 智慧第一公司 | Continuous multi-buffering random number generator and random number generation method |
| US20050154804A1 (en) * | 2004-01-08 | 2005-07-14 | Heath Stewart | Switch for bus optimization |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1889067A (en) | 2007-01-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3694165B1 (en) | Managing congestion in a network | |
| CN102780705B (en) | Ethernet-(controller area network) CAN protocol converter | |
| WO2016187813A1 (en) | Data transmission method and device for photoelectric hybrid network | |
| CN107079017B (en) | Message conversion method and device | |
| CN101707544B (en) | E1 channel multidirectional network bridge transmission method | |
| CN101258719A (en) | Method to extend the physical reach of an Infiniband network | |
| KR20030080443A (en) | Internet protocol system using hardware protocol processing logic and the parallel data processing method using the same | |
| Flammini et al. | Sensor interfaces: from field-bus to Ethernet and Internet | |
| EP2723031B1 (en) | Distributed measurement arrangement for an embedded automotive acquisition device with tcp acceleration | |
| US7269661B2 (en) | Method using receive and transmit protocol aware logic modules for confirming checksum values stored in network packet | |
| CN112395230A (en) | UART interface extension circuit based on programmable logic device | |
| CN101242284B (en) | Communication method and network device based on SPI bus | |
| CN100499666C (en) | System and method for inter connecting SP14 equipment and PCI Express equipment | |
| US11973826B2 (en) | Data transmission method and automation communication network | |
| US6483840B1 (en) | High speed TCP/IP stack in silicon | |
| CN108614792B (en) | 1394 transaction layer data packet storage management method and circuit | |
| TW200415474A (en) | Method and apparatus for intermediate buffer segmentation and reassembly | |
| US7853706B2 (en) | Method, interface and network for cyclical sending of Ethernet telegrams | |
| CN109361723B (en) | UDP (user Datagram protocol) effective message sending time sequence control method | |
| US20060062229A1 (en) | Terminal adapter device capable of performing IEEE1394-to-Ethernet conversion | |
| CN112968822A (en) | One-master multi-slave real-time communication system and method based on Ethernet PHY | |
| CN100422970C (en) | Method for receiving fast peripheral assembly interconnected bus data by serial external interface equipment | |
| KR20080106203A (en) | Method and device for transmitting data packets | |
| CN113347017A (en) | Network communication method and device, network node equipment and hybrid network | |
| US20050041606A1 (en) | Data communication apparatus, data communication method, data communication program and recording medium in which data communication program was recorded |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: NEW H3C TECHNOLOGIES Co.,Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: HANGZHOU H3C TECHNOLOGIES Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081001 |