CN100421225C - Method for improving hole mobility of PMOS field effect transistor - Google Patents
Method for improving hole mobility of PMOS field effect transistor Download PDFInfo
- Publication number
- CN100421225C CN100421225C CNB2004100746776A CN200410074677A CN100421225C CN 100421225 C CN100421225 C CN 100421225C CN B2004100746776 A CNB2004100746776 A CN B2004100746776A CN 200410074677 A CN200410074677 A CN 200410074677A CN 100421225 C CN100421225 C CN 100421225C
- Authority
- CN
- China
- Prior art keywords
- energy
- dosage
- sio
- hole mobility
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000005669 field effect Effects 0.000 title abstract description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 238000001020 plasma etching Methods 0.000 claims description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000354 decomposition reaction Methods 0.000 claims 2
- 230000004913 activation Effects 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract 3
- 238000005280 amorphization Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A method for improving hole mobility of PMOS field effect transistor is to introduce desired stress in channel region by process induced stress engineering to improve hole mobility in channel. The core of the method is low-energy BF in PMOS extension region2Before (or B) implantation, firstly carrying out Ge pre-amorphization implantation on the Si extension region, and then carrying out low-energy implantation BF2Or B. The method not only improves the activation efficiency of B, greatly reduces the sheet resistance of the PMOS extension region, but also greatly improves the hole mobility, and the essence is caused by the change of an energy band structure of a channel region under the action of stress.
Description
Technical field
The invention belongs to semiconductor device technology, relate to the method for a kind of raising P-type mos (PMOS) field-effect transistor hole mobility in more detail.
Background technology
" power consumption-speed " predicament that present IC faces is the main bottleneck that hinders the very large scale integration technology development.Improving device carrier channels mobility is one of key that solves above-mentioned predicament.On the basis that channel mobility promotes significantly, can adopt lower supply voltage and higher threshold value drain voltage on the one hand, favourable to reducing power consumption; Simultaneously can guarantee that again device has enough current driving abilities and speed.Utilizing strain engineering is to improve one of most promising technology of charge carrier effective mobility.Proposed much to improve the method for charge carrier effective mobility, as: go up to form the rise technology of strained silicon of twin shaft at relaxation edge germanium silicon (SiGe) and shown and can improve carrier mobility, but it is difficult to be integrated in the CMOS technology and goes, because its complex process, defective is many, has shortcomings such as self-heating effect and cost height.Can introduce the stress of wishing at channel region and induce stress engineering, thereby significantly improve carrier mobility based on the technology of traditional Si base CMOS technology.As uniaxial strain silicon technologies such as embedded SiGe source/leakage engineering, stress cap layer, stress storage technologies, they are more superior than the common twin shaft processes with strained silicon that rises, but still many shortcomings are arranged, as embedded SiGe source/leakage engineering, need increase source/processing steps such as leakage burn into selective epitaxy, its complex process, difficulty is big, and the process integration difficulty, the difficult control of rate of finished products.And the present invention be by in the source/drain extension region injects Ge, thereby induce a kind of method that stress improves hole mobility at channel region, this method and traditional cmos process are compatible fully, and it is simple for process, do not need to increase mask yet, can be integrated into easily in the CMOS technology and go, not only cost is low, and effect is very good, not only improved the activation efficiency of boron, PMOS extension area sheet resistance is reduced greatly, the more important thing is that it increases substantially hole mobility, thereby significantly improved device and circuit performance.And dwindling along with device feature size, the effect that hole mobility improves is more remarkable (as: under the 1.2MV/cm longitudinal electric field, when channel length is 90 nanometers, hole mobility improves 26%, and when channel length narrowed down to 35 nanometers, hole mobility then improved 43%), these characteristics are consistent with the trend of large scale integrated circuit development, show that fully the present invention has the advantage of sustainable development, thereby have more value and the rosy prospect of applying.
Summary of the invention
The objective of the invention is to induce stress engineering and improve hole mobility in the raceway groove at the stress of channel region introducing hope by technology.
The core of this method is at PMOS extension area low energy boron difluoride (BF
2) or before boron (B) injected, at first the Si extension area to PMOS carried out the pre-amorphous injection of germanium (Ge), and then low energy is injected BF
2Or B.This method has not only improved the activation efficiency of B, and PMOS extension area sheet resistance is reduced greatly, the more important thing is that it increases substantially hole mobility, and its essence is that channel region is due to band structure changes under stress.The concrete steps of this method are as follows:
Step 1: after the reactive ion etching polysilicon forms gate electrode, low-pressure chemical vapor deposition method (LPCVD) deposition tetraethoxysilane (TEOS), thermal decomposition forms a SiO
2Film;
Step 2: reactive ion etching the one SiO
2Film forms first side wall;
Step 3: the decrystallized injection of germanium;
Step 4:BF
2(or B) low energy is injected;
Step 5:LPCVD deposits tetraethoxysilane, and thermal decomposition forms the 2nd SiO
2Film;
Step 6: reactive ion etching the 2nd SiO
2Film forms second side wall;
Step 7:BF
2Source/leakage is injected;
Step 8: rapid thermal annealing (RTA).
Step 1 wherein: be after finishing conventional local field oxidation isolation and active area, form gate medium, deposit polysilicon film on it, then carry out photoetching and reactive ion etching, form polygate electrodes, the low-pressure chemical vapor deposition method deposits TEOS then, and 740-750 ℃ of thermal decomposition forms a SiO
2Film, thickness 20-40nm;
Step 2 wherein: reactive ion etching the one SiO
2Film forms first side wall, pressure 200-250m τ, radio frequency (RF) power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
Step 3 wherein: the decrystallized injection of germanium: energy 15-40Kev, dosage 2-8 * 10
14Cm
-2
Step 4:BF wherein
2Low energy is injected: BF
2Energy 5-8Kev, dosage 3-6 * 10
14Cm
-2
Wherein step 5:LPCVD deposits TEOS, and 710-750 ℃ of thermal decomposition forms the 2nd SiO
2Film, thickness 100-150nm;
Step 6 wherein: reactive ion etching the 2nd SiO
2Film forms second side wall, pressure 200-250m τ, RF power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm;
Step 7:BF wherein
2Source/leakage is injected: energy 25-35Kev, dosage 1.5-3 * 10
15Cm
-2
Wherein step 8:RTA temperature is 1000-1020 ℃, time 4-8 second, formation source/drain junction.
Description of drawings
Fig. 1 has provided SIMS profile analysis result, process decrystallized injection of Ge and BF
2Low energy is injected and the sample of sample behind RTA and the not decrystallized injection of process Ge compares.
Thereby Fig. 2 has provided Ge at the schematic diagram of the decrystallized injection of source/drain extension region at channel region introducing stress.
Fig. 3 has compared the input characteristics of the PMOS device that decrystallized injection of Ge (b) and the decrystallized injection of no Ge (a) are arranged.
Embodiment
Condition according to summary of the invention provides all can reach effect of the present invention, so the following examples are just with helping understand the present invention, and non-limiting scope of the present invention.In addition, equipment used in the present invention etc. all are semiconductor device technology equipment commonly used, and this point is that those skilled in the art are familiar with, thereby the present invention does not do any description to employed apparatus.
Embodiment:
Step 1) local field oxide thickness is SiO
2300nm, nitrogenize gate medium 1.4nm, polysilicon thickness 180nm on it then carries out photoetching and reactive ion etching, forms polygate electrodes, and LPCVD deposits TEOS then, and 720 ℃ of thermal decompositions form a SiO
2Film, thickness 30nm;
Step 2) reactive ion etching the one SiO
2Film forms first side wall, RF power 300W, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm, operating pressure 200m τ, terminal point trigger and end, and do not have quarter, 7 seconds soft quarters;
The decrystallized injection of step 3) germanium (Ge): energy 20Kev, dosage 3 * 10
14Cm
-2
Step 4) BF
2Low energy is injected: energy 6Kev, dosage 5 * 10
14Cm
-2
Step 5) LPCVD deposits TEOS, and 720 ℃ of thermal decompositions form the 2nd SiO
2Film, thickness 120nm;
Step 6) reactive ion etching the 2nd SiO
2Film forms second side wall, RF power 300W, pressure 200m τ, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm crosses and carved 7 seconds soft quarters 1 second;
Step 7) BF
2Source/leakage is injected: 30Kev, 2.5 * 10
15Cm
-2
Step 8) RTA, 1005 ℃, 4 seconds.
As seen from Figure 1, adopting the PMOS extension area junction depth of the sample of the decrystallized injection of Ge is 31nm, will reduce about 46% than the sample junction depth of the decrystallized injection of no Ge, simultaneously because the injection of Ge, improved the activity ratio of B, it is about 100% that super shallow junction surface concentration is improved, and sheet resistance reduces 35%.
As can be seen from Figure 3, the sample of the decrystallized injection of Ge is arranged, driven saturated power supply I
OsImproved 27%.This is because the decrystallized injection of Ge has been introduced a uniaxial compressive stress to raceway groove, as shown in Figure 2, because first side wall is extremely thin, make the distance at stress riser and raceway groove center shorter, so this uniaxial compressive stress is stronger to channelling, the result has improved the hole mobility of PMOS device greatly, with the PMOS device comparison of the decrystallized injection of no Ge, its hole mobility improves 26%, at less OFF leakage current I
OffObtained big ON state saturation current I down,
On
In sum, the present invention can improve the pmos fet hole mobility significantly, and source drain extension region sheet resistance is significantly reduced, and the two all makes the device current driving force improve greatly, and keeps low OFF leakage current simultaneously.
Claims (9)
1. method that improves the pmos fet hole mobility may further comprise the steps:
Step 1: after the reactive ion etching polysilicon forms gate electrode, low-pressure chemical vapor deposition method deposition tetraethoxysilane, 710-750 ℃ of thermal decomposition forms a SiO
2Film, thickness 20-40nm;
Step 2: reactive ion etching the one SiO
2Film forms first side wall, pressure 200-250m τ, radio-frequency power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
Step 3: the decrystallized injection of germanium, energy 15-40Kev, dosage 2-8 * 10
14Cm
-2
Step 4:BF
2Or B low energy is injected energy 5-8Kev, dosage 3-6 * 10
14Cm
-2
Step 5: low-pressure chemical vapor deposition method deposition tetraethoxysilane, 710-750 ℃ of thermal decomposition forms the 2nd SiO
2Film, thickness 100-150nm;
Step 6: reactive ion etching the 2nd SiO
2Film forms second side wall, pressure 200-250m τ, radio-frequency power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm;
Step 7:BF
2Source/leakage is injected, energy 25-35Kev, dosage 1.5-3 * 10
15Cm
-2
Step 8: rapid thermal annealing, temperature 1000-1020 ℃, time 4-8 second, formation source/drain junction.
2. the method for claim 1 is characterized in that, heat decomposition temperature is 720 ℃ in the step 1, thickness 30nm.
3. the method for claim 1 is characterized in that, the radio-frequency power 300W in the step 2, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm, operating pressure 200m τ, 7 seconds soft quarters.
4. the method for claim 1 is characterized in that, the decrystallized injection energy of germanium 20Kev in the step 3, dosage 3 * 10
14Cm
-2
5. the method for claim 1 is characterized in that, the energy 6Kev in the step 4, dosage 5 * 10
14Cm
-2
6. the method for claim 1 is characterized in that, the heat decomposition temperature in the step 5 is 720 ℃, thickness 120nm.
7. the method for claim 1 is characterized in that, radio-frequency power 300W in the step 6, pressure 200m τ, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm crosses and carved 7 seconds soft quarters 1 second.
8. the method for claim 1 is characterized in that, the energy 30Kev in the step 7, dosage 2.5 * 10
15Cm
-2
9. the method for claim 1 is characterized in that, the temperature of rapid thermal annealing is 1005 ℃ in the step 8,4 seconds time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100746776A CN100421225C (en) | 2004-09-13 | 2004-09-13 | Method for improving hole mobility of PMOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100746776A CN100421225C (en) | 2004-09-13 | 2004-09-13 | Method for improving hole mobility of PMOS field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1750242A CN1750242A (en) | 2006-03-22 |
| CN100421225C true CN100421225C (en) | 2008-09-24 |
Family
ID=36605596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100746776A Expired - Lifetime CN100421225C (en) | 2004-09-13 | 2004-09-13 | Method for improving hole mobility of PMOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100421225C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008035816B4 (en) * | 2008-07-31 | 2011-08-25 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 | Increase performance in PMOS and NMOS transistors by using an embedded deformed semiconductor material |
| CN102054695B (en) * | 2009-10-29 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for improving performance of semiconductor components |
| CN102130054B (en) * | 2010-01-20 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Method for improving divergence of cut-off leakage current of semiconductor device |
| CN102420138A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of transistor |
| CN103021827B (en) * | 2011-09-27 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming finned field effect transistor and complementary metal oxide semiconductor (CMOS) finned field effect transistor |
| CN102569408A (en) * | 2012-02-28 | 2012-07-11 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Silicon) unit transistor with high erasing speed and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030080361A1 (en) * | 2001-11-01 | 2003-05-01 | Anand Murthy | Semiconductor transistor having a stressed channel |
-
2004
- 2004-09-13 CN CNB2004100746776A patent/CN100421225C/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030080361A1 (en) * | 2001-11-01 | 2003-05-01 | Anand Murthy | Semiconductor transistor having a stressed channel |
Non-Patent Citations (3)
| Title |
|---|
| A 90nm High Volume Manufacturing Logic TechnologyFeaturing Novel 45nm Gate Length Strained Silicon CMOSTransistors. T. Ghani.IEDM Technical Digest. 2003 * |
| Low Temperature (<=800C) Recessed JunctionSelective Silicon-Germanium Source/Drain Technology forsub-70 nm CMOS. Shyam Gannavaram.IEDM Technical Digest. 2000 * |
| Strained Silicon MOSFET Technology. J.L.Hoyt.IEDM Technical Digest. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1750242A (en) | 2006-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100524666C (en) | Method for manufacturing transistor structure | |
| CN1728402B (en) | Ultra-thin body super-steep retrograde well (ssrw) fet device and its manufacture method | |
| US8936977B2 (en) | Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | |
| CN101699617B (en) | Preparation method of self-aligned tunneling field effect transistor | |
| US20040232499A1 (en) | Transistor in semiconductor devices and method of fabricating the same | |
| CN100365769C (en) | Semiconductor device and its manufacturing method | |
| CN104737298B (en) | Split gate power semiconductor field effect transistor | |
| JP2003338622A (en) | Method of manufacturing semiconductor element having extremely thin epichannel by decarborane dope | |
| CN101093854B (en) | Semiconductor device and method of manufacturing the same | |
| US20100155858A1 (en) | Asymmetric extension device | |
| KR20120035699A (en) | Semiconductor devices including source/drain regions with abrupt junction profiles and methods of fabricating the same | |
| CN102087980A (en) | High performance semiconductor device and method of forming the same | |
| CN102104006A (en) | Preparation method of field effect transistor | |
| CN101916776B (en) | SOIMOS (Silicon on Insulator Metal Oxide Semiconductor) device with BTS (Bodied Tied to Source) structure and manufacture method thereof | |
| CN109148578A (en) | Semiconductor structure and forming method thereof | |
| JPH01501189A (en) | Method of forming MOS integrated circuit | |
| JP2003188373A (en) | Semiconductor device and method of manufacturing the same | |
| CN111799175A (en) | Low-capacitance high-performance VDMOS device and preparation method thereof | |
| CN100421225C (en) | Method for improving hole mobility of PMOS field effect transistor | |
| CN101150071A (en) | Method of manufacturing semiconductor device | |
| WO2006134553A3 (en) | Semiconductor device having a polysilicon electrode | |
| CN102420189B (en) | Method for improving reliability of under-gate technology high-K gate dielectric medium CMOS (complementary metal oxide semiconductor) | |
| US20150349065A1 (en) | Transistor structure including epitaxial channel layers and raised source/drain regions | |
| TW200614387A (en) | Method of fabricating mos transistor by millisecond anneal | |
| CN105789203A (en) | Semiconductor device and manufacturing method therefor, and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201214 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100083 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220429 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080924 |