CN100419776C - Programmable security processor - Google Patents
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- CN100419776C CN100419776C CNB2006101443534A CN200610144353A CN100419776C CN 100419776 C CN100419776 C CN 100419776C CN B2006101443534 A CNB2006101443534 A CN B2006101443534A CN 200610144353 A CN200610144353 A CN 200610144353A CN 100419776 C CN100419776 C CN 100419776C
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Abstract
A programmable safety processor consists of program storage, control stack, control decoder, operation decoder, RAM controller, operation executor, operation stack and interface module. It is featured as supporting programmable structure, setting with some basic operation units and utilizing program control and said basic operation unit to realize multiple ciphering deciphering / algorithm.
Description
Technical field
The present invention relates to the microprocessor Design technical field in the integrated circuit (IC) design, relate in particular to a kind of programmable security processor.
Background technology
Current society enters the information age, and along with the development and the application of the network information technology, information security is concerning country and individual's destiny, and information security more and more causes country, society and individual attention.
Information security mainly is based upon on the various enciphering and deciphering algorithms, and the general operand of enciphering and deciphering algorithm is all very big.In built-in applied system widely, the computing power of general embedded microprocessor is limited, and carrying out an encryption and decryption computing needs for a long time, and this makes microprocessor be difficult to be competent in some need take into account the application of safety and real-time.
For example, in the wireless sensor network that rises is in recent years used, the wireless security protection network of commercial sub-district, application such as information supervision all needs the safety of guarantee information in the military affairs, and the latter more needs the real-time of guarantee information.
A kind of method of solution is to adopt specific safety chip, and domestic and international widely used crypto chip is at the specific cryptosystem algorithm and customized dedicated devices is very fast to specific cryptographic algorithm encryption/decryption speed mostly now.But the architecture of chip is fixed, and crypto-operation is finished by hardware.Therefore, big multi-password chip can only be finished a kind of cryptographic algorithm, and this is not enough in a lot of application scenarios.Said wireless sensor network is used for example, needs ad-hoc network, finishes work such as data acquisition.Duration of work need be applied to multiple different cryptographic algorithm, as authentication, and data encryption etc.So simple special purpose system chip is not enough.
Therefore, hope can have a kind of programmable crypto chip, and its feature is that a cover instruction set can be arranged, and based on this cover instruction set programming, can realize multiple enciphering and deciphering algorithm efficiently.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of programmable security processor, to satisfy requirement able to programme, realizes multiple enciphering and deciphering algorithm.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of programmable security processor, this safe processor comprises:
Program storage (PC) is used to store the encryption and decryption program, and selects an instruction according to the program counter value that is received from the control code translator, and the instruction that will select is divided into operational order and steering order, sends to operator delay respectively and controls code translator;
The control storehouse is used for finishing the preservation and the recovery of control code translator register and programmable counter;
The control code translator, be used to finish the decoding and the execution of the steering order that is received from program storage, the value of internal register is sent to operator delay and control storehouse, send the pop down control signal of popping, and send the branch predict instruction signal to the computing actuator to the control storehouse; This control code translator comprises:
Command decoder is used to finish the decoding and the execution of the steering order that is received from program storage, sends the pop down control signal of popping to the control storehouse, transmits control signal to accumulator register rega, regb and programmable counter;
Accumulator register rega, regb, regc are used for being pressed into or ejecting data according to the control signal that is received from command decoder to the control storehouse, and the data of preserving are sent to operator delay;
Programmable counter is used for being pressed into or the pop-up program Counter Value to the control storehouse according to the control signal that is received from command decoder, and to program storage written-out program Counter Value;
Base value register regmax, and base address register bs0, bs1, bs2 and bs3, described accumulator register rega, regb and regc, and base address register bs0, bs1, bs2 and bs3 are connected in operator delay, when decoding, operator delay utilizes described accumulator register rega, regb and regc, and the physical address of the value generating run number of base address register bs0, bs1, bs2 and bs3;
Operator delay, be used for the operational order that is received from program storage is deciphered, generate source operand address, destination operand address and arithmetic type according to decode results and the internal register value that is received from the control code translator, the source operand address and the destination operand address that generate are sent to the RAM controller, and the arithmetic type of generation sends to the computing actuator;
The RAM controller, be used for according to the operand address and the operation result that are received from operator delay, from RAM, read source operand, destination operand is write RAM, and according to the read-write control signal that is received from interface module, address signal with write the operation that data are carried out read-write RAM;
The computing actuator is used for the arithmetic type signal of the operand that is received from the RAM controller and operator delay is carried out the encryption and decryption computing, and execution result is turned back to the RAM controller; And return the branch prediction results signal to the control code translator according to operation result, and send the pop down control signal of popping to the computing storehouse, the computing storehouse is carried out the pop down control of popping;
The computing storehouse, the value that is used for preserving computing actuator register, the control of popping of the pop down of accepting the computing actuator;
Interface module is used to provide interactive interface, realizes safe processor and extraneous communicating by letter of carrying out.
Described operator delay comprises:
Instruction decoding unit is used for the operational order that is received from program storage is deciphered, and decode results is exported to scalar/vector and arithmetic type recognition unit;
Scalar/vector is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating source operand address and destination operand address, and source operand address and the destination operand address that generates sent to the RAM controller;
The arithmetic type recognition unit is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating arithmetic type, and the arithmetic type that generates is sent to the computing actuator.
The operand that described operator delay generates adopts the plot indexed addressing.
Described RAM controller comprises:
Selector switch is used for selecting address date to carry out the RAM operation from the address date that is received from operator delay, computing actuator and interface module;
Address mapping unit is used for the operand address that selector switch is selected is mapped to RAM;
RAM is used for writing or sense data according to the operand address of address mapping unit mapping, and the data of reading is sent to the computing actuator as operand.
Described RAM comprises 4 independently RAM, is respectively RAMA, and RAMB, RAMC and RAMD, each RAM support one to read one and write, and operand address is mapped among 4 RAM.
Described computing actuator comprises Advanced Encryption Standard (AES) forward/reverse byte transducer, Hash (HASH) compression function arithmetical unit, efficient multiply device, arithmetic logical unit (ALU) arithmetical unit and register;
Described HASH compression function arithmetical unit is used to finish 4 basic logic function F, G, H, the I of Message Digest 5 (MD5) compression function;
Described register comprises ALU carry/borrow zone bit, the two 8 figure places high byte save register that multiplies each other.
What described interface module realized comprises with communicating by letter of carrying out of the external world: the encryption and decryption data that carries out with the external world, with the input and output of the extraneous key that carries out or the encryption and decryption control of carrying out with the external world;
The signal of described interface modules handle comprises: clock signal, reset signal, input/output bus, encryption and decryption commencing signal, encryption and decryption end signal or input/output control signal.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, this programmable security processor provided by the invention, be one and can support programmable structure, by analyzing the fundamental operation of most of crypto-operation, these basic processing units are set then, just can realize multiple enciphering and deciphering algorithm by programmed control and fundamental operation then.Because it is able to programme that this programmable security processor is supported, and be easy to efficiently realize multiple cryptographic algorithm, so satisfied the quick demand that realizes multiple cryptographic algorithm of needs in Embedded Application.
2, utilize programmable security processor provided by the invention, because the algorithm of security fields mainly is the complex mathematical computing, this mathematical operation all is to control with the not high circulation of complexity to finish, and the distance of the judgement redirect of algorithm is not long, separating of operational order and steering order, too the steering logic of complexity just can be dealt with the cycling jump in the security algorithm, independent operational order, can be so that the timeslice of entire process device substantially all be used for the doing mathematics computing, thus the time and the instruction number of required execution reduced greatly.
3, programmable security processor provided by the invention, carry out by making up control assembly and arithmetic unit parallel decoding, special-purpose on the one hand control assembly can well be realized cycle control, on the other hand, steering order and operational order executed in parallel have been saved and have been controlled the required time, and the time all has been used in the computing.Improve algorithm like this, greatly and carried out efficient.
4, programmable security processor provided by the invention, support able to programme, can support multiple cryptographic algorithm like this, (RSA is a kind of encryption method as RSA, there is not fixing Chinese name, first letter that is the name of 3 cryptologists is pieced together, therefore there is not corresponding translator of Chinese), Advanced Encryption Standard (AES) etc., satisfy in the Embedded Application demand to multiple security algorithm encryption and decryption, wireless security protection network as the commercial sub-district of wireless sensor network (WSN) example application, information monitors in the military affairs, can use RSA Algorithm in authentication, uses aes algorithm in data encryption process.
Description of drawings
Fig. 1 is the structured flowchart of programmable security processor provided by the invention;
Fig. 2 is the structured flowchart of control code translator in the programmable security processor provided by the invention;
Fig. 3 is the structured flowchart of operator delay in the programmable security processor provided by the invention;
Fig. 4 is the structured flowchart of RAM controller in the programmable security processor provided by the invention;
Fig. 5 is the structured flowchart of computing actuator in the programmable security processor provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Processor architecture of the present invention is exactly one can support programmable structure, by analyzing the fundamental operation of most of crypto-operation, these basic processing units is set then, just can realize multiple enciphering and deciphering algorithm by programmed control and fundamental operation then.
Most of enciphering and deciphering algorithms, particularly block cipher as RSA, all relate to a large amount of circulations in the encryption and decryption computing of AES etc.
For example RSA Algorithm supposes that key is for { d, n} at first will be divided into some groups with encryption and decryption data, and each group is encrypted respectively, and this is a systemic circulation; Ask d the power mould n of integrated data M then, the most normal use algorithm be that key d is expressed as binary code, the most significant digit from binary code detects lowest order then, carries out the two numbers mould n that multiply each other by judging binary bit value, this is second layer circulation; At last, in two numbers multiplied each other the calculating of mould n, a kind of easy method was shown as binary code with one of them numerical table exactly, also is to detect lowest order by the most significant digit from binary code, carried out corresponding computing and realized multiplying each other and ask mould, and this is the 3rd layer of circulation.
Aes algorithm and for example, the ground floor circulation is the grouping circulation, and ten round transformations are carried out in each grouping then, and this is second layer circulation; At last, conversion each time all relates to each byte of grouping, if hardware is not directly realized the grouping map function, so, needs circulation that each byte is carried out conversion.
By as can be seen top, cycle control layer by layer is characteristics of enciphering and deciphering algorithm.In order to realize circulation, general instruction set is by comparison order, and jump instruction realizes.Like this, encryption and decryption need be carried out a lot of comparison orders, jump instruction, has reduced algorithm and has carried out efficient, and a lot of times that program is carried out all have been placed in the cycle control.And the present invention is provided with special control and computing parallel organization and proprietary cycle control unit according to these characteristics, can be good at realizing cycle control.
The safe processor structure that the present invention establishes, it supports able to programme, and is easy to efficiently realize multiple cryptographic algorithm, can satisfy the quick demand that realizes multiple cryptographic algorithm of needs in Embedded Application.
As shown in Figure 1, Fig. 1 is the structured flowchart of programmable security processor provided by the invention, and this programmable security processor comprises program storage 10, control storehouse 11, control code translator 12, operator delay 13, RAM controller 14, computing actuator 15, computing storehouse 16 and interface module 17.
Wherein, program storage (PC) 10 is used to store the encryption and decryption program, and according to the instruction of program counter value selection that is received from control code translator 12, and the instruction that will select is split as operational order and steering order two parts, send to operator delay and control code translator respectively, be about to operational order and send to operator delay, steering order is sent to the control code translator.
Control storehouse 11 is used for finishing the preservation and the recovery of control code translator 12 registers and programmable counter.
Programmable security processor provided by the invention is supported the very long instruction word structure, and an one characteristic are: a very long instruction word (VLIW) is made up of a steering order and an operational order, and steering order and operational order are separate.Steering order all is put into steering order such as cycle control etc. and partly finishes with the control program flow process that comes.Operational order is used for carrying out basic encryption and decryption computing, not responsible program circuit.And instruction word structure is corresponding to be the basic hardware device of processor, and basic device is made of control assembly and arithmetic unit, and they also are the independent operatings that walks abreast.
When obtain a very long instruction word (VLIW) from program storage after, the control assembly that the steering order of very long instruction word (VLIW) partly is assigned to is carried out, and operational order partly is assigned to arithmetic unit and carries out.Article two, executing instructions, control program flow process and the computing of execution encryption and decryption respectively.The benefit of doing like this is, because executed in parallel when steering order and operational order, therefore, cycle control is the occupying volume external instruction cycle not, and as mentioned before, characteristics of cryptographic algorithm are that cycle control is many, take a large amount of instruction cycles.Therefore adopt structure of the present invention, the tender execution efficient that improves cryptographic algorithm greatly.
Fig. 2 is the structured flowchart of control code translator in the programmable security processor provided by the invention.Described control code translator 12 comprises command decoder, accumulator register rega, regb, regc, and regmax, bs0, bs1, bs2, bs3 and programmable counter.Wherein, command decoder is used to finish the decoding and the execution of the steering order that is received from program storage, if stack operation instruction, then send the pop down control signal of popping to the control storehouse, and select some registers among accumulator register rega, regb, regc and regmax, bs0, bs1, bs2, the bs3, be pressed into or eject data according to the pop down control signal of popping to the control storehouse.In addition, register rega, regb, regc, bs0, bs1, bs2, bs3 are connected to operator delay 13, are used to realize address decoding.Accumulator register regc is not real register, but rega and regb and, mainly be addressing for convenience.
The included base value register regmax of control code translator 12 in the programmable security processor provided by the invention, and base address register bs0, bs1, bs2 and bs3 are used to make things convenient for addressing.In order to programme flexibly, addressing mode flexibly can be provided, the mode of employing is the plot indexed addressing, the form of 8 bit address sign indicating numbers is as shown in table 1.Described accumulator register rega, regb and regc, and base address register bs0, bs1, bs2 and bs3 are connected in operator delay, when decoding, operator delay utilizes described accumulator register rega, regb and regc, and the physical address of the value generating run number of base address register bs0, bs1, bs2 and bs3.
7 6 5 4 3 2 1 0
| Plot | Index | Side-play amount |
| 00:bs0 01:bs1 10:bs2 11:bs3 | 00:0 01:ixa 10:ixb 11:ixc | 0 15 |
Table 1
In the basic device, certain methods is adopted in the design of control assembly, realizes particularly cycle control of programmed control.The characteristics of the cycle control of cryptographic algorithm are that cycle index is very definite, can predict.And after in case cycle index determines, will carry out so repeatedly circulation, the centre can not stop suddenly, jumps out.RSA Algorithm for example, carry out two numbers multiply each other ask mould n in, suppose that two numbers are x and y.In RSA, n is the part of key, is a definite value, x, and y two numbers all are the z byte longs, z is by the decision of the size of n.If calculate the binary representation be based on y, will circulate z * 8 time of calculating process so, obviously, this value of z * 8 is also fixed, and is predictable.The determinacy of cycle index, predictability has been brought very big convenience to cycle control.Control assembly realizes that the round-robin concrete grammar is that radix register and accumulator register are set, and when initial, the radix register is put into definite cycle index value, and the value of accumulator register is set to 0.Then, every circulation primary makes accumulator register add one by steering order, and whether equates to judge by relatively add up storage and base value register whether circulation finishes simultaneously.
The benefit of doing like this is, on the one hand because executed in parallel when steering order and operational order, therefore, cycle control is the occupying volume external instruction cycle not; On the other hand, whether control assembly determining program easily finishes, control program flow process accurately, and cycle criterion can draw the result once clapping, and unlike microprocessor may need to do branch prediction like that or the operation dummy instruction is waited for comparative result, so also improved algorithm greatly and carried out efficient.Therefore, another characteristics of control assembly are that loop control instruction only moves an instruction cycle.
As shown in Figure 3, Fig. 3 is the structured flowchart of operator delay in the programmable security processor provided by the invention.Described operator delay 13 comprises instruction decoding unit, scalar/vector and arithmetic type recognition unit.Wherein, instruction decoding unit is used for the operational order that is received from program storage is deciphered, and decode results is exported to scalar/vector and arithmetic type recognition unit.Scalar/vector is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating source operand address and destination operand address, and source operand address and the destination operand address that generates sent to the RAM controller.The arithmetic type recognition unit is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating arithmetic type, and the arithmetic type that generates is sent to the computing actuator.The operand that described operator delay generates adopts the plot indexed addressing.
As shown in Figure 4, Fig. 4 is the structured flowchart of RAM controller in the programmable security processor provided by the invention.Described RAM controller 14 comprises selector switch, address mapping unit and RAM.Wherein, selector switch is used for selecting address date to carry out the RAM operation from the address date that is received from operator delay, computing actuator and interface module.Address mapping unit is used for the operand address that selector switch is selected is mapped to RAM.RAM is used for writing or sense data according to the operand address of address mapping unit mapping, and the data of reading are sent to the computing actuator as operand.
Concrete, RAM adopts the storage of 4 bodies, and each memory bank support one is read one and is write, like this, the demand of 4 read-write RAM when can guarantee main operational order.RAM comprises 4 independently RAM, is respectively RAMA, RAMB, and RAMC and RAMD, operand address is mapped among 4 RAM, will guarantee that here the physical address of any two source operands of an instruction can not be in same RAM.
As shown in Figure 5, Fig. 5 is the structured flowchart of computing actuator in the programmable security processor provided by the invention.Computing actuator 15 has disposed some basic crypto-operations, comprises AES forward/reverse byte transducer, HASH compression function arithmetical unit, efficient multiply device, ALU arithmetical unit and register etc.Wherein, HASH compression function arithmetical unit is used to finish 4 basic logic function F, G, H, the I of MD5 compression function.As required, can also add more basic processing unit, support more crypto-operation faster.Register in the computing actuator comprises ALU carry/borrow zone bit, the two 8 figure places high byte save register that multiplies each other.
The arithmetic type that computing actuator 15 obtains by decoding is selected corresponding arithmetic element, and as source operand, operation result is stored in RAM at last with the data of reading among the RAM.If the branch's jump instruction that has control code translator 12 to send here then detects the corresponding calculated result, provide whether the redirect signal is to control code translator 12.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a programmable security processor is characterized in that, this safe processor comprises:
Program storage is used to store the encryption and decryption program, and selects an instruction according to the program counter value that is received from the control code translator, and the instruction that will select is divided into operational order and steering order, sends to operator delay respectively and controls code translator;
The control storehouse is used for finishing the preservation and the recovery of control code translator register and programmable counter;
The control code translator, be used to finish the decoding and the execution of the steering order that is received from program storage, the value of internal register is sent to operator delay and control storehouse, send the pop down control signal of popping, and send the branch predict instruction signal to the computing actuator to the control storehouse; This control code translator comprises:
Command decoder is used to finish the decoding and the execution of the steering order that is received from program storage, sends the pop down control signal of popping to the control storehouse, transmits control signal to accumulator register rega, regb and programmable counter;
Accumulator register rega, regb, regc are used for being pressed into or ejecting data according to the control signal that is received from command decoder to the control storehouse, and the data of preserving are sent to operator delay;
Programmable counter is used for being pressed into or the pop-up program Counter Value to the control storehouse according to the control signal that is received from command decoder, and to program storage written-out program Counter Value;
Base value register regmax, and base address register bs0, bs1, bs2 and bs3, described accumulator register rega, regb and regc, and base address register bs0, bs1, bs2 and bs3 are connected in operator delay, when decoding, operator delay utilizes described accumulator register rega, regb and regc, and the physical address of the value generating run number of base address register bs0, bs1, bs2 and bs3;
Operator delay, be used for the operational order that is received from program storage is deciphered, generate source operand address, destination operand address and arithmetic type according to decode results and the internal register value that is received from the control code translator, the source operand address and the destination operand address that generate are sent to the RAM controller, and the arithmetic type of generation sends to the computing actuator;
The RAM controller, be used for according to the operand address and the operation result that are received from operator delay, from RAM, read source operand, destination operand is write RAM, and according to the read-write control signal that is received from interface module, address signal with write the operation that data are carried out read-write RAM;
The computing actuator is used for the arithmetic type signal of the operand that is received from the RAM controller and operator delay is carried out the encryption and decryption computing, and execution result is turned back to the RAM controller; And return the branch prediction results signal to the control code translator according to operation result, and send the pop down control signal of popping to the computing storehouse, the computing storehouse is carried out the pop down control of popping;
The computing storehouse, the value that is used for preserving computing actuator register, the control of popping of the pop down of accepting the computing actuator;
Interface module is used to provide interactive interface, realizes safe processor and extraneous communicating by letter of carrying out.
2. programmable security processor according to claim 1 is characterized in that, described operator delay comprises:
Instruction decoding unit is used for the operational order that is received from program storage is deciphered, and decode results is exported to scalar/vector and arithmetic type recognition unit;
Scalar/vector is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating source operand address and destination operand address, and source operand address and the destination operand address that generates sent to the RAM controller;
The arithmetic type recognition unit is used for according to the decode results that receives and is received from the internal register value of controlling code translator generating arithmetic type, and the arithmetic type that generates is sent to the computing actuator.
3. programmable security processor according to claim 2 is characterized in that, the operand that described operator delay generates adopts the plot indexed addressing.
4. programmable security processor according to claim 1 is characterized in that, described RAM controller comprises:
Selector switch is used for selecting address date to carry out the RAM operation from the address date that is received from operator delay, computing actuator and interface module;
Address mapping unit is used for the operand address that selector switch is selected is mapped to RAM;
RAM is used for writing or sense data according to the operand address of address mapping unit mapping, and the data of reading is sent to the computing actuator as operand.
5. programmable security processor according to claim 4 is characterized in that, described RAM comprises 4 independently RAM, is respectively RAMA, and RAMB, RAMC and RAMD, each RAM support one to read one and write, and operand address is mapped among 4 RAM.
6. programmable security processor according to claim 1, it is characterized in that described computing actuator comprises Advanced Encryption Standard AES forward/reverse byte transducer, Hash HASH compression function arithmetical unit, efficient multiply device, arithmetic logical unit ALU arithmetical unit and register;
Described HASH compression function arithmetical unit is used to finish 4 basic logic function F, G, H, the I of Message Digest 5 MD5 compression function;
Described register comprises ALU carry/borrow zone bit, the two 8 figure places high byte save register that multiplies each other.
7. programmable security processor according to claim 1 is characterized in that,
What described interface module realized comprises with communicating by letter of carrying out of the external world: the encryption and decryption data that carries out with the external world, with the input and output of the extraneous key that carries out or the encryption and decryption control of carrying out with the external world;
The signal of described interface modules handle comprises: clock signal, reset signal, input/output bus, encryption and decryption commencing signal, encryption and decryption end signal or input/output control signal.
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| US8370641B2 (en) * | 2008-05-24 | 2013-02-05 | Via Technologies, Inc. | Initialization of a microprocessor providing for execution of secure code |
| CN104461676B (en) * | 2014-10-27 | 2017-09-08 | 杭州中天微系统有限公司 | Binary system translates stack manipulation accelerated processing method and its processor |
| CN111124499B (en) * | 2019-11-22 | 2022-11-01 | 中国科学院计算技术研究所 | Processor compatible with multi-instruction system and operation method thereof |
| CN113055165A (en) * | 2021-03-11 | 2021-06-29 | 湖南国科微电子股份有限公司 | Asymmetric cryptographic algorithm device, method, equipment and storage medium |
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