CN100416701C

CN100416701C - SRAM interface compatible delayed reading/storing mode of DRAM

Info

Publication number: CN100416701C
Application number: CNB031429793A
Authority: CN
Inventors: 施正宗
Original assignee: Etron Technology Inc
Current assignee: Etron Technology Inc
Priority date: 2003-06-13
Filing date: 2003-06-13
Publication date: 2008-09-03
Anticipated expiration: 2023-06-13
Also published as: CN1567477A

Abstract

The present invention relates to a method for executing external initialization in an internal type to access dynamic memory array comprising a plurality of dynamic memory storing grids to be updated periodically. The method comprises: first, whether the dynamic memory array is started is determined; second, a waiting period of stand-by time for reading and writing is inserted, wherein the stand-by time for reading and writing is the sum of array accessing time and array precharging time; the process of waiting for updating can be performed during the stand-by time for reading and writing; the process of waiting writing access is performed during the stand-by time for reading and writing; at last, after the stand-by time for reading and writing, external access can be executed inside the dynamic memory array in the internal type.

Description

The delay that is compatible to the DRAM at SRAM interface is read/storage method and circuit

Technical field

The present invention is the Dynamic Random Access Memory (DARM) that is compatible to SRAM (SARM) interface for a kind of, refers to that especially a kind of inner formula carries out the Method and circuits of initialization of external access (initiatedaccess) dynamic memory volume array (comprise a plurality of dynamic memory bodies that need periodically update deposit lattice).

Background technology

Dynamically or Dynamic Random Access Memory (DRAM) device comprise that array deposits lattice, the typical case has comprised a single access electric crystal and a capacitor.Comparatively speaking, SRAM (SARM) comprises a multiple electric crystal lattice array, contain 4 or 6 electric crystals on the general typical case, so, Dynamic Random Access Memory (DRAM) has smaller volume, therefore also relatively cheap relatively the time on the price with the SRAM (SARM) of ad eundem, but, SRAM (SARM) has the advantage of low Mao electricity, because Dynamic Random Access Memory (DARM) lattice capacitor must often more be newly arrived and be kept their memory kenel.

From the viewpoint that reduces cost, should use Dynamic Random Access Memory (DARM), rather than SRAM (SARM).For example, we can be in the electronic system of portable and mobile phone be replaced by the SRAM (SARM) of low power consumption the Dynamic Random Access Memory (DARM) that can reduce chip or system bulk size and cost.For the ease of replacing SRAM (SARM) with Dynamic Random Access Memory (DARM), under the prerequisite that performance does not influence, Dynamic Random Access Memory (DARM) must overcome three problems.

1. inner upgrade operation must transparence to this external procedure of putting;

2. power consumption is essential reduces, and particularly reads/storage operation by the unnecessary inside of cancellation;

3. the external access operation of Dynamic Random Access Memory (DARM) must be compatible with the SRAM (SARM) of the access operation, particularly asynchronous type of a standard static random access memory (SARM).

Please consult Fig. 1 earlier, the time that a common Dynamic Random Access Memory (DRAM) is installed under the compatible state of a SRAM (SARM) is chosen (timing) figure, comprising two operation kenels.In the kenel bottom being illustrated in, bide one's time then initialization one external access operation in time if there is not outside or hiding renewal operation.And in the kenel on top, when starting the external access operation of a memory body position, then wait for a concealed renewal.Exception portion address bus (bus) 22 transition statuses of particularly consulting the below or not having a concealed renewal are to address AD2.When access required (ACCESS REQUEST), Dynamic Random Access Memory (DRAM) can interrupt this conversion process.Because in Dynamic Random Access Memory (DRAM), there be not concealed being updated in the wait, therefore, carry out (ACCESS EXECUTE) when occurring when the access of WL (AD2), asynchronous access requires the operation meeting to begin execution immediately.Noticeable, for Dynamic Random Access Memory (DRAM), this access needs minimum memory lattice store cycle time, and it is Dynamic Random Access Memory (DRAM) row (row) access time to add above-listed (row) precharge (pre-charging) time, or T _Ras+ t _RpIn addition, on non-concealed renewal example, no matter be to read or store, all be to carry out at once.

Then, see also the example of concealed renewal.When asynchronous access requires (ACCESSREQUEST) is conversion (transition) via address 10 when sending, and then one innerly upgrades operation and is armed state.Shown in the affirmation (assertion) of REFRESH WL 14, upgrade operation and carry out immediately.Therefore, under the affirmation of WL (AD2), the execution of external access (access execute) will postpone t _Ras+ t _RpAccess time.In the differential responses of Dynamic Random Access Memory (DARM), be easy to cause the problem of wherein indeterminate (undefiniteness) for the address order that is compatible to SRAM (SARM).In addition, for external device (ED), microprocessor for example also can't be predicted whether read in first circulation or second circulation effectively (valid) of data because of unpredictability.

Next, see also Fig. 2, it has disclosed another problem that use Dynamic Random Access Memory (DRAM) is used as SRAM (SARM) compatible substitute.The state of address deflection (skew) has taken place on this example.Particularly, address bus-bar (ADDRESS 34) at first converts address AD1 to.Then, after the very short time, ADDRESS 34 converts address AD3 again to.This state is referred to as the address deflection.In fact, access device just carries out transition and conversion between address AD0 and the last address AD3 before one.Yet, on the different time, may be owing to different length or the capacity coupled problems of circuit, indivedual address circuits are converted to new address state.In any case but Dynamic Random Access Memory (DRAM) sees that initial address is converted to AD1, and it is interpreted as the beginning of access.Notice that fair to write bar line (write enable barline) be the state that is reading.Therefore, Dynamic Random Access Memory (DRAM) is read as reading of AD1 with the requirement (FALSE REQUEST) of mistake and connects and reach (read access).As be shown in the illusory access (DUMMY ACCESS) of WL (AD1) 36, read and connect that to reach be to read in the circulation in first to carry out.When the final conversion of ADDRESS 34 betides address AD3, then produce one second access requirement (ACCESS REQUEST).As the access that is shown in WL (AD3) 40 carries out (access execute), and reading of AD3 is to read in the circulation in second to carry out.The example of ADDRESS SKEW has produced the virtual access of Dynamic Random Access Memory (DRAM), and this is just needing extra cycle length and cause unnecessary electric consumption.

Consult Fig. 3 again, it has disclosed the problem again that use Dynamic Random Access Memory (DRAM) is used as SRAM (SRAM) compatible substitute.Disclosed the example of virtual reading (DUMMY READ) among the figure.SRAM (SRAM) access specification (specification) can require an address setting-up time T before fair the writing of WE*line 54 on address circuit 50 _AsBut Dynamic Random Access Memory (DRAM) is transferred to AD0 with 50 transition of address circuit and then is read as to start to read to connect from AD0 and reaches.This access is to reach for the mistake that is implemented as WL (AD0) 58 in first circulation reads to connect.The affirmation of WE*line 54 is read as secondary requirement, and then writes among the address AD0.This writes access is to carry out in second circulation of WL (AD0) 58.So the performance of memory body worsens once again because of unnecessary comprising (inclusion), current drain and reading of mistake (false).

Many prior arts have disclosed the Method and circuits of the Dynamic Random Access Memory (DRAM) compatible with SRAM (SRAM).The United States Patent (USP) U.S.6 that Leung has, 028,804 has disclosed one produces compatible Dynamic Random Access Memory (DRAM) circuit of SRAM (SRAM).This circuit utilizes the access time to carry out the action that renewal replenishes.When the conflict of running between an external access and inner the renewal, external access is carried out then earlier to be upgraded, and therefore, external access does not postpone.The United States Patent (USP) U.S.5 of Alwais et al, 991,851 have disclosed a Dynamic Random Access Memory (DRAM) compatible with SRAM (SRAM) installs.Wherein, SRAM (SRAM) is intended for the fast cache reservoir (cache) of Dynamic Random Access Memory (DRAM) array.The United States Patent (USP) U.S.5 of Alwaisetal, 999,474 have disclosed a Dynamic Random Access Memory (DRAM) compatible with SRAM (SRAM) installs, and it uses the array of SRAM (SRAM) as a fast cache reservoir and a Dynamic Random Access Memory (DRAM).

Summary of the invention

Fundamental purpose of the present invention, promptly be to create a kind of access that can innerly carry out an outside startup dynamic memory volume array, comprise the effective of a plurality of Dram lattices and the Method and circuits that can make, wherein, dynamic memory body lattice needs periodic upgrade (periodic refreshing).

Secondary objective of the present invention promptly is to create a kind of Method and circuits of Dynamic Random Access Memory (DRAM) the array interface compatible with SRAM (SRAM) array.

A further object of the present invention, promptly being to create by removing the illusory cycle (dummy cycle) provides a kind of Method and circuits that reduces the power consumption of Dynamic Random Access Memory (DRAM) array compatible with SRAM (SRAM) interface.

Another purpose of the present invention promptly is to create a kind of Method and circuits that inner cryptomnesia body upgrades and do not need throughput compensation (throughput penalty) of handling.

Another object of the present invention promptly is to create and a kind ofly must handles the Method and circuits of address deflection (address skew) and virtual read cycle by more newly arriving in the stand-by period in read/write.

The invention described above purpose be postpone by a Dynamic Random Access Memory (DRAM) that is compatible to SRAM (SRAM) interface to read/feature of storage mode reaches, and is the statement supernumerary structure with advantage and purpose of the present invention in the dependent claims of other claim.

According to purpose of the present invention, a kind of inner formula is carried out initialization of external access dynamic memory volume array, and this array comprises the method that a plurality of dynamic memory bodies that need periodically update are deposited lattice, and this method comprises that (1) determine whether this dynamic memory volume array has started; (2) insert a read-write stand-by time the waiting period, wherein this read-write stand-by time is the summation for being listed as the access time and being listed as precharge time.And waiting to be updated is to carry out in the middle of reading and writing free time.Waiting access to be written must carry out in the middle of the read-write stand-by time.At last, after read-write free time, again with the execution of carrying out inner formula in the dynamic memory volume array that is accessed in of outside.

Moreover, according to purpose of the present invention, a kind of Dynamic Random Access Memory (DRAM) that is compatible to SRAM (SRAM) interface, especially refer to a kind of inner formula execution initialization of external access dynamic memory volume array, and comprising a plurality of dynamic memory bodies that need periodically update, this array deposits the circuit of lattice, this circuit comprises: a synchronization clock pulse generator, and it is to produce a synchronous clock pulse by an external access information; One trigger delay generator again, it produces one from synchronous clock pulse and postpones synchronizing pulse, and this delays synchronizing pulse is followed the tracks of synchronous clock pulse by the read-write stand-by time that comprises the summation that is listed as access time and precharge time; One read/write access control formula, it upgrades clock pulse from synchronous clock pulse, delay synchronizing pulse and and produces a renewal startup signal, wherein, when upgrading the clock pulse startup, upgrades the startup signal and is also started in the middle of reading and writing stand-by time; Control of one word group circuit and timer circuit, it produces word group circuit action signal and bit circuit action signal from postponing synchronizing pulse and upgrading the startup signal; An and row address multiplexer, it is in selecting to upgrade the external demand address and inner the renewal between the address that start signal, wherein, one waits to be updated the action is carried out in the middle of the read-write stand-by time, and the external access of dynamic memory volume array is carried out in inside after the read-write stand-by time.

As for detailed construction of the present invention, application principle, effect and effect, then the explanation of doing with reference to following adjoint can be understood completely.

Description of drawings

Fig. 1 is for connecting the common embodiment synoptic diagram that (interface) is compatible to Dynamic Random Access Memory (DRAM) array apparatus of SRAM (SRAM) signal, wherein figure marks in the middle of renewal and non-renewal, the speed of Dynamic Random Access Memory (DRAM) performance (performance);

Fig. 2 is common Dynamic Random Access Memory (DRAM) synoptic diagram that is compatible to SRAM (SRAM) signal for a use, wherein illustrates the address deflected condition;

Fig. 3 is for the synoptic diagram of a common Dynamic Random Access Memory of use (DRAM), wherein illustrates dummy read state;

Fig. 4 is a preferred embodiment of the present invention's Dynamic Random Access Memory (DRAM) method of being compatible to SRAM (SRAM);

Fig. 5 is the sequential performance of method of the present invention, wherein illustrates the read/write standby and postpones (idle delay);

Fig. 6 is sequential performance of the present invention, wherein illustrates (pending refresh) to be updated and the time state to be written of waiting;

Fig. 7 is sequential performance of the present invention, and wherein figure marks an address deflected condition;

Fig. 8 is sequential performance of the present invention, and wherein figure marks dummy read state;

Fig. 9 is the preferred embodiment for the present invention's Dynamic Random Access Memory (DRAM) method compatible with SRAM (SRAM);

Figure 10 to Figure 12 is the sequential performance for preferred embodiment circuit of the present invention.

Embodiment

Embodiments of the invention have disclosed a Method and circuits that forms the Dynamic Random Access Memory (DARM) compatible with SRAM (SRAM).Inner formula is carried out initialization of external access (initiated access) dynamic memory volume array, comprises a plurality of dynamic memory body lattices, and wherein, dynamic memory body lattice needs periodic the renewal.The following stated is preferred embodiment of the present invention only, is not to be used for limiting scope of the present invention.Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.

As shown in Figure 4, the preferred embodiment of the inventive method is that form with exemplary flow chart (exemplary flow chart) shows.Fig. 5 to Fig. 8 illustrates the preferred embodiment as sequential chart.Present embodiment is a method of carrying out initialization of external access (initiatedaccess) dynamic memory volume array for an inner formula, and wherein, this array comprises a plurality of dynamic memory body lattices, and dynamic memory body lattice needs periodic the renewal.As shown below, this method provides the Dynamic Random Access Memory (DRAM) compatible with SRAM (SRAM) interface of a power saving and the performance of measurable speed.Many key characters of the present invention will be described as follows.

Consult Fig. 4 again, a key character of the inventive method is for determining at first whether external access dynamic memory volume array starts in the 100-104 step.See also Fig. 5, for example, if during address bus ADDRESS 170 conversion, external access just begins to start.In the present embodiment, address bus is converted to address AD2.This action is and asynchronous the carrying out of Dynamic Random Access Memory (DRAM) device, because the system synchronization clock pulse between Dynamic Random Access Memory (DRAM) and the access device does not give synchronization.See also Fig. 4 again, a key character of the inventive method be for read-write stand-by time in 108 steps the waiting period will begin to start.The read-write stand-by time is Dynamic Random Access Memory (DRAM) row (row) access time to add above-listed (row) summation of precharge (pre-charging) time, or is expressed as T _Ras+ t _RpSee also Fig. 5 again, comprise T _Ras+ t _RpThe read-write stand-by time is that the conversion by address bus 170 starts.

See also Fig. 4 again, the further feature of the inventive method is waited the renewal for the treatment of in the middle of the read-write stand-by time of 120 and 124 steps.See also Fig. 6 now, illustrate the time that memory body upgrades in the sequential chart of the present invention and treat state.Address bus ADDRESS 180 transits to address AD2 and starts access action.As mentioned above, the read-write stand-by time is to start in 108 steps.In the present embodiment, wait the more first month of the lunar year of a memory body position treat in the middle of.Therefore, in the middle of the read-write stand-by time, the carrying out of renewal is as in shown in the REFRESH WL 188.After the read-write stand-by time, the AD2 access is then undertaken by WL (AD2) 184.

See also Fig. 4 again, also must in the middle of the read-write stand-by

time

112 and 116 steps, carry out from the access to be written of the time of previous external access.See also Fig. 6 again, illustrate previous writing and wait embodiment in the middle for the treatment of.In this embodiment, the outside is carried out before writing in the Dynamic Random Access Memory (DRAM) in address 190 transition and conversion to address AD2.But this action that writes is not done inner execution by Dynamic Random Access Memory (DRAM) yet.If should example be detected, then the preferred embodiment meeting of the inventive method uses the read-write stand-by time to carry out this previous write command, shown in WRITE WL 198.The present external access that is converted to the Dynamic Random Access Memory (DRAM) that AD2 190 started by address will be carried out by WL (AD2) 194 then, at this moment, in the middle of if previous write command is still waited and treated, then the execution of write command will have precedence over the renewal that as shown in Figure 4 a time is treated.

Please consult Fig. 4 again, when an address is inclined to when detecting in the step 128, then reading and writing stand-by time can start in step 132 once again.See also Fig. 7, it is the synoptic diagram for an address deflected condition of the inventive method.As the explanation analysis in common embodiment, when multiple conversion appears in address bus 200 promptly the address deflection can appear, and be converted to address AD1 in this embodiment earlier and arrive address AD3 again.And work as time t1 less than read-write stand-by time T _Ras+ t _RpThe time, secondary switch transition appears.The preferable implementation method of the present invention is a detecting address deflected condition, and restarts the read-write stand-by time.As being left in the basket in the first address AD1 shown in the WL (AD1) 204.The access of the second address AD3 is carried out (ACCESS EXECUTE) and is carried out after the read-write stand-by time shown in the WL (AD3) 208.

Please consult Fig. 4 again, when detecting in 136 steps as if dummy read state, then reading and writing stand-by time can severe startup once again in 140 steps.See also Fig. 8, it is to read reaction for preferred embodiment method of the present invention virtual.Write bar (WE*) signal because address setting-up time t when fair _AsWhen reading state, 220 transition and conversion of address are to new address AD0.Then, WE*224 is converted to write state again.Because address setting-up time t _AsLess than read-write free time T _Ras+ t _Rp, so this method can be detected and virtually reads and restart the read-write standby and wait for.After the read-write stand-by time as shown, write access and promptly begin to carry out.Preferred embodiment of the present invention is that the dummy read cycles of removing Dynamic Random Access Memory (DRAM) is avoided unnecessary electrical source consumption.Consulting Fig. 4 again, is after the read-write stand-by time of step 148 in

step

100 and 104 external access that started, and the dynamic memory volume array promptly carries out inside and carries out action.Please consult Fig. 5 again, carry out (ACCESS EXECUTE) by the access that conversion started of address 170 and after the read-write stand-by time, carried out by WL (AD2) 174.

See also Fig. 9, it is for the preferred embodiment of circuit of the present invention.This circuit at first comprises: (1) one synchronization clock pulse generator 300 (clock generator), and it is to produce a synchronous clock pulse SYNC CLOCK by an external access information EXT.CONTROL; (2) one trigger delay generators 304 again, it produces one from SYNC CLOCK and postpones synchronizing pulse DELAYED SYNC PULSE.Postpone synchronizing pulse and add above-listed (row) precharge (pre-charging) time or T by comprising row (row) access time _Ras+ t _Rp, the read-write stand-by time of summation is followed the tracks of (TRAIL) clock pulse synchronously; (3) one read/write access control procedures (ARBITER), it upgrades clock pulse from synchronous clock pulse, delay synchronizing pulse and and produces renewal startup (refresh enable) signal RFE.When upgrading timer initiation, upgrade startup signal RFE and in the middle of the read-write stand-by time, also started; The control of (4) one word group circuits (wordline control) and timer circuit 308, it produces word group circuit action (WL ACTIVE) signal and bit circuit action (BLACTIVE) signal from postponing synchronizing pulse and upgrading startup signal RFE.At last, a row address multiplexer 324 (multiplexer), it is in selecting to upgrade the external demand EXT.ROW ADDRESS row address and inner the renewal between the address that start signal.One waits to be updated the action is carried out in the middle of reading and writing free time.And the external access of dynamic memory volume array is carried out in inside behind read-write stand-by time RW IDLE.

See also Figure 10, it is the preferable clock pulse performance for clock pulse generator circuit 300.Responding on the external command, it comprises address 340 transition and conversion to AD1, synchronously clock pulse 344.See also Figure 11, it is to be the preferable timing performance of trigger delay generator 304 again.The input end 350 of representing synchronous clock pulse is to produce one to postpone to be the read-write standby pulse of free time on output terminal 354.Note that if 350 pulses of one second input end appear at less than T _Ras+ t _RpT ₂The time, the output terminal 354 that postpones synchronizing pulse is can not send pulse.This characteristic just helps to filter address deflection and the virtual situation that reads.See also Figure 12, it is the preferable timing performance for WL control and timer circuit 308.Representative postpones 360 pairs of WL ACTIVE 364 timing of input end and the previous order (dictate) of charging in carrying out as shown of BLPRECHARGE of synchronizing pulse.

Advantage of the present invention must be made following conclusion.Can reach a kind of by the present invention and can innerly carry out an outside access that starts the dynamic memory volume array, comprise the effective of a plurality of dynamic memory body lattices and the Method and circuits that can make, wherein, dynamic memory body lattice needs periodic the renewal.Method and circuits of the present invention can make the memory array interface of a Dynamic Random Access Memory (DRAM) and the memory array compatibility of a SRAM (SRAM).By removing the illusory cycle, Method and circuits of the present invention can reduce the power consumption of Dynamic Random Access Memory (DRAM) array compatible with SRAM (SRAM) interface.In addition, Method and circuits of the present invention can be handled inner cryptomnesia body renewal and not need the throughput compensation.Moreover Method and circuits of the present invention must be handled address deflection (address skew) and virtual read cycle by more newly arriving in the stand-by period in read/write.

As described in above-mentioned embodiment, can innerly carry out an outside access that starts the dynamic memory volume array, comprising a plurality of dynamic memory body lattices, and, dynamic memory body lattice needs periodic the renewal, the Method and circuits of this kind provided one with respect to common technique effectively and the Method and circuits that can make.

The above person is preferred embodiment of the present invention only, is not to be used for limiting scope of the present invention.Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.

Component Name and numbering are to as directed in graphic

SRAM ... SRAM

Dynamic Random Access Memory ... DRAM

A ... concealed renewal 10 ... address

14 ... upgrade word group circuit 18 ... word group circuit (AD2)

B ... non-concealed renewal 22 ... address

26 ... upgrade word group circuit 30 ... word group circuit (AD2)

C ... address deflection 34 ... address

40 ... word group circuit (AD3) D ... virtual reading

50 ... address 54 ... the fair bar of writing

58 ... word group circuit (AD0) 100 .... standby

104 .... external access starts

108 .... start read-write stand-by time (Tras+trp)

112 .... wait and treat before to write 116 ... execution writes

114 .... carry out and upgrade 120 ... wait to be updated

128 .... address deflection 132 .... restart the read-write stand-by time

136 .... virtually read 140 .... restart the read-write stand-by time

144 .... surpass read-write stand-by time 148 .... carry out the outside and read

152 ... standby 170 .... address

174 ... word group circuit (AD2) E ... wait to be updated

180 ... address 184 .... word group circuit (AD2)

188 ... upgrade word group circuit F ... wait to be written

190 ... address 194 .... word group circuit (AD2)

198 ... write word group circuit G ... the address deflection

200 ... address 204 .... word group circuit (AD1)

208 ... word group circuit (AD3) H ... virtual reading

220 ... address 224 .... the fair bar of writing

228 ... word group circuit (AD0) 300 .... clock pulse generator

304 ... again trigger-delay circuit 308 ... .WL control and timer

312 ... upgrade clock pulse generator 316 .... read/write is upgraded access control procedure

320 .... row address MUX 340 ... address

344 .... synchrotimer 350 ... input end

354 .... output terminal 360 ... input end

364 .... word group circuit (AD2) 368 ... the precharge of bit circuit

Claims

1. a Dynamic Random Access Memory time-delay that is compatible to the SRAM interface is read/storage method, and it is characterized in that: this method comprises:

Determine whether this dynamic memory volume array starts;

Wait for a read-write stand-by time, wherein this read-write stand-by time is to be row access time and the summation that is listed as precharge time, and to wait to be updated be to carry out in the middle of reading and writing stand-by time; And,

After the read-write stand-by time, inner formula is carried out this dynamic memory volume array of external access.

2. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 1 is read/storage method, it is characterized in that: other is included in the middle of the read-write stand-by time, inner formula is carried out previous outside writing, wherein, this previous outside writing is just to have started before this external access action.

3. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 1 is read/storage method, it is characterized in that: this method is and the standard method of outside formula access one an asynchronous static memory volume array, deposits lattice and this array has comprised a plurality of static memory bodies that do not need to periodically update.

4. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 1 is read/storage method, it is characterized in that: this method is that inner formula ground is synchronous each other with this external access, but not synchronous with an inner clock pulse.

5. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 1 is read/storage method, and it is characterized in that: other comprises:

The address deflection that detecting one comprises this external access, this access are during the step of waiting for a read-write stand-by time, are started by the transition and conversion of an address bus and address bus charged state; And, when detecting this address deflection, restart the step of waiting for the read-write stand-by time at every turn.

6. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 5 is read/storage method, it is characterized in that: other is included in the middle of the read-write stand-by time, inner formula is carried out previous outside writing, wherein, this previous outside writing is just to have started before this external access action.

7. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 1 is read/storage method, it is characterized in that: other comprises: detect virtual reading, it comprise by an address bus and one from reading state change to a write state fair write between the signal transition and conversion and during the step of waiting for the read-write stand-by time and the external access that starts; And when detecting this virtual reading, restart the step of waiting for the read-write stand-by time at every turn.

8. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 7 is read/the storage method method, it is characterized in that: other is included in and reads and writes in the middle of free time, inner formula is carried out previous outside writing, wherein, this previous outside writing is just to have started before this external access action.

9. a Dynamic Random Access Memory time-delay that is compatible to the SRAM interface is read/storage method, and it is characterized in that: this method comprises:

-determine whether this dynamic memory volume array starts;

Wait for a read-write stand-by time, wherein this read-write stand-by time is to be row access time and the summation that is listed as precharge time, and to wait to be updated be to carry out in the middle of reading and writing stand-by time; And comprise: the address deflection that detecting one comprises this external access, this access are during the step of waiting for a read-write stand-by time, are started by the transition and conversion of an address bus and address bus charged state; And when detecting this address deflection, restart the step of waiting for the read-write stand-by time at every turn;

Detect virtual reading, it comprises by an address bus and from reading state

Change to a write state fair write between the signal transition and conversion and during the step of waiting for the read-write stand-by time and the external access that starts;

When detecting this virtual reading, restart the step of waiting for the read-write stand-by time at every turn; And after the read-write stand-by time, inner formula is carried out this dynamic memory array of external access.

10. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 9 is read/storage method, it is characterized in that: other is included in the middle of the read-write stand-by time, inner formula is carried out previous outside writing, wherein, this previous outside writing is just to have started before this external access action.

11. the Dynamic Random Access Memory time-delay that is compatible to the SRAM interface as claimed in claim 9 is read/storage method, it is characterized in that: this method is and the standard method of outside formula access one an asynchronous static memory volume array, deposits lattice and this array has comprised a plurality of static memory bodies that do not need to periodically update.

12. as claimed in claim 9 as claim, it is characterized in that: this method is that inner formula ground is synchronous each other with this external access, but not synchronous with an inner clock pulse.

13. Dynamic Random Access Memory circuit that is compatible to the SRAM interface, read/storage method in order to realize that the above-mentioned Dynamic Random Access Memory that is compatible to the SRAM interface is delayed time, it is characterized in that: this circuit comprises:

One synchronization clock pulse generator, it is to produce a synchronous clock pulse by an external access signal;

One trigger delay generator again, it produces one from synchronous clock pulse and postpones synchronizing pulse, and this delays synchronizing pulse is followed the tracks of synchronous clock pulse by the read-write stand-by time that comprises the summation that is listed as access time and precharge time;

One read/write access control procedure, it upgrades clock pulse from synchronous clock pulse, delay synchronizing pulse and and produces a renewal startup signal, wherein, when upgrading the clock pulse startup, upgrades the startup signal and is also started in the middle of reading and writing stand-by time;

Control of one word group circuit and timer circuit, it produces word group circuit action signal and bit line action signal from postponing synchronizing pulse and upgrading the startup signal; And,

One row address multiplexer, it is in selecting to upgrade the external demand address and inner the renewal between the address that start signal, wherein, one waits to be updated the action is carried out in the middle of the read-write stand-by time, and the external access of dynamic memory volume array is carried out in inside after the read-write stand-by time.

14. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 13, it is characterized in that: if previous outside writing is just to have started before this external access action, it is to carry out in the middle of the read-write stand-by time that then inner formula is carried out previous outside writing.

15. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 13, it is characterized in that: this circuit is and the standard method of outside formula access one an asynchronous static memory volume array, deposits lattice and this array has comprised a plurality of static memories that do not need to periodically update.

16. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 13, it is characterized in that: detecting an address deflection that comprises this external access, this access is during the step of waiting for a read-write stand-by time, when starting, then restart this read-write stand-by time by the transition and conversion of an address bus and address bus charged state.

17. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 14, it is characterized in that: if should previous outside writing be just to have started before this external access action, it be to carry out in the middle of the read-write stand-by time that then inner formula is carried out previous outside writing.

18. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 13, it is characterized in that: detecting virtual reading, it comprise by an address bus and one from reading state change to a write state fair write between the signal transition and conversion and during the step of waiting for the read-write stand-by time and during the external access that starts, then restart this read-write stand-by time.

19. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 18, it is characterized in that: if should previous outside writing be just to have started before this external access action, it be to carry out in the middle of the read-write stand-by time that then inner formula is carried out previous outside writing.

20. the Dynamic Random Access Memory circuit that is compatible to the SRAM interface as claimed in claim 13, it is characterized in that: detecting an address deflection that comprises this external access, this access is during the step of waiting for a read-write stand-by time, when starting, then restart this read-write stand-by time by the transition and conversion of an address bus and address bus charged state; And detecting virtual reading, it comprise by an address bus and one from reading state change to a write state fair write between the signal transition and conversion and during the step of waiting for the read-write stand-by time and during the external access that starts, then restart this read-write stand-by time.