CN100416700C - AC timing parameter controlling circuit and method for semiconductor memory equipment - Google Patents
AC timing parameter controlling circuit and method for semiconductor memory equipment Download PDFInfo
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- CN100416700C CN100416700C CNB021542627A CN02154262A CN100416700C CN 100416700 C CN100416700 C CN 100416700C CN B021542627 A CNB021542627 A CN B021542627A CN 02154262 A CN02154262 A CN 02154262A CN 100416700 C CN100416700 C CN 100416700C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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Abstract
A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.
Description
Technical field
The present invention relates to a kind of semiconductor memory apparatus, relate in particular to a kind of circuit, this circuit is used for the AC timing parameters of semiconductor memory apparatus is controlled and controlled the operation of semiconductor memory apparatus by the variation of identification AC timing parameters.
Background technology
The operation timing of semiconductor memory apparatus (timing) (also claim AC regularly) parameter-definition specific running time or the time interval between the specific operation, stipulated the tolerance limit of operation timing for the operate as normal that guarantees semiconductor memory apparatus.
Usually, the special value of the AC timing parameters of semiconductor memory apparatus is defined as the cycle of a plurality of predetermined reference times or reference clock signal.The tolerance limit of the particular value of AC timing parameters is big more, can guarantee the performance of semiconductor memory apparatus more better.Yet, when the tolerance limit of the particular value of AC timing parameters increases, make circuit design become very difficult owing in tolerance limit, be difficult to obtain the identical operations characteristic.
In conventional semiconductor memory apparatus, when circuit design, select fuse or select metal by installing, or solve problem by using the AD HOC register setting.In the situation of selecting metal is installed, need the shielding of (separate) respectively, increased the cost of making shielding like this.In install selecting the situation of fuse, the space that fuse is installed must be arranged and chip size is increased.In addition, must comprise the fuse failure process respectively, and increase manufacturing cost and consuming time.
In using the situation of MRS, must comprise being used to use the circuit of MRS and increasing chip size.Do not need other processing procedure of branch, handle as fuse failure, even finished product also can be revised.
Yet, when using MRS, under the situation of the variation of AC timing parameters and its variation of needs reflection, must carry out the programming process of MRS respectively.Be difficult to make the operating characteristic of semiconductor memory apparatus to be consistent like this, and reduce the performance of semiconductor memory apparatus.
Summary of the invention
First purpose of the present invention is to provide by identification AC timing parameters to change the circuit of the timing parameters of semiconductor memory apparatus being controlled and controlled the operation of semiconductor memory apparatus.
Second purpose of the present invention provides by identification AC timing parameters and changes the method for operating of the timing parameters of semiconductor memory apparatus being controlled and controlled semiconductor memory apparatus.
The 3rd purpose of the present invention provides the circuit that is used to discern the cycle of semiconductor memory apparatus reference clock signal and controls the operation of semiconductor memory apparatus.
Therefore, for reaching the first above-mentioned purpose, provide a kind of circuit that is used to control the semiconductor memory apparatus timing parameters.Circuit comprises definitional part time delay, rating unit and control section.
Time delay, definitional part received continuous input signal, and produced first to n (n is a natural number) time delayed signal, and wherein input signal is delayed preset time.
Rating unit receiving inputted signal and first produces first to the n comparison pulse signal to the n time delayed signal, and each pulse signal has effective section corresponding to the duration.
Control section receiving inputted signal and first compares to the n comparison pulse signal input signal and first to the n comparison pulse signal, and produces first to the n operating control signal that is used to control the AC timing parameters of semiconductor memory apparatus.
At this input signal is semiconductor memory apparatus clock signal or order.
Preferably time delay, definitional part comprised the first time-delay equipment that is used for also producing with the scheduled delay delay input signal by receiving inputted signal first time delayed signal, with be used for by receiving first time delayed signal and produce the second time-delay equipment of second time delayed signal with scheduled delay first time delayed signal of delaying time, and be used for by receiving (n-1) time delayed signal and producing the n time-delay equipment of n time delayed signal with scheduled delay time-delay (n-1) time delayed signal.
Preferably rating unit comprises first to the n comparison means, and this installs respectively receiving inputted signal and corresponding first to the n time delayed signal, and produces first to the n comparison pulse signal, and each comparison pulse signal has effective section of predetermined lasting time.
Preferably control section comprises first to the n operation control section, this operation control section difference receiving inputted signal and corresponding first is to the n comparison pulse signal, effective section of input signal compared with the corresponding first effective time to the n comparison pulse signal, and produce first to the n operating control signal.
Circuit also preferably further comprises the operation determining section, and this operation determining section receiving inputted signal and operation allow signal, and determine whether operator input signal is transferred to definitional part time delay.
For reaching second purpose, be provided for variation by identification AC timing parameters, the semiconductor memory apparatus method of operating is controlled and controlled to the timing parameters of semiconductor memory apparatus, this method comprises: (a) receive continuous input signal, and produce first to n (n is a natural number) time delayed signal, wherein input signal is delayed time corresponding time delay, (b) receiving inputted signal and first is to the n time delayed signal, produce first to the n comparison pulse signal, each pulse signal has effective section of predetermined lasting time, (c) receiving inputted signal and first is to the n comparison pulse signal, input signal and first is compared to the n comparison pulse signal, produce the AC timing parameters be used to control semiconductor memory apparatus first to the n operating control signal.Here input signal is semiconductor memory apparatus clock signal or order.
Step (a) also preferably includes following steps: (a1) also produce first time delayed signal with the scheduled delay delay input signal by receiving inputted signal, (a2) by receiving first time delayed signal and delaying time that first time delayed signal produces second time delayed signal and (a3) by receiving (n-1) time delayed signal and producing the n time delayed signal with schedule time time-delay (n-1) time delayed signal with scheduled delay.
For reaching the 3rd purpose, provide a kind of circuit that is used to discern the reference clock signal cycle.Circuit comprises operation determining section, time delay definitional part, rating unit and control section.
The operation determining section receives continuous input signal and operation allows signal, and produces the operation that is used to control the control section operation and determine signal.
Time delay, the definitional part receiving inputted signal with corresponding scheduled delay delay input signal, produced first and second time delayed signals.
Rating unit receives first and second time delayed signals, produces first and second comparison pulse signals, and each pulse signal has effective section of predetermined lasting time.
Control section receives operation and determines signal, first and second comparison pulse signals, determines that to operating the signal and first and second comparison pulse signals compare, and generation first and second is used to control the operating control signal of semiconductor memory apparatus operation.
Time delay, definitional part preferably comprised the time-delay equipment that odd number is connected mutually and had scheduled delay.
Rating unit also preferably comprises first comparison means, this device receiving inputted signal and corresponding first time delayed signal, generation has effective section first comparison pulse signal of predetermined lasting time, with second comparison means, this device receiving inputted signal and corresponding second time delayed signal produce effective section second comparison pulse signal with predetermined lasting time.
Control section also preferably comprises the first operation control section, this part receives operation and determines signal and corresponding first comparison pulse signal, compare operating effective period duration determining the signal and first comparison pulse signal, and generation is used to control first operating control signal of semiconductor memory apparatus, with the second operation control section, this part receives operation and determines signal and corresponding second comparison pulse signal, determine that to operating signal and effective period duration of second comparison pulse signal compare, and generation is used to control second operating control signal of semiconductor memory apparatus.
Therefore be used to control the circuit of AC timing parameters of semiconductor memory apparatus and the variation that method can be discerned the AC timing parameters thereof according to the present invention, and the operation that can control semiconductor memory apparatus is suitable for the AC timing parameters.
Description of drawings
By the description of carrying out below in conjunction with the accompanying drawing that an example exemplarily is shown, above-mentioned and other purposes of the present invention and characteristics will become apparent, wherein:
Fig. 1 is the block scheme according to the semiconductor memory apparatus AC timing parameters control circuit of first embodiment of the invention;
Fig. 2 is the process flow diagram of expression according to the semiconductor memory apparatus AC timing parameters control method of first embodiment of the invention;
Fig. 3 is the circuit diagram of circuit that is used to discern the reference clock signal cycle according to first embodiment of the invention;
Fig. 4 is the expression sequential chart that is used to discern the circuit working in reference clock signal cycle shown in Figure 3;
Fig. 5 is the circuit diagram that is illustrated in the identification reference clock signal periodic circuit shown in Figure 3 of use in the circuit;
Fig. 6 is the working timing figure of expression circuit shown in Figure 5;
Fig. 7 is the circuit diagram that is used to detect the circuit of RAS time, and wherein this circuit uses AC timing parameters control circuit shown in Figure 1;
Fig. 8 is the block scheme of internal voltage generator, and wherein this generator has used the signal of controlling circuit working shown in Figure 7;
Fig. 9 is the sequential chart of internal voltage generator work shown in Figure 8;
Figure 10 is the circuit diagram that is used to detect the circuit of RC time, and wherein this circuit uses AC timing parameters control circuit shown in Figure 1;
Figure 11 represents to be used to produce the circuit that has with the control signal of the information of RC time correlation; And
Figure 12 is the working timing figure of expression Figure 10 and circuit shown in Figure 11.
Embodiment
At this accompanying drawing the present invention is stated with reference to the preferred embodiment of the present invention.All the reference number of system is indicated identical part in the accompanying drawing.
Fig. 1 is the block scheme according to the semiconductor memory apparatus AC timing parameters control circuit of first embodiment of the invention.With reference to Fig. 1, the AC timing parameters comprises definitional part 110 time delay, rating unit 130 and control section 150.
The continuous input signal INCK (by the optional operation determining section 160 among Fig. 1) of definitional part 110 receptions time delay, with corresponding scheduled delay delay input signal INCK, produce first to n (n is a natural number) time delayed signal DES 1, DES2 ..., DESn.
Input signal INCK is semiconductor memory apparatus clock signal or order.Specifically, time delay, definitional part 110 comprised the time-delay equipment of several series connection: the first time-delay equipment 111 is delayed time input signal INCK with scheduled delay; The second time-delay equipment 112 receives and with the scheduled delay first time delayed signal DES1 that delays time; " at last " or n time-delay equipment 113 receives and with scheduled delay time-delay (n-1) time delayed signal (not shown).
In the present embodiment, the first time-delay equipment 111, the second time-delay equipment 112 and n time-delay equipment 113 have different time delay.Yet according to the configuration of circuit, the first time-delay equipment 111, the second time-delay equipment 112 and n time-delay equipment 113 also can have identical time delay.
More specifically, rating unit 130 comprises first to n comparison means 131,132 and 133, each comparison means receiving inputted signal INCK and receive respectively corresponding first to n time delayed signal DES1, DES2 ..., DESn, and produce respectively first to n comparison pulse signal COMP1, COMP2 ..., COMPn, each comparison pulse signal has effective section of predetermined lasting time.First to n comparison pulse signal COMP1, COMP2 ..., COMPn has effective section of various durations.
More specifically, control section 150 comprises first to the n operation control section 151,152 and 153, each the operation control section receiving inputted signal INCK and receive respectively corresponding first to n comparison pulse signal COMP1, COMP2 ..., COMPn, to each input signal INCK and corresponding first to n comparison pulse signal COMP1, COMP2 ..., duration of effective period of COMPn compares, produce first to n operating control signal OPCON1, the OPCON2 that is used to control the AC timing parameters ..., OPCONn.
Here, according to correspondence first to n operating control signal OPCON1, OPCON2 ..., the logic level of OPCONn, first to n operating control signal OPCON1, OPCON2 ..., OPCONn represent effective section of each input signal INCK whether be longer than or be shorter than corresponding first to n comparison pulse signal COMP1, COMP2 ..., COMPn.
AC timing parameters control circuit 100 can further comprise operation determining section 160, and this operation determining section 160 receiving inputted signal INCK and operation allow signal OPES.Operation allows the state decision of signal OPES whether operator input signal OUTCK to be transferred to definitional part 110 time delay.When OPES asks, circuit 100 will be activated (enable) or be under an embargo like this.
Here operation allows signal OPES to be produced by mode register device (MRS), but except that MRS, OPES also can be produced by external command or internal signal.Operation determining section 160 can be the NAND door.
Hereinafter with reference to Fig. 1 set forth in detail is carried out in the work of AC timing parameters control circuit.
Time delay, definitional part 110 received predetermined continuous input signal INCK, and produce first to n time delayed signal DES1, DES2 ..., DESn, wherein with predetermined delay input signal INCK time delay.
Input signal INCK can be the order of clock signal or semiconductor memory apparatus.For example, if control circuit 100 recognizes the cycle of memory device reference clock signal, thus the specific operation of control semiconductor memory apparatus, reference clock signal can be used as input signal INCK.If 100 identification row address strobe (RAS) times (representing with tRAS usually) of control circuit, thereby the specific operation of control semiconductor memory apparatus, row effectively (RA) signal can be used as input signal INCK.Here the RAS time is to be permitted to line precharge (RP) required time when signal is allowed to from the RA signal.
Time delay, definitional part 110 comprised that first to the n time-delay equipment 111,112 and 113, the first time-delay equipment 111 are by receiving inputted signal INCK and produce the first time delayed signal DES1 with scheduled delay delay input signal INCK.The first time delayed signal DES1 is applied to first comparison means 131 and the second time-delay equipment 112 of rating unit 130 (after this describing).The second time-delay equipment 112 is by receiving the first time delayed signal DES1 and producing the second time delayed signal DES2 with the scheduled delay first time delayed signal DES1 that delays time.The second time delayed signal DES2 is applied to second comparison means 132 and the second time-delay equipment (not shown) of rating unit 130.Similarly, n time-delay equipment 113 is by receiving (n-1) (not shown) time delayed signal and producing n time delayed signal DESn with scheduled delay time-delay (n-1) time delayed signal.First to the n time-delay equipment 111,112 and 113 can be made of the logical device that is used for signal lag, as impact damper.In this embodiment, first to the n time-delay equipment 111,112 has different time delay with 113, but can have identical time delay during specific implementation.
Because the first time delayed signal DES1 is only produced by input signal INCK is delayed time by the first time-delay equipment, so be different from by the second time delayed signal DES2 of the first and second time-delay equipment 111,112 by input signal INCK time-delay is produced.That is, first in n time delayed signal DES1, DES2......, the DESn time-delay degree of each be different.
Here, according to corresponding first to n operating control signal OPCON1, OPCON2 ..., the logic level of OPCONn, first to n operating control signal OPCON1, OPCON2 ..., OPCONn represent effective section of each input signal INCK be longer than or be shorter than corresponding first to n comparison pulse signal COMP1, COMP2 ..., effective section of COMPn.That is, first to the n operation control section 151,152 and 153 with first to n comparison pulse signal COMP1, COMP2 ..., COMPn respectively with following one-period of input signal INCK begin compare.
Because known first to n time-delay equipment 111,112 and 113 the time delay, just can know first to n comparison pulse signal COMP1, COMP2 ..., the COMPn duration effectively period.Thereby according to corresponding first to n operating control signal OPCON1, OPCON2......, OPCONn output high level or output low level, effective section of can know each input signal INCK be longer than or be shorter than corresponding first to n comparison pulse signal COMP1, COMP2 ..., effective section of COMPn.
Like this by use first to n operating control signal OPCON1, OPCON2 ..., OPCONn, if the effective segment length who determines input signal INCK is in the required time of semiconductor memory apparatus scheduled operation, then semiconductor memory apparatus is carried out first operation, if effective section that determines input signal INCK is shorter than the required time of semiconductor memory apparatus scheduled operation, semiconductor memory apparatus is equipped with the circuit of carrying out second operation, thus the operation of control semiconductor memory apparatus.
At this, operation allows signal OPES to be produced by MRS.That is,, then produce operation and allow signal OPES to forbid control circuit 100 if satisfy predetermined situation by adjusting the MRS semiconductor memory apparatus.Except MRS, operation allows signal OPES also can be produced by external command or internal signal.
Fig. 2 is the process flow diagram of method that is used to control the AC timing parameters of semiconductor memory apparatus according to first embodiment of the invention.See figures.1.and.2 the method is described.
The method can be discerned the work of AC timing parameters and control semiconductor memory apparatus, in step 210, by with scheduled delay delay input signal INCK generation first to n (n is a natural number) time delayed signal DES1, DES2 ..., DESn.More particularly, in step 210, receive and with delay input signal INCK time delay that is scheduled to, thereby produce the first time delayed signal DES1.Produce the second time delayed signal DES2 and hereinafter with the comparison pulse signal COMP1 that describes with the first time delayed signal DES1.Receive and with the scheduled delay first time delayed signal DES1 that delays time, and produce the second time delayed signal DES2.Use this mode, receive and with (n-1) time delayed signal DESn-1 that delays time the time delay of being scheduled to, thereby produce n time delayed signal DESn.
At this, be used for the length difference of the scheduled delay of delay input signal INCK.Therefore, first to n time delayed signal DES1, DES2 ..., DESn has different time delay.Yet the method for the circuit that is used to form in method (200) operation according to the AC timing parameters that is used for controlling semiconductor memory apparatus, the time that is used for delay input signal is identical.
Input signal INCK can be semiconductor memory apparatus clock signal or order.For example, if be used to control the cycle of method (200) the identification semiconductor memory apparatus reference clock signal of AC timing parameters, thus the specific operation of control semiconductor memory apparatus, reference clock signal can be used as input signal INCK.If method (200) identification row address strobe (RAS) time (representing with tRAS usually), thereby the specific operation of control semiconductor memory apparatus, row effectively (RA) signal can be used as input signal INCK.Here, the RAS time is to be permitted to line precharge (RP) signal from the RA signal to be allowed to the required time.
In addition, operation allows signal OPES can determine whether to apply input signal.Thereby, when not needing to use the situation of the method (200) of controlling semiconductor memory apparatus AC timing parameters, produce operation and allow signal OPES, so that do not apply input signal to control circuit 100, and control circuit 100 is not operated.Operation allows signal OPES to be produced by MRS.That is,, then produce operation and allow signal OPES not work with the method (200) that is used in control AC timing parameters if satisfy predetermined situation by adjusting the MRS semiconductor memory apparatus.Except MRS, operation allows signal OPES also can be produced by external command or internal signal.
In step 220, receiving inputted signal INCK and first to n time delayed signal DES1, DES2 ..., DESn, produce each effectively section have the predetermined lasting time that has nothing in common with each other first to n comparison pulse signal COMP1, COMP2 ..., COMPn.More particularly, in step 220, receiving inputted signal and the corresponding first time delayed signal DES1, and be used to produce effective section the first comparison pulse signal COMP1 with predetermined lasting time.In a like fashion, produce second to n comparison pulse signal COMP2 ..., COMPn.To input signal with produced by delay input signal INCK first to n time delayed signal DES1, DES2 ..., DESn compares, produce have pulse waveform first to n comparison pulse signal COMP1, COMP2 ..., COMPn.In addition, first to n time delayed signal DES1, DES2 ..., the time-delay degree of DESn is different, thereby first to n comparison pulse signal COMP1, COMP2 ..., effective section of COMPn have the different duration.
In step 230, receiving inputted signal INCK and first to n comparison pulse signal COMP1, COMP2 ..., COMPn, to input signal INCK and first to n comparison pulse signal COMP1, COMP2 ..., COMPn compares, produce be used to control semiconductor memory apparatus AC timing parameters first to n operating control signal OPCON1, OPCON2 ..., OPCONn.More particularly, in step 230, receiving inputted signal INCK and the corresponding first comparison pulse signal COMP1, effective period duration to each input signal and the corresponding first comparison pulse signal COMP1 compares, and produces the first operating control signal OPCON1 that is used to control semiconductor memory apparatus AC timing parameters.Use same way as, generation second to n operating control signal OPCON2 ... OPCONn.
According to first to n operating control signal OPCON1, OPCON2 ..., the logic level of OPCONn, first to n operating control signal OPCON1, OPCON2 ..., OPCONn represent effective section of input signal INCK whether be longer than or be shorter than first to n comparison pulse signal COMP1, COMP2 ..., effective section of COMPn.Because known first to the n signal time delay DES1, DES2 ..., time delay of DESn, can know first to n comparison pulse signal COMP1, COMP2 ..., the length that allows of COMPn.Therefore, according to first to n operating control signal OPCON1, OPCON2 ..., OPCONn is output high level or output low level, just can determine input signal INCK effectively section whether be longer than or be shorter than first to n comparison pulse signal COMP1, COMP2 ..., effective section of COMPn.Promptly, by use first to n operating control signal OPCON1, OPCON2 ..., OPCONn, if the effective segment length who determines input signal INCK is in the scheduled operation required time of semiconductor memory apparatus, semiconductor memory apparatus is carried out first operation, if determine the effective section scheduled operation required time less than semiconductor memory apparatus of input signal INCK, semiconductor memory apparatus is carried out second operation.Can make semiconductor memory apparatus blocked operation under different input signal timing modes like this.
Fig. 3 is the circuit diagram that is used to discern the reference clock signal cycle according to first embodiment of the invention.With reference to Fig. 3, circuit 300 comprises operation determining section 310, time delay definitional part 320, rating unit 330 and control section 340.
Time delay, definitional part 320 receiving inputted signal INCK and produced first and second time delayed signal DES1 and the DES2 with scheduled delay delay input signal INCK.Time delay, definitional part 320 comprised that odd number connects mutually and have the time-delay equipment (illustrating 321,323,325,327 and 329) of scheduled delay.Specifically, time-delay equipment 321,323,325,327 has different time delay with 329 among this embodiment, but when specific implementation can be arranged identical time delay.
The output of the 3rd time-delay equipment 325 becomes the second time delayed signal DES2.The output of the 5th time-delay equipment 329 becomes the first time delayed signal DES1.
According to the logic level of the first or second operating control signal OPCON1 or OPCON2, the first and second operating control signal OPCON1 and OPCON2 represent to operate effective section effective section of whether being longer than or being shorter than the corresponding first or second comparison pulse signal COMP1 or COMP2 determining signal OPDS.
More specifically, the first operation control section 350 comprises: first phase inverter 351, and it receives operation and determines signal OPDS and make it anti-phase; First transmission gate 352, its operation response determine that the output of the signal OPDS and first phase inverter 351 is transferred to first latch units 353 with the first comparison pulse signal COMP1; First latch units 353, this latch units 353 comprise second phase inverter 354 that the output that is used to make first transmission gate 352 is anti-phase and are used to make the output of second phase inverter 354 anti-phase and output is applied to the 3rd phase inverter 355 of second phase inverter 354; Second transmission gate 356, its operation response is determined the output of the signal OPDS and first phase inverter 351, and the output of first latch units 353 is transferred to the 4th phase inverter 357; With the 4th phase inverter 357, it makes the output of second transmission gate 356 anti-phase, and produces the first operating control signal OPCON1.
The second operation control section 360 is operated control section 350 roughly the same with above-mentioned first, and difference is to receive the second comparison pulse signal COMP2 to determine signal OPDS with operation, produces the second operating control signal OPCON2.
Fig. 4 is a sequential chart of describing circuit 300 work.For circuit 300 work that are used in the identification reference clock signal cycle, at first operation allows signal OPES to apply high level.If n the time clock of input signal INCK is to start at high level, then respond input signal INCK and operation permission signal OPES, operation determines that signal OPDS is activated at high level.
Be applied to time delay definitional part 320 input signal INCK through all time-delay equipment 321,323,325,327 and 329, thereby produce the first time delayed signal DES1.The first time delayed signal DES1 at first is applied to first comparison means 331 of rating unit 330.Input signal INCK only produces the second time delayed signal DES2 through three time-delay equipment 321,323 and 325.The second time delayed signal DES2 is applied to the rating unit 330 and second comparison means 333.
First comparison means 331 receives the first time delayed signal DES1 and input signal INCK, produces the first comparison pulse signal COMP1.Second comparison means 333 receives the second time delayed signal DES2 and input signal INCK, produces the second comparison pulse signal COMP2.Time delay, the configuration of definitional part 320 and rating unit 330 was same autompulse generators.Therefore, the first and second comparison pulse signal COMP1COMP2 have same pulse waveform.If time delay definitional part 320 time-delay equipment 321,323,325,327 and be respectively " T " 329 time delay, then the first comparison pulse signal COMP1 has the time delay of 5T, the second comparison pulse signal COMP2 has the time delay of 3T.This point has clearly expression in Fig. 4.
When the n+1 clock pulse signal of input signal INCK was applied to operation determining section 301, operation determined that signal OPDS is transformed into low level.When operation determined that signal OPDS turns back to low level, 340 pairs of operations of control section determined that the signal OPDS and the first and second comparison pulse signal COMP1 and COMP2 compare, and produce first and second operating control signal OPCON1 and the OPCON2.The first and second operating control signal OPCON1 and OPCON2 have the operation of being relevant to and determine whether signal OPDS is longer than or is shorter than the information by the scheduled delay of definitional part 320 generations time delay.
Here, operation determines that signal OPDS is that rising edge at input signal INCK time clock n is activated, and is under an embargo at the rising edge of next input signal INCK time clock n+1, thereby has effective section of one-period length of input signal INCK.Therefore, the first and second operating control signal OPCON1 and OPCON2 have the information that the schedule time was longer than or was shorter than to the one-period that is relevant to input signal INCK whether.
Now the work of control section 340 is at length stated.Determine signal OPDS when operation and be applied to first phase inverter 351 of the first operation control section 350 with high level.First transmission gate 352 is opened, and the first comparison pulse signal COMP1 is applied to and is latched in first latch units 353.Its open with closing state be that the nmos pass transistor MN1 that controlled by reset signal RESET is prior to OPDS initialization first module 353.
When operation determined that signal OPDS returns low level and is applied to first phase inverter 351, first transmission gate 352 was closed, and second transmission gate 356 is opened.Then, export the first comparison pulse signal COMP1 from first latch units 353, and be generated as the first operating control signal OPCON1 through the 4th phase inverter 357.With reference to Fig. 4, when operation determined that signal OPDS is in low level, the first comparison pulse signal COMP1 was in low level state, thereby the first operating control signal OPCON1 that is produced also is in low level.That is, under operation determined that signal OPDS is than the short situation of the first comparison pulse signal COMP1, the first operating control signal OPCON1 of generation was in low level.
The operation of the second operation control section 360 is identical with the operation of the first operation control section 350, so its detailed description will be omitted.With reference to Fig. 4, when operation determined that signal OPDS is in low level, the second comparison pulse signal COMP2 was in high level state, thereby the second operating control signal OPCON2 that is produced also is in high level.That is, under operation determined that signal OPDS is than the long situation of the second comparison pulse signal COMP2, the second operating control signal OPCON2 of generation was in high level.
Therefore, according to the logic level of the first or second operating control signal OPCON1 or OPCON2, can know the schedule time is longer than or is shorter than to the cycle of input signal INCK whether, this result can be used for controlling the operation of semiconductor memory apparatus.
Fig. 5 is to use the circuit diagram of the circuit 500 of OPCON1 and the operation of OPCON2 opertaing device.Circuit 500 shown in Figure 5 comprises: be used to make the anti-phase phase inverter of clock signal clk 505; Transmission gate 511,517,521 and 527, opening and closed condition of they controlled in the output of its response phase inverter 505; Be used to form the phase inverter 513,515,523 and 525 of latch; Be used to make the anti-phase phase inverter 519 and 529 of output of transmission gate 517 and 527; NAND door 530 receives the output of the first and second operating control signal OPCON1 and OPCON2 and phase inverter 519, and the output of the first and second operating control signal OPCON1 and OPCON2 and phase inverter 519 is compared; Phase inverter 535 makes the output of NAND door 530 anti-phase, and produces the output as the first output signal OUT1; The output of 540 couples second operating control signal OPCON2 of NAND door and phase inverter 529 compares; Make the output of NAND door 540 anti-phase with phase inverter 545, and produce output as the second output signal OUT2.
Fig. 6 is the working timing figure of expression circuit shown in Figure 5.Specifically, Fig. 6 A is illustrated in the first and second operating control signal OPCON1 and OPCON2 is under the low level situation, does not produce the input control signal INS as the first output signal OUT1 or the second output signal OUT2.
Fig. 6 B represents that the first and second operating control signal OPCON1 and OPCON2 are in the situation of high level, produces the input control signal INS as the first output signal OUT1.
Fig. 6 C represents that the first operating control signal OPCON1 is in low level and the second operating control signal OPCON2 is in the situation of high level, produces the input control signal INS as the second output signal OUT2.
Hereinafter with reference to Fig. 5 and Fig. 6 the work of circuit 500 is stated.
The circuit 500 response clock signal CLK of Fig. 5 carry out work.Here, clock signal clk can be internal clock signal or reference clock signal.
The input control signal INS that is applied to transmission gate 511 is the scheduled operation in order to the control semiconductor memory apparatus that produces in semiconductor memory apparatus.
Logic level according to the first and second operating control signal OPCON1 and OPCON2, just whether be longer than or be shorter than scheduled delay according to the input signal INCK cycle, the circuit 500 of Fig. 5 is controlled the scheduled operation of semiconductor memory apparatus by the input control signal INS that produces as the first output signal OUT1 or the second output signal OUT2.In other words, the scheduled operation of semiconductor memory apparatus can be controlled according to the length of reference clock signal one-period.
When clock signal clk was in high level and is applied to phase inverter 505, transmission gate 511 was opened, and input control signal INS is applied to the latch 516 that is made of phase inverter 513 and 515.Here, nmos pass transistor MN1 receives reset signal RESET and initialization latch 516.When clock signal clk was in low level and is applied to phase inverter 505, transmission gate 517 was opened, and the input control signal INS that is latched like this is applied to NAND door 530 through phase inverter 519.In the case, according to the logic level of the first and second operating control signal OPCON1 and OPCON2, determine whether that the input control signal INS that will be applied to NAND door 530 exports as the first output signal OUT1.
If any is in low level among the first and second operating control signal OPCON1 and the OPCON2, can not export input control signal INS.All be in the situation of high level at the first and second operating control signal OPCON1 and OPCON2, produce input control signal INS as the first output signal OUT1.This point has clearly expression in Fig. 6 B.
In this situation,, determine whether that the input control signal INS that will be applied to NAND door 540 exports as the second output signal OUT2 according to the logic level of the second operating control signal OPCON2.
Be in low level and the second operating control signal OPCON2 is under the situation of high level at the first operating control signal OPCON1, produce input control signal INS as the second output signal OUT2.This point has clearly expression in Fig. 6 C.In another situation, can not produce input control signal INS as the second output signal OUT2.
That is, all be under the low level situation, can not outwards export input control signal INS at the first and second operating control signal OPCON1 and OPCON2.Be in low level and the second operating control signal OPCON2 is in the situation of high level at the first operating control signal OPCON1, outside output input control signal INS after two clock signal clk period expires.All be in the situation of high level at the first and second operating control signal OPCON1 and OPCON2, only outside output input control signal INS after a clock signal clk period expires.
About the circuit 300 that is used to discern the reference clock signal cycle shown in Figure 3, one-period at input signal INCK is shorter than under the situation of the first pulse comparison signal COMP1, generation is in the low level first operating control signal OPCON1, be longer than at the one-period of input signal INCK under the situation of the second comparison pulse signal COMP2, produce the second operating control signal OPCON2 that is in high level.Like this, if input signal, promptly a reference clock signal cycle was longer than for first schedule time (the permission time of the second comparison pulse signal COMP2), be shorter than second schedule time (the permission time of the first comparison pulse signal COMP1), then after two clock signal clk period expires, outwards export input control signal INS.
In Fig. 5 circuit 500, implement the situation of this process, when the one-period of reference clock signal was shorter than for first schedule time, outwards do not export input control signal INS, when the one-period of reference clock signal was longer than for second schedule time, only after a clock signal clk period expires, outwards export input control signal INS, when the one-period of reference clock signal is between first schedule time and second schedule time, after two clock signal clk period expires, outwards export input control signal INS.
Fig. 7 has been to use the circuit of the AC timing parameters of control semiconductor memory apparatus shown in Figure 1, is used to detect the circuit diagram of the circuit of RAS time.
With reference to Fig. 7, the circuit that is used to detect the RAS time is used to discern the circuit 300 in reference clock signal cycle and has similar configuration to shown in Figure 3.That is, circuit 700 comprises: the definitional part 710 time delay that receives line activating order RA; Rating unit 720, the output of this part receive delay timing definition part 710 and line activating order RA, and above-mentioned two signals are compared produce comparison signal COMP; With control section 730, this part compares line activating order RA and comparison signal COMP, produces operating control signal TRAS.
Time delay, definitional part 710 comprised time-delay equipment 711,712 and 713.Rating unit 720 is made of the NAND door, and control section 730 has and shown in Figure 3 first or second control section 350 or 360 similar configurations.
In view of the operation of circuit 700, RAS time representation is expert at and is allowed to the required time to precharge command after activation command RA is allowed to.Precharge command is allowed to if line activating order RA is allowed to the back, and line activating order RA is under an embargo, and the RAS time is exactly to be permitted to it from the line activating order to be under an embargo once more the required time like this.
The circuit 700 that is used to detect the RAS time shown in Figure 7 has the operation similar to the circuit that is used to discern the reference clock signal cycle shown in Figure 3 300.That is, if line activating order RA is applied to definitional part 710 time delay, definitional part 710 usefulness scheduled delays time-delay time delay line activating order RA, and it is applied to rating unit 720.The output and the line activating order RA of rating unit definitional part 720 pairs of time delay 710 compare, and produce to have the predetermined effectively comparison pulse signal COMP of section.Control section 730 receives comparison pulse signal COMP and line activating order RA, and when the line activating order changed low level into, relatively whether line activating order RA was longer than or is shorter than comparison pulse signal COMP, thereby produced operating control signal TRAS.Thereby operating control signal TRAS has the information whether line activating order RA was longer than or was shorter than comparison pulse signal COMP that is relevant to.
As mentioned above, RAS time representation line activating order RA forbids the required time from allowing to.In the embodiment of Fig. 7, suppose that the RAS time discerns line activating order RA in each RC time and whether be longer than or be shorter than comparison pulse signal COMP.Here RC time representation is permitted to and is under an embargo from line activating order RA and then is allowed to once more the required time of this process.Like this, be used to discern the circuit 300 in reference clock signal cycle shown in the image pattern 3, do not need to comprise to be used to produce the independent circuit of the definite signal OPDS of operation so that select to be used for discerning the time in reference clock signal cycle.
Fig. 8 is the block scheme of internal voltage generator, and this generator has used the signal of controlling circuit working shown in Figure 7.Conventional internal voltage generator 800 comprises: voltage generator 810, and it receives external voltage EV and produces builtin voltage IV; Pulse producer 820, its responsive trip activation command (RA) produces pulse signal; With voltage generator 830, the output OVDRV_N of its response external voltage EV and pulse producer 820 produces predetermined voltage.The internal voltage generator 800 of Fig. 8 comprises pulse producer 840 in addition, the operating control signal TRAS that the circuit 700 of these pulse producer 840 response diagrams 7 produces and produce pulse signal, with voltage generator 850, the output of these voltage generator 850 response impulse generators 840 and external voltage EV and produce predetermined voltage.
Fig. 9 represents the working condition of internal voltage generator shown in Figure 8.
The electric energy that storage array consumes when line activating order in the semiconductor memory apparatus allows increases, and causes the level of builtin voltage IV obviously to reduce like this.This voltage descended shown in the time period that Fig. 9 is represented by VDIP.Therefore, most semiconductor memory apparatus include the circuit that compensation builtin voltage IV level descends.
As the example of compensating circuit, when line activating order RA was allowed to, circuit produced short pulse signal OVDRV_N, responded short pulse signal OVDRV_N then and produced additional electrical energy, thereby increase the driving force of voltage generator 810 immediately.Yet, use the method, owing to can't infinitely increase as the driving force of toning problem voltage generators 810 such as (overshoot).
It is to produce predetermined voltage then by responsive trip activation command RA generation pulse signal to compensate that some voltage descends.It is to recompense by the normal operations of voltage generator 810 in the RAS time period that voltage continues to descend.If RAS time abundance compensates by using pulse producer 820 and voltage generator 830 by line activating order RA operation, can work effectively.If but the RAS time decreased, voltage generator 810 can not be worked effectively, is difficult to the decline of compensation builtin voltage IV like this.
For addressing this problem, in internal voltage generator 800, increased pulse signal generator 840 and voltage generator 850, the operating control signal TRAS of this generator 840 and 700 outputs of 850 response circuits operates.In other words, if the RAS time is less than preset time, just produce operating control signal TRAS with predetermined logic level, pulse producer 840 responses have the operating control signal TRAS of predetermined logic level and produce pulse signal OVDRV_S, rely on the voltage generator 850 of received pulse signal OVDRV_S that the driving force of voltage generator 810 is increased.
When RAS is chronic (for example, when operating control signal TRAS is in this situation of low level), internal voltage generator 800 responsive trip activation command RA shown in Figure 8 produce short pulse signal OVDRV_N, and the voltage that relies on voltage generator 830 to produce strengthens the driving force of voltage generator 810.When RAS time (for example, when operating control signal TRAS is in this situation of high level) very in short-term, produce short pulse signal OVDRV_S by the operating control signal TRAS that receives from circuit 700 with high level.Voltage generator 850 response OVDRV_S further strengthen the driving force of voltage generator 810.As shown in Figure 9, according to pulse producer 820 responsive trip activation command RA and produce pulse signal OVDRV_N and produce pulse signal OVDRV_S when the pulse producer 840 operation response control signal TRAS whether.Among Fig. 9, the level of builtin voltage IV improves when pulse signal produces.
Figure 10 is the circuit diagram that is used to detect the circuit of RC time, and this circuit uses the circuit that is used for the control of AC timing parameters shown in Figure 1.
Figure 11 represents to be used to produce the circuit that has with the control signal of the relevant information of RC time.
Figure 12 is the working timing figure of expression Figure 10 and circuit shown in Figure 11.
The circuit 900 that is used to detect the RC time shown in Figure 10 is used to discern circuit 300 differences in reference clock signal cycle and is with shown in Figure 3: T-flip flop 910 is created in the rising edge of each line activating order and is determined signal OPDS by anti-phase operation; A rating unit of two rating units substitutes the NAND door with the NOR door.
Now the circuit 900 that is used to detect the RC time is described with reference to Figure 10,11 and 12.
RC time tRC represents that being allowed to the back from line activating order RA then is allowed to the required time of this process once more to being under an embargo.
The circuit 900 that is used to detect the RC time shown in Figure 10 comprise two time delay definitional part 920 and 950, two rating units 930 and 960 and two control sections 940 and 970 so that detect RC time tRC at the rising edge of each line activating order RA.
For detecting RC time tRC at the rising edge of each line activating order RA, T-flip flop 910 produces operation and determines signal OPDS, wherein its at the rising edge of each line activating order RA by anti-phase.
Determine that in operation the rising edge of signal OPDS, operation determine that signal OPDS is applied to definitional part 920 time delay, produces the first comparison pulse signal COMP1 to have predetermined effective width at rating unit 930.The control section 940 generations first operating control signal OPCON1, this OPCON1 compare with the definite signal OPDS of operation the first comparison pulse signal COMP1 by the next negative edge of determining signal OPDS in operation and are latched.With reference to Figure 12, operation determines that signal OPDS is shorter than the first comparison pulse signal COMP1, in this case, produces the first operating control signal OPCON1 that is in high level.
Determine that in operation the negative edge of signal OPDS, operation determine that signal OPDS is applied to definitional part 950 time delay, produce at rating unit 960 to have the effective section predetermined second comparison pulse signal COMP2.Be used as second operating control signal OPCON2 generation by the signal that is latched operating the next rising edge of determining signal OPDS that the second comparison pulse signal COMP2 and the definite signal OPDS of operation are compared at control section 940.With reference to Figure 12, determine that in operation the rising edge second comparison pulse signal COMP2 of signal OPDS is in low level, in this case, generation is in the low level second operating control signal OPCON2.
Similarly, the rising edge that swashs order RA at each row detects RC time tRC,, is operating each rising edge and the negative edge of determining signal OPDS that is, and shown in Figure 10 being used to detects the circuit 900 of RC time can discern continuous RC time tRC.
At each rising edge and the negative edge of the definite signal OPDS of operation, circuit 980 shown in Figure 11 is alternately exported the first operating control signal OPCON1 and the second operating control signal OPCON2.That is, at the negative edge of the definite signal OPDS of operation, output is as the first operating control signal OPCON1 of control signal TRC_S, and at the rising edge of operating definite signal OPDS, output is as the second operating control signal OPCON2 of control signal TRC_S.
Have the rapid information of RC time tRC previous step that is relevant at the rising edge of each line activating order RA by the operation generation, that is, whether be longer than or be shorter than the control signal TRC-S of the information of the schedule time of presetting about RC time tRC.
Control signal TRC-S can use the built-in function that is used to control semiconductor memory apparatus in application circuit
As mentioned above, according to control circuit and the method for operating thereof that is used to control the AC timing parameters of semiconductor memory apparatus of the present invention, can discern the variation of the AC timing parameters of semiconductor memory apparatus, the operation that can control semiconductor memory apparatus makes it be suitable for the AC timing parameters.
Although represented with reference to definite preferred embodiment of the present invention and described the present invention, but the one of ordinary skilled in the art will be appreciated that and can be under the prerequisite that does not deviate from the aim of the present invention that is defined by the following claims and scope the present invention be carried out modification on various forms and the details.
Claims (45)
1. variation that is used for by identification AC timing parameters, to the circuit that the operation of the timing parameters of semiconductor memory apparatus and semiconductor memory apparatus is controlled, this circuit comprises:
Time delay definitional part, receiving inputted signal produces first to the n time delayed signal, each time delayed signal is compared with input signal has corresponding skew time delay, wherein n is a natural number;
Rating unit, receiving inputted signal and first produce first to the n comparison pulse signal to the n time delayed signal, and each pulse signal has effective section of corresponding duration; And
Control section, receiving inputted signal and first compare to the n comparison pulse signal input signal and first to the n comparison pulse signal, and produce first to the n operating control signal that is used to control the AC timing parameters of semiconductor memory apparatus.
2. circuit as claimed in claim 1, wherein, input signal is semiconductor memory apparatus clock signal or continuous order.
3. circuit as claimed in claim 1, wherein, time delay, definitional part comprised:
The first time-delay equipment produces first time delayed signal by receiving inputted signal, and with first time delay delay input signal;
The second time-delay equipment produces second time delayed signal by receiving first time delayed signal, and with first time delayed signal of delaying time for second time delay; And
The n equipment of delaying time produces the n time delayed signal by receiving (n-1) time delayed signal, and with scheduled delay time-delay (n-1) time delayed signal.
4. circuit as claimed in claim 3, wherein, each in the described first time-delay equipment, second delay apparatus, the n time-delay equipment has different time delay.
5. circuit as claimed in claim 1, wherein, rating unit comprises first to the n comparison means, a corresponding time delayed signal in each device receiving inputted signal and first to n, and produce corresponding comparison pulse signal in first to n.
6. circuit as claimed in claim 5, wherein, first has the effective period different duration to the n comparison pulse signal.
7. circuit as claimed in claim 1, wherein, control section comprises first to the n operation control section, a corresponding comparison pulse signal in each operation control section receiving inputted signal and first to n, effective section to corresponding comparison pulse signal in effective section and first to n of input signal compares, and produces a corresponding operating control signal in first operating control signal.
8. circuit as claimed in claim 1, wherein, first represents by its logic level separately whether effective section of input signal be longer than or be shorter than first to effective section of n comparison pulse signal to the n operating control signal.
9. circuit as claimed in claim 1 also comprises the operation determining section, and its receiving inputted signal and operation allow signal, and determines whether control circuit allowed and the input signal of the operation forbidden is transferred to definitional part time delay.
10. circuit as claimed in claim 9, wherein, operation allows signal to be produced by mode register device MRS.
11. circuit as claimed in claim 9, wherein, the operation determining section is to have input signal and operate to allow the NAND door of signal as its input signal.
12. a variation that is used for by identification AC timing parameters, to the method that the operation of the timing parameters of semiconductor memory apparatus and semiconductor memory apparatus is controlled, this method comprises:
(a) receiving inputted signal produces first to the n time delayed signal, and each time delayed signal is compared with input signal has corresponding skew time delay, and wherein n is a natural number;
(b) use input signal and first to produce first to the n comparison pulse signal to the n time delayed signal, each pulse signal has and a corresponding effectively section lasting time delay; And
(c) input signal and first is compared to the n comparison pulse signal, produce the AC timing parameters be used to control semiconductor memory apparatus first to the n operating control signal.
13. method as claimed in claim 12, wherein, input signal is semiconductor memory apparatus clock signal or continuous order.
14. method as claimed in claim 12, wherein, input signal is that operation response allows signal and imports.
15. the described method of claim 14, wherein, operation allows signal to be produced by mode register device MRS.
16. method as claimed in claim 12, wherein, the n minimum is 3, and step (a) comprising:
(a1) by with first time delay delay input signal produce first time delayed signal;
(a2) by producing second time delayed signal with first time delayed signal of delaying time for second time delay; And
(a3) produce the n time delayed signal by (n-1) time delayed signal of delaying time time delay with n.
17. method as claimed in claim 16, wherein, first has different time delay to the n time delayed signal.
18. method as claimed in claim 12, wherein, first has effective period different duration to the n comparison pulse signal.
19. method as claimed in claim 12, wherein, first is to represent by its logic level separately whether to input signal effective section is longer than or is shorter than first to effective section of n comparison pulse signal to the n operating control signal.
20. a variation that is used for by identification AC timing parameters, the circuit of identification reference clock signal cycle and the operation of control semiconductor memory apparatus, this circuit comprises:
The operation determining section, receiving inputted signal and operation allow signal, produce operation and determine signal;
Time delay definitional part, receiving inputted signal, and produce first and second time delayed signals, wherein said first and second time delayed signals have been delayed time corresponding time delay from input signal;
Rating unit receives first and second time delayed signals, produces first and second comparison pulse signals, and each comparison pulse signal has effective section of the duration corresponding with the time delay of corresponding time delayed signal; And
Control section, receive operation and determine signal, first and second comparison pulse signals, determine that to operating the signal and first and second comparison pulse signals compare, and, produce first and second operating control signals that are used to control the semiconductor memory apparatus operation according to operating the comparative result of determining signal and comparison pulse signal.
21. circuit as claimed in claim 20, wherein, input signal is a reference clock signal.
22. circuit as claimed in claim 20, wherein, the operation determining section is a trigger, and it receives operation at its input end and allows signal, at the clock signal input terminal receiving inputted signal, determines signal in the output terminal output function.
23. circuit as claimed in claim 20, wherein, time delay, definitional part comprised the time-delay equipment that odd number is connected mutually and had the phase delay time.
24. circuit as claimed in claim 23, wherein, input signal is through the time-delay equipment of all series connection, and generation has first time delayed signal of first time delay, input signal is through some odd number time-delay equipment, and generation has second time delayed signal of second time delay.
25. circuit as claimed in claim 23, wherein, each in the described odd number time-delay equipment has different time delay.
26. circuit as claimed in claim 20, wherein, rating unit comprises:
First comparison means, its receiving inputted signal and corresponding first time delayed signal produce first comparison pulse signal, and this comparison pulse signal has effective section of the duration corresponding with first time delay; And
Second comparison means, its receiving inputted signal and corresponding second time delayed signal produce second comparison pulse signal, and this comparison pulse signal has effective section of the predetermined lasting time corresponding with second time delay.
27. circuit as claimed in claim 26, wherein, first and second comparison means are NAND doors.
28. circuit as claimed in claim 26, wherein, first and second comparison pulse signals have effective period different duration.
29. circuit as claimed in claim 20, wherein, control section comprises:
The first operation control section, it receives operation and determines signal and corresponding first comparison pulse signal, determine that to operating signal and effective period duration of first comparison pulse signal compare, and generation is used to control first operating control signal of semiconductor memory apparatus; And
The second operation control section, it receives operation and determines signal and corresponding second comparison pulse signal, determine that to operating signal and effective period duration of second comparison pulse signal compare, and generation is used to control second operating control signal of semiconductor memory apparatus.
30. circuit as claimed in claim 29, wherein, first and second operating control signals represent to operate effective section effective section of whether being longer than or being shorter than first and second comparison pulse signals determining signal according to logic level separately.
31. circuit as claimed in claim 29, wherein, the first operation control section comprises:
First phase inverter, it receives operation and determines signal, and makes operation determine signal inversion;
First transmission gate, its operation response determine that the output signal of the signal and first phase inverter is transferred to first latch units with first comparison pulse signal;
First latch units, it comprises second phase inverter that the output that is used to make first transmission gate is anti-phase and makes the output of second phase inverter anti-phase and the output of the 3rd phase inverter is applied to the 3rd phase inverter of second phase inverter;
The output signal that second transmission gate, operation response are determined the signal and first phase inverter is transferred to the 4th phase inverter with the output signal of first latch units; And
The 4th phase inverter, the output signal of second transmission gate is anti-phase, and generation is as the output signal of first operating control signal.
32. circuit as claimed in claim 29, wherein, the second operation control section comprises:
The 5th phase inverter, it receives operation and determines signal, and makes operation determine signal inversion;
The 3rd transmission gate, its operation response determine that the output signal of signal and the 5th phase inverter is transferred to second latch units with second comparison pulse signal;
Second latch units comprises the hex inverter that the output that is used to make the 3rd transmission gate is anti-phase and makes the output of hex inverter anti-phase and the output of the 7th phase inverter is applied to the 7th phase inverter of hex inverter;
The output signal that the 4th transmission gate, its operation response are determined signal and the 5th phase inverter is transferred to the 8th predetermined phase inverter with the output of second latch units; And
The 8th phase inverter, its output signal with the 4th transmission gate is anti-phase, and produces the output signal as second operating control signal.
33. one kind is used to operate process for semiconductor devices, this method comprises:
Comparator input signal and first inhibit signal corresponding with described input signal are to produce the first relatively pulse;
The duration and described first duration of comparing pulse to input signal compare;
Be shorter than described first comparison during duration of pulse when the input signal duration, select first built-in function; And
When input signal lasts longer than described first comparison during duration of pulse, select second built-in function.
34. method as claimed in claim 33, wherein, input signal is a reference clock signal, and first and second built-in functions comprise operation timing, and wherein the operation of first internal operation ratio, second built-in function needs more reference clock cycle.
35. method as claimed in claim 33, wherein, input signal is a row address signal, and first built-in function is included as the request of responsive trip address signal, and temporarily activates the first inner voltage generator that replenishes.
36. method as claimed in claim 35, wherein, first and second built-in functions all are included as the request of responsive trip address signal, and temporarily activate the second inner voltage generator that replenishes.
37. method as claimed in claim 33 also comprises:
Comparator input signal and second inhibit signal corresponding with described input signal are to produce the second relatively pulse;
The duration and described second duration of comparing pulse to input signal compare, and the duration of the second comparison pulse is shorter than the duration of the first comparison pulse;
Compare the duration of pulse when input signal lasts longer than second, but be shorter than first comparison during duration of pulse, select first built-in function; And
The input signal duration is shorter than second comparison during duration of pulse, selects the 3rd built-in function.
38. method as claimed in claim 37, wherein, the 3rd built-in function comprises quiescing, and this quiescing can cause with other method.
39. method as claimed in claim 33, wherein, input signal is the time interval between adjacent two row address signals, wherein the comparator input signal duration comprises the function that alternately compares between two circuit, so that first circuit compared the time between first row address signal and second row address signal, second circuit compared the time between second row address signal and the third line address signal.
40. the semiconductor memory apparatus with control circuit of adjusting equipment behavior, this control circuit comprises:
First delay circuit, its response input signal produces first time delayed signal;
First pulse producer, it produces the first relatively pulse, and first compares pulse has the duration relevant with the time-delay of first delay circuit, and the request of response input signal is triggered; And
The first duration comparer, it produces first operating control signal, last longer than first relatively during duration of pulse when input signal, operating control signal is set to first logic state, when the duration of input signal was shorter than the duration of the first comparison pulse, operating control signal was set to second logic state.
41. memory device as claimed in claim 40 also comprises:
Second delay circuit, its response input signal produces second time delayed signal;
Second pulse producer, it produces the second relatively pulse, and second compares pulse has the duration relevant with the time-delay of second delay circuit, and the request of response input signal is triggered; And
The second duration comparer, produce second operating control signal, last longer than second relatively during duration of pulse when input signal, operating control signal is set to first logic state, when the duration of input signal is shorter than the duration of the second comparison pulse, operating control signal is set to second logic state
Wherein, the input of second delay circuit is the output of first delay circuit, so that the second comparison duration of pulse is relevant with the time-delay of first and second delay circuits.
42. memory device as claimed in claim 41, wherein, input signal is a command signal, and wherein control circuit is according to the behavior of the adjustment of the time interval between serial command equipment, and control circuit also comprises:
Trigger circuit alternately cause the relatively relatively comparison of the duration of pulse of duration or second of pulse of the time interval and first; And
Select circuit, when trigger circuit cause the comparison of the time interval and the duration of the first comparison pulse, select first operating control signal as control signal, when trigger circuit cause the comparison of the time interval and the duration of the second comparison pulse, select second operating control signal as control signal.
43. memory device as claimed in claim 40, wherein, input signal is a command signal, and wherein control circuit according to the behavior of the effective impulse width adjustment equipment of the current command signal.
44. memory device as claimed in claim 43, wherein, comprise that further fundamental voltage generator and first replenishes voltage generator, when operating control signal is set to second logic state, for assisting the temporary transient first additional voltage generator that activates of fundamental voltage generator operating control signal.
45. memory device as claimed in claim 44 wherein, comprises that further second replenishes voltage generator, response the current command signal second replenishes voltage generator and is activated to assist the fundamental voltage generator.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR81254/2001 | 2001-12-19 | ||
| KR10-2001-0081254A KR100408419B1 (en) | 2001-12-19 | 2001-12-19 | Circuit for controlling AC timing parameter of semiconductor memory device and method thereof |
| KR81254/01 | 2001-12-19 |
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| Publication Number | Publication Date |
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| CN1433025A CN1433025A (en) | 2003-07-30 |
| CN100416700C true CN100416700C (en) | 2008-09-03 |
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| CNB021542627A Expired - Fee Related CN100416700C (en) | 2001-12-19 | 2002-12-19 | AC timing parameter controlling circuit and method for semiconductor memory equipment |
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| Country | Link |
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| US (1) | US6795354B2 (en) |
| JP (2) | JP4439806B2 (en) |
| KR (1) | KR100408419B1 (en) |
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| DE (1) | DE10261768A1 (en) |
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| JP3688392B2 (en) * | 1996-05-31 | 2005-08-24 | 三菱電機株式会社 | Waveform shaping device and clock supply device |
| JP3545163B2 (en) * | 1997-04-10 | 2004-07-21 | パイオニア株式会社 | Signal conversion device and digital information recording device |
| US6163196A (en) * | 1998-04-28 | 2000-12-19 | National Semiconductor Corporation | Micropower delay circuit |
-
2001
- 2001-12-19 KR KR10-2001-0081254A patent/KR100408419B1/en not_active IP Right Cessation
-
2002
- 2002-12-16 US US10/321,242 patent/US6795354B2/en not_active Expired - Lifetime
- 2002-12-18 JP JP2002366779A patent/JP4439806B2/en not_active Expired - Fee Related
- 2002-12-19 CN CNB021542627A patent/CN100416700C/en not_active Expired - Fee Related
- 2002-12-19 DE DE10261768A patent/DE10261768A1/en not_active Ceased
-
2007
- 2007-06-08 JP JP2007153376A patent/JP2007242236A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6298004B1 (en) * | 1996-08-13 | 2001-10-02 | Fujitsu Limited | Semiconductor device, semiconductor system, and digital delay circuit |
| US6018259A (en) * | 1997-02-05 | 2000-01-25 | Samsung Electronics, Co., Ltd. | Phase locked delay circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1433025A (en) | 2003-07-30 |
| KR20030050739A (en) | 2003-06-25 |
| US20030111676A1 (en) | 2003-06-19 |
| DE10261768A1 (en) | 2003-07-31 |
| JP4439806B2 (en) | 2010-03-24 |
| JP2007242236A (en) | 2007-09-20 |
| JP2003203478A (en) | 2003-07-18 |
| KR100408419B1 (en) | 2003-12-06 |
| US6795354B2 (en) | 2004-09-21 |
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