CN100414531C

CN100414531C - Double processor communication method

Info

Publication number: CN100414531C
Application number: CNB2005100207775A
Authority: CN
Inventors: 余杰; 邓新群
Original assignee: Sichuan Changhong Electric Co Ltd
Current assignee: Sichuan Changhong Electric Co Ltd
Priority date: 2005-04-22
Filing date: 2005-04-22
Publication date: 2008-08-27
Anticipated expiration: 2025-04-22
Also published as: CN1687919A

Abstract

The present invention relates to a double-processor communication method which belongs to computer technology, particularly to the communication technology between processors. In the double-processor communication method provided by the present invention, the two processors are directly communicated with each other through a predetermined port. The present invention has the advantages of no system resource occupation by the communication between the two processors, avoidance of bus contention, system work efficiency enhancement and fine expandability.

Description

The method of double processor communication

Technical field

The present invention relates to computer technology, particularly the communication technology between the processor.

Background technology

Along with Development of Multimedia Technology, often comprise a plurality of processors in the multimedia system, each processor is finished the part work of system, thereby has effectively avoided single processor processing ability not enough or respond untimely shortcoming.But this moment, it is especially important that the collaborative work in the system between each processor just seems.Generally adopt the pci bus technology in computer realm, under the united and coordinating of system-level processor, carry out data transmission, PCI is owing to adopt modularization digital data transmission and time-division multiplex technique, and just need the communication issue of solution and system and processor at the PCI equipment development initial stage, so do not have the basic problem of system communication; And, generally adopt I in multimedia display fields such as TVs ²The C bussing technique is finished the co-ordination of each functional module, although I ²The C bus is emphasized many primary processors function, but actual multimedia system does not generally allow operation like this, otherwise will cause very easily that system is out of control, therefore, often adopts one in the multimedia system and has main I ²The processor of C interface, other processors can only have from I ²C interface is finished collaborative work between system based on this.In general, has master control I ²The processor of C interface has stronger processing power, sometimes, needs certain subsystem to have stronger processing power in the multimedia system, and because have master control I simultaneously with main system processor ²C interface and cause bus contention can only be given up best processing subsystem and has to take the second best, and has reduced the quality of system virtually.The UART asynchronous serial passes through in system generally as system debug usefulness in addition, is unfavorable for the needs of inter-processor communication.

Propose a kind of double processor communication method at present and can be implemented under the prerequisite of each several part proper communication between the system of not influencing, realized the exchanges data between two processors.

Referring to. Fig. 1 and Fig. 2 (a), Fig. 2 (b).Two-processor system comprises three parts, need finish processor, the communication channel of data communication.R1, R2 are pull-up resistor, and purpose is for improving the signal carrying load ability and guaranteeing signal integrity; P1, P2 are over-voltage protector; P3, P4 are over-current protection device; Need increase the logic buffer circuit when line between CPU is long, to guarantee signal integrity.The communication mode of two-processor system is: the first processor output order is to the GPIO port of second processor, and the second processor return message is to the GPIO port of first processor.Concrete workflow: at first CPU1, CPU2 system initialization, after CPU1 receives querying command by GPIOa transmit status querying command to the GPIOc:CPU2 of CPU2, to then thinking that CPU2 exists after the GPIOb:CPU1 of CPU1 receives correct feedback data and with its controlling object as self, otherwise CPU1 thinks that not having other master cpus exists by GPIOd return state information.

When the CPU1 operate as normal, if need the CPU2 collaborative work, then send the GPIOc of director data to CPU2 by GPIOa, CPU2 responds to instruction, instruction ignore is then by GPIOd link order invalid information, and instruction is effectively then carried out and returned execution result information by GPIOd.

In addition, under the electric electromagnetic environment of complexity, need use same instruction count, guarantee that system communication is normal, be CPU2 when the recognition instruction data if check code is incorrect or instruction itself is invalid, then the link order invalid information is to CPU1, and CPU1 then repeats to send present instruction, and the people can not effectively send and then point out communication failure in stipulated number.Shown in Fig. 2 (b), CPU2 receives the signal that sends from CPU1 GPIOa by GPIOc, is stored in the CPU internal register, simultaneously the feedback signal reception condition; CPU2 detected register value is also compared with definition of data in the data-carrier store, carries out corresponding operating, and will operate implementation status and feed back CPU 1.

Limited when the GPIO mouth of at present a lot of CPU, there is not unnecessary GPIO mouth to be used as two direct communication passages between the processor.

Summary of the invention

Technical matters to be solved by this invention is, method for communicating between a kind of dual processor is provided, and do not have when processor under the situation of unnecessary GPIO mouth, can realize the exchanges data between two processors under the prerequisite that does not influence each several part proper communication between system.

The present invention solves the technical scheme that aforementioned technical problem adopts, and a kind of method of double processor communication is provided, between two processors by the predetermined port direct communication.Described " direct communication " is meant between the CPU by independently connecting circuit communication, without bus.

Concrete implementation method is decided on the concrete condition that processor lacks the GPIO mouth:

I, when when first processor needs the second processor collaborative work, when second processor did not have unnecessary GPIO mouth, the double processor communication method specifically may further comprise the steps:

A1. the second channel control signal is communicated with the first processor and second external register;

B1. first processor output order data are to second external register;

C1. second processor is from the second external register reading command data;

D1. second processor executes instruction, and the second channel control signal is communicated with the first processor and second processor, returns the GPIO port of execution result to first processor then.

Ii, when when first processor needs the second processor collaborative work, when first processor did not have unnecessary GPIO mouth, the double processor communication method specifically may further comprise the steps:

A2. the first passage control signal is communicated with second processor and first processor;

B2. first processor output order data are to the GPIO port of second processor;

C2. second processor executes instruction, and the first passage control signal is communicated with second processor and first external register, returns execution result then to first external register;

D2. first processor is from the first external register reading command data.

Iii, when when first processor needs the second processor collaborative work, when two processors did not all have unnecessary GPIO mouth, the double processor communication method specifically may further comprise the steps:

A3. the second channel control signal is communicated with the first processor and second external register with the first passage control signal;

B3. first processor output order data are to second external register;

C3. second processor is from the second external register reading command data;

D3. second processor executes instruction, and the second channel control signal is communicated with second processor and first external register with the first passage control signal, return execution result then to first external register;

E3. first processor is from the first external register reading command data.

Further, the instruction that first processor sends comprises check code, during the second processor recognition instruction data, if the incorrect or instruction ignore of check code, then return invalid information to first processor, first processor repeats to send present instruction, surpasses preset value if send number of times, then points out communication failure.

The invention has the beneficial effects as follows not have the exchanges data between the dual processor that still can realize occupying system resources not under the situation of unnecessary GPIO mouth when processor, be with good expansibility.

The invention will be further described below in conjunction with specification drawings and specific embodiments.

Description of drawings

Fig. 1 is the process flow diagram of prior art.

Fig. 2 is the hardware configuration synoptic diagram of prior art two-processor system.

Fig. 3 is the hardware configuration synoptic diagram of the embodiment of the invention 1.

Fig. 4 is the hardware configuration synoptic diagram of the embodiment of the invention 2.

Fig. 5 is the hardware configuration synoptic diagram of the embodiment of the invention 3.

Fig. 6 is the hardware configuration synoptic diagram of the embodiment of the invention 4.

Embodiment

Embodiment 1

Referring to Fig. 3.Present embodiment is first processor CPU1 when needing the second processor CPU2 collaborative work, does not have under the unnecessary GPIO situation at CPU1, uses external register, the situation that expands GPIO as EEPROM or FLASH ROM data bus.Increase bus switch circuit on the hardware configuration, channel control signals uses CS1 (CHIPSELECT) signal of CPU1.

The GPIO that the present invention adopts needs to export a kind of of coded systems such as PWM, PAM, PPM, PCM, PNM, is generally PWM.Need the data of communication to be divided into control data, status data,, can select to use PWM, PAM with different preamble codes, PPM, PCM, PNM etc. to carry out data transmission, with the easiest realization of PWM according to the characteristic of CPU itself.Two CPU need basis system's needs configuration order response item and signal feedback item separately, and guarantee under any circumstance, the order that equal energy normal response request end sends.

Software flow: during system start-up, CPU1 connects FLASHROM by CS1 with bus switch, the calling system program; System start-up is finished, and bus switch is connected the GPIO of CPU2, and all the other flow processs are same as the prior art, all is in order to realize between two processors by the predetermined port direct communication.Concrete steps are:

A2. channel control signals CS1 is communicated with CPU1 and CPU2;

B2.CPU1 output order data are to the GPIO port of CPU2;

The c2.CPU2 execution command is communicated with the CPU1 and the first external register FLASH1 by channel control signals CS1, returns execution result then to FLASH1;

D2.CPU1 is from FLASH1 reading command data.

Embodiment 2

Referring to Fig. 4.Present embodiment is CPU1 when needing the CPU2 collaborative work, and CPU2 does not have under the situation of unnecessary GPIO and implements.Increased bus switch circuit 2 in hardware configuration, channel control signals uses the CS2 signal of CPU2.

Software flow: during system start-up, CPU2 connects FLASH ROM by CS2 with bus switch, the calling system program; System start-up is finished, and bus switch is connected the GPIO of CPU1, and all the other flow processs are identical with embodiment 1.Concrete steps:

A1. channel control signals CS2 is communicated with the CPU1 and the second external register FLASH2;

B1.CPU1 output order data are to FLASH2;

C1.CPU2 is from FLASH2 reading command data;

The d1.CPU2 execution command is communicated with CPU1 and CPU2 by channel control signals CS2, returns the GPIO port of execution result to CPU1 then.

Embodiment 3

Referring to Fig. 5.Present embodiment be CPU1 CPU2 all do not have performance under the situation of unnecessary GPIO.Increased by two bus switch circuits on the hardware configuration, channel control signals use respectively CPU1 CPU2 CS1 the CS2 signal.

Software flow: during system start-up, CPU1 connects FLASHROM by CS1 with bus switch, the calling system program; System start-up is finished, bus switch 1 turn-on bus switch 2.CPU2 connects FLASH2, calling system program by CS2 with bus switch 2; System start-up is finished, bus switch 2 turn-on bus switches 1.All the other flow processs are identical with embodiment 1.Concrete steps:

A3. channel control signals CS2 is communicated with CPU2 and FLASH2 with channel control signals CS1;

B3.CPU1 output order data are to FLASH2;

C3.CPU2 is from FLASH2 reading command data;

D3.CPU2 device execution command, channel control signals CS2 is communicated with CPU2 and FLASH1 with channel control signals CS1, returns execution result then to FLASH1;

E3.CPU1 is from FLASH1 reading command data.

Embodiment 4

Referring to Fig. 6 (a) Fig. 6 (c).Present embodiment is not have under the unnecessary GPIO situation at CPU, uses I ²The C bus expands the embodiment of GPIO, comprises three kinds of situations that may occur.Fig. 6 (a) does not have the situation of unnecessary GPIO for CPU1, and Fig. 6 (b) does not have the situation of unnecessary GPIO for CPU2, and Fig. 6 (c) is the situation that two CPU do not have unnecessary GPIO.

1 ²C bus, GPIO port translation circuit have belonged to mature technology, can be by 1 as PHILIPS PCF8574 monolithic ²C expands 8 road GPIO ports.Repeat no more herein.

Claims

1. the method for double processor communication is characterized in that, by the predetermined port direct communication, specifically may further comprise the steps between two processors:

A1. second processor is communicated with the first processor and second external register by the second channel control signal;

B1. first processor output order data are to second external register;

C1. second processor is from the second external register reading command data;

D1. second processor execution command is communicated with the first processor and second processor by the second channel control signal, returns the GPIO port of execution result to first processor then.

2. the method for double processor communication as claimed in claim 1, it is characterized in that, the instruction that first processor sends comprises check code, during the second processor recognition instruction data, if the incorrect or instruction ignore of check code is then returned invalid information to first processor, first processor repeats to send present instruction, surpass preset value if send number of times, then point out communication failure.

3. the double processor communication method is characterized in that, by the predetermined port direct communication, specifically may further comprise the steps between two processors:

A2. first processor is communicated with second processor and first processor by the first passage control signal;

B2. first processor output order data are to the GPIO port of second processor;

C2. second processor execution command is communicated with second processor and first external register by the first passage control signal, returns execution result then to first external register;

D2. first processor is from the first external register reading command data.

4. the method for double processor communication as claimed in claim 2, it is characterized in that, the instruction that first processor sends comprises check code, during the second processor recognition instruction data, if the incorrect or instruction ignore of check code is then returned invalid information to first processor, first processor repeats to send present instruction, surpass preset value if send number of times, then point out communication failure.

5. the double processor communication method is characterized in that, by the predetermined port direct communication, specifically may further comprise the steps between two processors:

A3. second processor is communicated with the first processor and second external register by the second channel control signal with the first passage control signal;

B3. first processor output order data are to second external register;

C3. second processor is from the second external register reading command data;

D3. second processor execution command is communicated with second processor and first external register by the second channel control signal with the first passage control signal, returns execution result then to first external register;

E3. first processor is from the first external register reading command data.

6. the method for double processor communication as claimed in claim 5, it is characterized in that, the instruction that first processor sends comprises check code, during the second processor recognition instruction data, if the incorrect or instruction ignore of check code is then returned invalid information to first processor, first processor repeats to send present instruction, surpass preset value if send number of times, then point out communication failure.