CN100407136C - 使用睡眠-唤醒机制来执行指令的方法和装置 - Google Patents

使用睡眠-唤醒机制来执行指令的方法和装置 Download PDF

Info

Publication number
CN100407136C
CN100407136C CN2005100798027A CN200510079802A CN100407136C CN 100407136 C CN100407136 C CN 100407136C CN 2005100798027 A CN2005100798027 A CN 2005100798027A CN 200510079802 A CN200510079802 A CN 200510079802A CN 100407136 C CN100407136 C CN 100407136C
Authority
CN
China
Prior art keywords
processor
lock
instruction
sleep
incident
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2005100798027A
Other languages
English (en)
Chinese (zh)
Other versions
CN1716186A (zh
Inventor
布拉廷·萨哈
马修·默藤
珀尔·哈马伦德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1716186A publication Critical patent/CN1716186A/zh
Application granted granted Critical
Publication of CN100407136C publication Critical patent/CN100407136C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858Result writeback, i.e. updating the architectural state or memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526Mutual exclusion algorithms
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/52Indexing scheme relating to G06F9/52
    • G06F2209/521Atomic

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Advance Control (AREA)
CN2005100798027A 2004-06-30 2005-06-29 使用睡眠-唤醒机制来执行指令的方法和装置 Expired - Fee Related CN100407136C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/880,638 2004-06-30
US10/880,638 US8607241B2 (en) 2004-06-30 2004-06-30 Compare and exchange operation using sleep-wakeup mechanism

Publications (2)

Publication Number Publication Date
CN1716186A CN1716186A (zh) 2006-01-04
CN100407136C true CN100407136C (zh) 2008-07-30

Family

ID=34941754

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005100798027A Expired - Fee Related CN100407136C (zh) 2004-06-30 2005-06-29 使用睡眠-唤醒机制来执行指令的方法和装置

Country Status (6)

Country Link
US (2) US8607241B2 (cg-RX-API-DMAC7.html)
EP (1) EP1612661A3 (cg-RX-API-DMAC7.html)
JP (2) JP2006031691A (cg-RX-API-DMAC7.html)
KR (1) KR100829638B1 (cg-RX-API-DMAC7.html)
CN (1) CN100407136C (cg-RX-API-DMAC7.html)
TW (1) TWI285332B (cg-RX-API-DMAC7.html)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8099538B2 (en) 2006-03-29 2012-01-17 Intel Corporation Increasing functionality of a reader-writer lock
US20070271450A1 (en) * 2006-05-17 2007-11-22 Doshi Kshitij A Method and system for enhanced thread synchronization and coordination
US8468526B2 (en) * 2006-06-30 2013-06-18 Intel Corporation Concurrent thread execution using user-level asynchronous signaling
KR101205323B1 (ko) * 2006-09-28 2012-11-27 삼성전자주식회사 리텐션 입/출력 장치를 이용하여 슬립모드를 구현하는시스템 온 칩
WO2009050644A1 (en) * 2007-10-18 2009-04-23 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8145849B2 (en) * 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8452947B2 (en) * 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8612977B2 (en) * 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8880853B2 (en) * 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8386822B2 (en) * 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8015379B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Wake-and-go mechanism with exclusive system bus response
US8250396B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8316218B2 (en) * 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8788795B2 (en) * 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US8640141B2 (en) * 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8145931B2 (en) * 2008-05-27 2012-03-27 Sharp Laboratories Of America, Inc. Imaging device with adaptive power saving behavior and method for use thereon
US8555292B2 (en) * 2008-06-27 2013-10-08 Microsoft Corporation Synchronizing communication over shared memory
EP2144163A1 (en) * 2008-07-09 2010-01-13 Software AG Method and system for synchronizing the execution of a critical code section
US7792916B2 (en) * 2008-10-20 2010-09-07 International Business Machines Corporation Management of cluster-wide resources with shared variables
US20100146169A1 (en) * 2008-12-05 2010-06-10 Nuvoton Technology Corporation Bus-handling
US8886919B2 (en) 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources
US8145723B2 (en) * 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8230201B2 (en) * 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
US8082315B2 (en) * 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US8156275B2 (en) 2009-05-13 2012-04-10 Apple Inc. Power managed lock optimization
US8266383B1 (en) * 2009-09-28 2012-09-11 Nvidia Corporation Cache miss processing using a defer/replay mechanism
US8601242B2 (en) * 2009-12-18 2013-12-03 Intel Corporation Adaptive optimized compare-exchange operation
US8464035B2 (en) * 2009-12-18 2013-06-11 Intel Corporation Instruction for enabling a processor wait state
US8996845B2 (en) * 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
US8516577B2 (en) * 2010-09-22 2013-08-20 Intel Corporation Regulating atomic memory operations to prevent denial of service attack
US8732496B2 (en) * 2011-03-24 2014-05-20 Nvidia Corporation Method and apparatus to support a self-refreshing display device coupled to a graphics controller
JP5819184B2 (ja) 2011-12-28 2015-11-18 富士通株式会社 情報処理装置及び情報処理装置の制御方法
CN104583956B (zh) 2012-06-15 2019-01-04 英特尔公司 用于实现加载存储重新排序和优化的指令定义
EP2862058B1 (en) * 2012-06-15 2021-05-19 Intel Corporation A semaphore method and system with out of order loads in a memory consistency model that constitutes loads reading from memory in order
CN104583975B (zh) 2012-06-15 2017-07-14 英特尔公司 无消歧乱序加载存储队列
EP2862061A4 (en) 2012-06-15 2016-12-21 Soft Machines Inc MEMORY PRECISION FOR VIRTUAL LOAD WITH DYNAMIC SHIPPING WINDOW WITH UNIFORM STRUCTURE
CN104823168B (zh) 2012-06-15 2018-11-09 英特尔公司 用于实现从由加载存储重新排序和优化导致的推测性转发遗漏预测/错误中恢复的方法和系统
KR101825585B1 (ko) 2012-06-15 2018-02-05 인텔 코포레이션 명확화 없는 비순차 load store 큐를 갖는 재정렬된 투기적 명령어 시퀀스들
KR20170102576A (ko) 2012-06-15 2017-09-11 인텔 코포레이션 분산된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐
US8719504B2 (en) * 2012-09-14 2014-05-06 International Business Machines Corporation Efficient processing of cache segment waiters
CN104854845B (zh) * 2012-10-04 2019-07-23 高通股份有限公司 使用高效的原子操作的方法和装置
CN103885824B (zh) * 2012-12-21 2017-06-20 华为技术有限公司 接口控制电路、设备和标识切换方法
TWI573015B (zh) 2013-06-19 2017-03-01 祥碩科技股份有限公司 防超時方法及資料處理系統
US9465432B2 (en) * 2013-08-28 2016-10-11 Via Technologies, Inc. Multi-core synchronization mechanism
US9466091B2 (en) 2013-09-26 2016-10-11 Imagination Technologies Limited Atomic memory update unit and methods
GB2520603B (en) * 2013-09-26 2016-04-06 Imagination Tech Ltd Atomic memory update unit and methods
US11257271B2 (en) 2013-09-26 2022-02-22 Imagination Technologies Limited Atomic memory update unit and methods
US9817703B1 (en) * 2013-12-04 2017-11-14 Amazon Technologies, Inc. Distributed lock management using conditional updates to a distributed key value data store
US9372500B2 (en) 2014-02-27 2016-06-21 Applied Micro Circuits Corporation Generating a timeout signal based on a clock counter associated with a data request
US10120681B2 (en) 2014-03-14 2018-11-06 International Business Machines Corporation Compare and delay instructions
US9454370B2 (en) * 2014-03-14 2016-09-27 International Business Machines Corporation Conditional transaction end instruction
US9558032B2 (en) 2014-03-14 2017-01-31 International Business Machines Corporation Conditional instruction end operation
US10198274B2 (en) * 2015-03-27 2019-02-05 Intel Corporation Technologies for improved hybrid sleep power management
US10191747B2 (en) * 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
CN105068904A (zh) * 2015-08-17 2015-11-18 浪潮电子信息产业股份有限公司 一种linux系统下自动计算内存理论带宽的方法
US11216378B2 (en) * 2016-09-19 2022-01-04 Advanced Micro Devices, Inc. Techniques for handling cache coherency traffic for contended semaphores
CN110825530B (zh) * 2018-08-10 2022-12-23 昆仑芯(北京)科技有限公司 用于人工智能芯片的指令执行方法和装置
US10901807B2 (en) 2019-01-02 2021-01-26 International Business Machines Corporation Computer system with concurrency for multithreaded applications
US11105645B2 (en) * 2019-05-28 2021-08-31 Glazberg, Applebaum & co. Navigation in vehicles and in autonomous cars
CN112130904B (zh) * 2020-09-22 2024-04-30 黑芝麻智能科技(上海)有限公司 处理系统、处理器间通信方法、以及共享资源管理方法
JP7509021B2 (ja) * 2020-12-14 2024-07-02 トヨタ自動車株式会社 車載システム、車載システム制御方法、及び車載システム制御プログラム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05225149A (ja) * 1992-02-13 1993-09-03 Toshiba Corp ロック方式
JPH07319716A (ja) * 1994-05-23 1995-12-08 Hitachi Ltd 計算機システムの資源の排他制御方式
JP2001084235A (ja) * 1999-09-10 2001-03-30 Nec Corp ロック粒度統計情報を利用した排他制御方法及びプログラムを記録した機械読み取り可能な記録媒体

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274809A (en) * 1988-05-26 1993-12-28 Hitachi, Ltd. Task execution control method for a multiprocessor system with enhanced post/wait procedure
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JP3745800B2 (ja) 1995-09-29 2006-02-15 富士通株式会社 共有資源の排他制御方式
US5787026A (en) * 1995-12-20 1998-07-28 Intel Corporation Method and apparatus for providing memory access in a processor pipeline
US6938263B2 (en) * 1996-04-23 2005-08-30 Sun Microsystems, Inc. System and method for facilitating dynamic loading of “stub” information to enable a program operating in one address space to invoke processing of a remote method or procedure in another address space
US6237024B1 (en) 1998-03-20 2001-05-22 Sun Microsystem, Inc. Method and apparatus for the suspension and continuation of remote processes
US5860126A (en) * 1996-12-17 1999-01-12 Intel Corporation Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model
US5889983A (en) * 1997-01-21 1999-03-30 Intel Corporation Compare and exchange operation in a processing system
US5790851A (en) 1997-04-15 1998-08-04 Oracle Corporation Method of sequencing lock call requests to an O/S to avoid spinlock contention within a multi-processor environment
US6112222A (en) 1998-08-25 2000-08-29 International Business Machines Corporation Method for resource lock/unlock capability in multithreaded computer environment
US6223335B1 (en) * 1998-12-09 2001-04-24 Sun Microsystems, Inc. Platform independent double compare and swap operation
US6493741B1 (en) 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
US6473819B1 (en) * 1999-12-17 2002-10-29 International Business Machines Corporation Scalable interruptible queue locks for shared-memory multiprocessor
US6886105B2 (en) * 2000-02-14 2005-04-26 Intel Corporation Method and apparatus for resuming memory operations from a low latency wake-up low power state
US6615340B1 (en) * 2000-03-22 2003-09-02 Wilmot, Ii Richard Byron Extended operand management indicator structure and method
US6502170B2 (en) * 2000-12-15 2002-12-31 Intel Corporation Memory-to-memory compare/exchange instructions to support non-blocking synchronization schemes
JP3796124B2 (ja) * 2001-03-07 2006-07-12 株式会社ルネサステクノロジ スレッド間優先度可変プロセッサ
JP4253796B2 (ja) 2001-11-08 2009-04-15 富士通株式会社 コンピュータ及び制御方法
US7127561B2 (en) * 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US7363474B2 (en) 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
JP2004135875A (ja) 2002-10-17 2004-05-13 Konsho Ryu 巻取り装置付き靴
US7559060B2 (en) * 2003-06-10 2009-07-07 National Instruments Corporation Time-bounded program execution
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
EP1503309A1 (en) * 2003-07-31 2005-02-02 Deutsche Börse Ag Data validity control in straight-through processing systems
JP2005225149A (ja) 2004-02-16 2005-08-25 Mitsubishi Paper Mills Ltd インクジェット記録材料
JP4376692B2 (ja) 2004-04-30 2009-12-02 富士通株式会社 情報処理装置、プロセッサ、プロセッサの制御方法、情報処理装置の制御方法、キャッシュメモリ
US7529914B2 (en) * 2004-06-30 2009-05-05 Intel Corporation Method and apparatus for speculative execution of uncontended lock instructions
US7437581B2 (en) * 2004-09-28 2008-10-14 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism
US7555630B2 (en) * 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US8010969B2 (en) * 2005-06-13 2011-08-30 Intel Corporation Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
US7882339B2 (en) * 2005-06-23 2011-02-01 Intel Corporation Primitives to enhance thread-level speculation
US8099538B2 (en) 2006-03-29 2012-01-17 Intel Corporation Increasing functionality of a reader-writer lock
JP4129532B2 (ja) 2007-09-11 2008-08-06 株式会社高尾 弾球遊技機
US7904696B2 (en) 2007-09-14 2011-03-08 Intel Corporation Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
US8555016B2 (en) 2008-12-17 2013-10-08 Intel Corporation Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
US8316194B2 (en) 2009-12-15 2012-11-20 Intel Corporation Mechanisms to accelerate transactions using buffered stores
US8479053B2 (en) 2010-07-28 2013-07-02 Intel Corporation Processor with last branch record register storing transaction indicator
US8446903B1 (en) 2012-05-22 2013-05-21 Intel Corporation Providing a load/store communication protocol with a low power physical unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05225149A (ja) * 1992-02-13 1993-09-03 Toshiba Corp ロック方式
JPH07319716A (ja) * 1994-05-23 1995-12-08 Hitachi Ltd 計算機システムの資源の排他制御方式
JP2001084235A (ja) * 1999-09-10 2001-03-30 Nec Corp ロック粒度統計情報を利用した排他制御方法及びプログラムを記録した機械読み取り可能な記録媒体

Also Published As

Publication number Publication date
JP5054665B2 (ja) 2012-10-24
US20060005197A1 (en) 2006-01-05
CN1716186A (zh) 2006-01-04
US9733937B2 (en) 2017-08-15
JP2009151793A (ja) 2009-07-09
EP1612661A2 (en) 2006-01-04
US8607241B2 (en) 2013-12-10
KR20060048630A (ko) 2006-05-18
TWI285332B (en) 2007-08-11
JP2006031691A (ja) 2006-02-02
TW200614075A (en) 2006-05-01
KR100829638B1 (ko) 2008-05-16
US20130232499A1 (en) 2013-09-05
EP1612661A3 (en) 2007-09-19

Similar Documents

Publication Publication Date Title
CN100407136C (zh) 使用睡眠-唤醒机制来执行指令的方法和装置
CN102722418B (zh) 用于硬件锁省略(hle)的后期锁获取机制
CN101814018B (zh) 事务存储器(tm)系统中的读和写监控属性
DE112010003330B4 (de) Einrichten von Prüfpunkten bei Cachespeichern für die spekulative Versionierung
DE60029619T2 (de) Verfahren, vorrichtung, medium und programm zur aufnahme und zum verlassen von mehreren fäden in einem vielfadenprozessor
US6823511B1 (en) Reader-writer lock for multiprocessor systems
US8316190B2 (en) Computer architecture and method of operation for multi-computer distributed processing having redundant array of independent systems with replicated memory and code striping
CA2189307C (en) Method of commitment in a distributed database transaction
US7080376B2 (en) High performance synchronization of accesses by threads to shared resources
CN1908890B (zh) 用于使用记录板机制处理加载锁定指令的方法和装置
US20060259907A1 (en) Systems and methods of sharing processing resources in a multi-threading environment
CN1983193A (zh) 用于信息处理的系统和方法
US10114748B2 (en) Distributed reservation based coherency protocol
US20020087925A1 (en) Computer processor read/alter/rewrite optimization cache invalidate signals
WO2007115003A1 (en) Transactional memory in out-of-order processors
JP2003044452A (ja) 同期メモリ・バリアを実装する方法およびシステム
CN107003896B (zh) 具有共享事务处理资源的装置和数据处理方法
US20030002440A1 (en) Ordered semaphore management subsystem
US20040117564A1 (en) System and method for reducing shared memory write overhead in multiprocessor systems
US6594733B1 (en) Cache based vector coherency methods and mechanisms for tracking and managing data use in a multiprocessor system
US20080040524A1 (en) System management mode using transactional memory
US7328322B2 (en) System and method for optimistic caching
US8219762B1 (en) Computer system and method for leasing memory location to allow predictable access to memory location
US20130144842A1 (en) Failover and resume when using ordered sequences in a multi-instance database environment
US7412572B1 (en) Multiple-location read, single-location write operations using transient blocking synchronization support

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080730

Termination date: 20180629