CN100405599C - Pixel unit and display - Google Patents

Abstract

The present invention provides a pixel unit and a display device. The pixel unit comprises a first and a second metallic layers, wherein the first metallic layer is provided with a grid electrode and a first electrode, and the second metallic layer is provided with a drain electrode, a source electrode and a second electrode. The overlapping position of the drain electrode and the grid electrode is a first overlap region, the overlapping position of the source electrode and the grid electrode is a second overlap region, and the overlapping position of the second electrode and the first electrode is a third overlap region. The size of the first electrode is as much as the second electrode, and both of the electrodes are mutually staggered. The pixel unit of the present invention can be applied to the display device. Because the capacitance value of storage capacitance of the present invention changes in company with the change of the capacitance value of parasitic capacity, deviation generated by para-position error of the capacitance value of the parasitic capacity can be automatically compensated, and then the voltage variation quantity of the storage capacitance can be fixed further. Moreover, when the voltage variation quantity of the storage capacitance is fixed, the voltage variation quantity of the storage capacitance can be compensated by a method of adjusting common voltage.

Description

Pixel cell and display unit

Technical field

The invention relates to a kind of pixel cell, particularly relevant for a kind of pixel cell of the capacitance of compensate for parasitic capacitance automatically.

Background technology

Fig. 1 a is the schematic diagram of known pixels unit.As shown in the figure, pixel cell 1 comprises thin-film transistor (Thin Film Transistor; TFT) 12 and storage capacitors (storage capacitor; C _s) 14.Thin-film transistor 12 has gate electrode 122, source electrode 124 and drain electrode 126.Gate electrode 122 couples gate line 16, and source electrode 124 couples source electrode line 18.

Because gate electrode 122 is made of the first metal layer, and source electrode 124 and drain electrode 126 are made of second metal level, therefore, when the zone 128 of semi-conductor layer was arranged between the first metal layer and second metal level, then the overlay region A and the drain electrode 126 of gate electrode 122, drain electrode 126 overlapping gate electrodes 122 can constitute a parasitic capacitance (parasitical capacitor; C _P).In addition, the overlay region B and the source electrode 124 of gate electrode 122, source electrode 124 overlapping gate electrodes 122 can constitute another parasitic capacitance.

The equivalent circuit diagram of the pixel cell of Fig. 1 b displayed map 1a.The sequential chart of the pixel cell of Fig. 1 c displayed map 1a.Please refer to Fig. 1 b and Fig. 1 c, the sweep signal on the gate line 16 is at time t ₁The time, convert high logic level to by low logic level, in order to conducting membrane transistor 12.Storage capacitors 14 and liquid crystal capacitance C _LCBegin charging according to the data-signal on the source electrode line 18, and at time t ₁In charge to voltage V ₁

At time t ₁Afterwards, the sweep signal on the gate line 16 converts low logic level to by high logic level, makes thin-film transistor 12 convert not on-state to by conducting state, this moment storage capacitors 14 voltage V ₁₄Should remain on voltage V ₁Yet because the gate electrode 122 and 126 of the drain electrodes of thin-film transistor 12 have parasitic capacitance C _pSo, will make the voltage V of storage capacitors 14 ₁₄By voltage V1 decline Δ V.

Because storage capacitors 14 and liquid crystal capacitance C _LCThe brightness that stored voltage represent pixel unit 1 will present is so when the voltage of storage capacitors 14 changes, will make pixel cell 1 present the brightness of mistake.Known settling mode is to change the common electric voltage V that puts on first electrode 22 _ComVoltage V when storage capacitors 14 ₁₄During decline Δ V, then with common electric voltage V originally _Com1Reduce Δ V and become V _Com2, with compensate for parasitic capacitance C _pThe influence that is caused.

When making large-sized display floater, because the insufficient area of photo etched mask covers large-sized display floater, so display floater must be divided into many zones, more respectively to the pixel cell in the zones of different expose, lithography process such as development, etching.

When a certain lithography process generation bit errors, then may influence the area of the overlay region A in the pixel cell.When the area of overlay region A changes, parasitic capacitance C then _pCapacitance also can be along with variation.Because the pixel cell in each zone is not to be made into simultaneously,, thereby cause the capacitance of parasitic capacitance of the pixel cell in each zone all inequality so each zone may have bit errors separately.

When the capacitance of the parasitic capacitance on the same display floater is inequality, the influence that then can't utilize the mode of adjusting common electric voltage to come compensate for parasitic capacitance to cause.

Summary of the invention

The present invention promptly proposes for the disappearance that solves above-mentioned prior art.

The invention provides a kind of pixel cell, comprise one first and second metal level.The first metal layer has a gate electrode and one first electrode.Second metal level has a drain electrode, one source pole electrode and one second electrode.The overlapping gate electrode part of drain electrode is one first overlay region.The overlapping gate electrode part of source electrode is one second overlay region.The overlapping first electrode part of second electrode is one the 3rd overlay region.First and second electrode big or small close, and stagger mutually.

In addition, the rate of change of the area of the rate of change of the area of described first overlay region and the 3rd overlay region is positive relation, i.e. proportional relation.

The present invention provides a kind of display unit in addition, comprises one scan driver, a data driver and a plurality of pixel cell.Scanner driver is in order to provide sweep signal.Data driver is in order to provide data-signal.Each pixel cell comprises one first and second metal level.The first metal layer has a gate electrode and one first electrode.Second metal level has a drain electrode, one source pole electrode and one second electrode.The overlapping gate electrode part of drain electrode is one first overlay region.The overlapping gate electrode part of source electrode is one second overlay region.The overlapping first electrode part of second electrode is one the 3rd overlay region.This first and second electrode big or small close, and stagger mutually.

Owing to the capacitance of storage capacitors of the present invention can change along with the capacitance variation of parasitic capacitance, thus automatically the capacitance of compensate for parasitic capacitance because of the skew that bit errors produced, and then the voltage variety of stationary storage electric capacity.

And, then can utilize the method for adjusting common electric voltage when the voltage variety of storage capacitors fixedly the time, compensate the voltage variety of storage capacitors.

For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:

Description of drawings

Fig. 1 a is the schematic diagram of known pixels unit.

The equivalent circuit diagram of the pixel cell of Fig. 1 b displayed map 1a.

The sequential chart of the pixel cell of Fig. 1 c displayed map 1a.

Fig. 2 a shows first embodiment of pixel cell of the present invention.

Fig. 2 b shows second embodiment of pixel cell of the present invention.

Fig. 3 a shows the 3rd embodiment of pixel cell of the present invention.

Fig. 3 b shows the 4th embodiment of pixel cell of the present invention.

Fig. 4 a～Fig. 5 b shows other embodiment of pixel cell of the present invention.

The primary clustering symbol description:

1: pixel cell; 12: thin-film transistor;

14: storage capacitors; 122,21: gate electrode;

124,23: source electrode; 126,24: drain electrode;

16,20: gate line; 18,27: source electrode line;

128,42,44: the zone; A, B, C: overlay region;

22: the first electrodes; 25: the second electrodes;

26: connecting line.

Embodiment

Because parasitic capacitance C _pExistence, so when thin-film transistor 12 switched to not on-state by conducting state, then the voltage of storage capacitors 14 can change, its voltage variety Δ V is shown below:

$\mathrm{\ΔV}=(V_{\mathrm{gateoff}}-V_{\mathrm{gateon}})\frac{C_{\mathrm{gd}}}{C_{\mathrm{gd}}+C_S+C_{\mathrm{other}}}.....................\left(1\right)$

Wherein, C _GdBe parasitic capacitance C _pCapacitance, C _SBe the capacitance of storage capacitors 14, C _OtherFor other electric capacity (as liquid crystal capacitance C _LC) capacitance; V _GateoffGrid voltage during for thin-film transistor 12 not conductings; V _GateonGrid voltage during for thin-film transistor 12 conductings.

When bit errors does not take place, if when thin-film transistor 12 switches to not on-state by conducting state, the voltage variety Δ V of storage capacitors 14 then ₁Be shown below:

$\mathrm{\&Delta;}{V}_1=(V_{\mathrm{gateoff}}-V_{\mathrm{gateon}})\frac{C_{\mathrm{gd}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}+C_{S1}+C_{\mathrm{other}}}..................\left(2\right)$

Wherein, C _Gd1Parasitic capacitance C when bit errors does not take place _pCapacitance; C _S1The capacitance of the storage capacitors 14 when bit errors does not take place.

And when bit errors takes place, if when thin-film transistor 12 switches to not on-state by conducting state, the voltage variety Δ V of storage capacitors 14 then ₂Be shown below:

$\mathrm{\&Delta;}{V}_2=(V_{\mathrm{gateoff}}-V_{\mathrm{gateon}})\frac{C_{\mathrm{gd}2}}{C_{\mathrm{gd}2}+C_{S2}+C_{\mathrm{other}}}..................\left(3\right)$

Wherein, C _Gd2Parasitic capacitance C during for the generation bit errors _pCapacitance; C _S2The capacitance of the storage capacitors 14 during for the generation bit errors.

For the voltage variety of stationary storage electric capacity 14, so make Δ V ₁=Δ V ₂After, can get:

$(V_{\mathrm{gateoff}}-V_{\mathrm{gateon}})\frac{C_{\mathrm{gd}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}+C_{S1}+C_{\mathrm{other}}}=(V_{\mathrm{gateoff}}-V_{\mathrm{gateon}})\frac{C_{\mathrm{gd}2}}{C_{\mathrm{gd}2}+C_{S2}+C_{\mathrm{other}}}...\left(4\right)$

The abbreviation formula can get following formula after (4):

$\frac{C_{\mathrm{gd}1}}{C_{\mathrm{gd}2}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout>}}_S+C_{\mathrm{other}}}{C_{S2}+C_{\mathrm{other}}}....................................\left(5\right)$

By formula (5) as can be known, as parasitic capacitance C _pCapacitance C _GdBecause of the C of bit errors by script _Gd1Skew is C _Gd2The time, if with the capacitance of storage capacitors 14 by C originally _S1Be adjusted to C _S2The time, just can make the voltage variety of storage capacitors 14 not be subjected to the influence of bit errors.

For example, when supposing bit errors does not take place, parasitic capacitance C _pCapacitance C _Gd1Be 0.05pF, the capacitance C of storage capacitors 14 _S1Be 0.7pF, and other capacitance C _OtherBe 0.8pF.When bit errors takes place when, parasitic capacitance C _pCapacitance C _Gd2Then be 0.05+ Δ C _GdPF, the capacitance C of storage capacitors 14 _S2Then be 0.8+ Δ C _SPF, and other capacitance C _OtherBe 0.8pF, the substitution formula can get after (5):

$\frac{0.05}{0.05+\mathrm{\&Delta;}{C}_{\mathrm{gd}}}=\frac{0.7+0.8}{0.7+\mathrm{\&Delta;}{C}_S+0.8}...........................\left(6\right)$

$\mathrm{\&Delta;}{C}_S=\frac{1.5}{0.05}\&CenterDot;\mathrm{\&Delta;}{C}_{\mathrm{gd}}=30\&CenterDot;\mathrm{\&Delta;}{C}_{\mathrm{gd}}...........................\left(7\right)$

If parasitic capacitance C _pCapacitance C _GdVariation delta C _GdDuring=0.01pF, the capacitance C of storage capacitors 14 then _SVariation delta C _SAs long as equal 0.3pF, just can compensate the influence that bit errors causes.Therefore, by formula (7) as can be known, parasitic capacitance C _pCapacitance C _GdCapacitance C with storage capacitors 14 _S(as proportional relation) is proportionate.

Fig. 2 a shows first embodiment of pixel cell of the present invention.Pixel cell of the present invention can be applicable in the display unit, the data-signal that sweep signal of being exported in order to the scanner driver (not shown) of receiving and displaying device and data driver (not shown) are exported.

Pixel cell comprises first and second metal level at least, in order to constitute the drive unit of pixel cell.As shown in the figure, the first metal layer has the gate electrode 21 and first electrode 22.Gate electrode 21 couples gate line (gate line) 20.Gate line 20 gives gate electrode 21 in order to the scanner driver sweep signal that (not shown) is exported to be provided.

Second metal level has source electrode 23, drain electrode 24 and second electrode 25.Source electrode 23 couples source electrode line (source line) 27.Source electrode line 27 gives source electrode 23 in order to the data driver data-signal that (not shown) is exported to be provided.

Drain electrode 24 overlapping gate electrode 21 parts are overlay region A, and source electrode 23 overlapping gate electrode 21 parts are overlay region B.Second electrode, 25 overlapping first electrode, 22 parts are overlay region C.First electrode 22 and second electrode 25 big or small close, and stagger mutually.Second metal level also comprises a connection electrode 26, in order to connecting the drain electrode 24 and second electrode 25, and any zone that it can't overlapping the first metal layer.

Owing between the first metal layer and second metal level, have semi-conductor layer, so gate electrode 21, overlay region A and drain electrode 24 can constitute the parasitic capacitance C shown in Fig. 1 b _p, and first electrode 22, overlay region C and second electrode 25 can constitute storage capacitors 14.Gate electrode 21, source electrode 23 and drain electrode 24 can constitute the thin-film transistor 12 shown in Fig. 1 b.

Though also can form a parasitic capacitance at gate electrode 21, overlay region B and source electrode 23, but when thin-film transistor 12 not conductings, parasitic capacitance between gate electrode 21 and the source electrode 23 can't influence the stored electric charge of storage capacitors 14, so do not consider parasitic capacitance between gate electrode 21 and the source electrode 23 at this.

By changing the shape of first electrode 22 and second electrode 25, the area of overlay region C is changed along with the area of overlay region A.The present invention does not limit the shape of first electrode 22 and second electrode 25, in the present embodiment, first electrode 22 and second electrode 25 be shaped as herringbone form.

By Fig. 2 a as can be known, when drain electrode 24 and second electrode 25 are offset because of bit errors, will cause the area of overlay region A, C to diminish left, make parasitic capacitance C _pAnd the capacitance of storage capacitors 14 diminishes; And when drain electrode 24 and second electrode 25 were offset to the right because of bit errors, then the area of overlay region A, C can become greatly, made parasitic capacitance C _pAnd the capacitance of storage capacitors 14 becomes big.And when the area of overlay region A did not change, then the area of overlay region C can not change yet.

Fig. 2 b shows second embodiment of pixel cell of the present invention.The shown pixel cell of Fig. 2 b is similar in appearance to Fig. 2 a, and difference is the shape of first electrode 22 and second electrode 25.In the present embodiment, first electrode 22 and second electrode 25 is shaped as barrier shape.When drain electrode 24 moved horizontally because of bit errors, second electrode 25 also can be along with moving horizontally.Shown in Fig. 2 b, drain electrode 24 vertical gate polar curves 20, therefore, the perforate vertical gate polar curve 20 of first electrode 22 and second electrode 25.

Fig. 3 a shows the 3rd embodiment of pixel cell of the present invention.Pixel cell shown in Fig. 3 a can compensate the bit errors of vertical direction.When drain electrode 24 during because of the bit errors vertical moving, second electrode 25 also can be along with vertical moving, and then makes the area of overlay region C change with the area change of overlay region A.As shown in the figure, drain electrode 24 parallel gate polar curves 20, therefore, the perforate parallel gate polar curve 20 of first electrode 22 and second electrode 25.

Fig. 3 b shows the 4th embodiment of pixel cell of the present invention.The shown pixel cell of Fig. 3 b is similar in appearance to Fig. 3 a, and difference is the shape of first electrode 22 and second electrode 25.

The bit errors that Fig. 2 a～Fig. 3 b is mentioned is source electrode 23, drain electrode 24 and second electrode 25 that occurs in second metal level.The shown pixel cell of Fig. 4 a～Fig. 5 b then can compensate the bit errors of the semiconductor layer between the first metal layer and second metal level.

Shown in Fig. 4 a, Fig. 4 b, semiconductor layer has zone 42 and 44, zone 42 overlapping gate electrodes 21, zone 44 overlapping first electrodes 22.When zone 42 is moved to the left because of bit errors, then cause the gate electrode 21 and the overlay region area in zone 42 to reduce; And when the zone 42 of semiconductor layer moves right, then cause the gate electrode 21 and the overlay region area in zone 42 to increase.

For avoiding the overlay region area effect parasitic capacitance C in gate electrode 21 and zone 42 _pCapacitance, so when the overlay region area in gate electrode 21 and zone 42 changes, then change the area of first electrode 22 and the overlay region in zone 44 simultaneously.Shown in Fig. 5 a and Fig. 5 b, when semiconductor layer during because of the bit errors vertical moving, the area in zone 42 and 44 also can be along with variation.

Owing to the capacitance of storage capacitors of the present invention can change along with the capacitance variation of parasitic capacitance, thus automatically the capacitance of compensate for parasitic capacitance because of the skew that bit errors produced, and then the voltage variety of stationary storage electric capacity.

When the voltage variety of storage capacitors fixedly the time, then can utilize the method for adjusting common electric voltage (commonvoltage), compensate the voltage variety of storage capacitors.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any people who has the knack of this skill, without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim defines.

Claims (34)

1. pixel cell is characterized in that comprising:

One the first metal layer has a gate electrode and one first electrode; And

One second metal level, have a drain electrode, one source pole electrode and one second electrode, the overlapping gate electrode part of drain electrode is one first overlay region, and the overlapping gate electrode part of source electrode is one second overlay region, and the overlapping first electrode part of second electrode is one the 3rd overlay region; Wherein, first and second electrode big or small close, and stagger mutually.

2. pixel cell as claimed in claim 1 is characterized in that, the rate of change of the area of the rate of change of the area of described first overlay region and the 3rd overlay region is a positive relation.

3. pixel cell as claimed in claim 2 is characterized in that, described positive correlation is a proportional relation.

4. pixel cell as claimed in claim 1 is characterized in that, by changing the shape of first and second electrode, makes the area of the 3rd overlay region change along with the area of first overlay region.

5. pixel cell as claimed in claim 4 is characterized in that the shape of described first and second electrode is herring-bone form.

6. pixel cell as claimed in claim 4 is characterized in that the shape of described first and second electrode is paliform.

7. pixel cell as claimed in claim 1 is characterized in that, also comprises a connection electrode, is coupled between second electrode and the drain electrode, and when the area change of first overlay region, connection electrode can the overlapping gate electrode or first electrode.

8. pixel cell as claimed in claim 7 is characterized in that described connection electrode is made of second metal level.

9. pixel cell as claimed in claim 7 is characterized in that, when overlapping first electrode of described second electrode, then constitutes an electric capacity.

10. pixel cell as claimed in claim 9 is characterized in that described gate electrode, drain electrode and source electrode constitute a transistor.

11. pixel cell as claimed in claim 1 is characterized in that, when described second metal level level or vertical moving, will change the area of first, second and the 3rd overlay region.

12. pixel cell as claimed in claim 1, it is characterized in that, also comprise semi-conductor layer, be arranged between first and second metal level, the overlapping gate electrode part of this semiconductor layer is one the 4th overlay region, and the overlapping first electrode part is one the 5th overlay region.

13. pixel cell as claimed in claim 12 is characterized in that, when described semiconductor layer level or vertical moving, will change the area of the 4th and the 5th overlay region.

14. pixel cell as claimed in claim 12 is characterized in that, the part of described the 4th overlay region is overlapping with first overlay region and second overlay region, the part of the 5th overlay region and the 3rd overlapping area overlapping.

15. pixel cell as claimed in claim 1 is characterized in that, described gate electrode couples a gate line; When vertical this gate line of drain electrode, vertical this gate line of the perforate of first and second electrode then.

16. pixel cell as claimed in claim 1 is characterized in that, described gate electrode couples a gate line; When parallel this gate line of drain electrode, parallel this gate line of the perforate of first and second electrode then.

17. pixel cell as claimed in claim 1 is characterized in that, the shape of described first electrode is identical with the shape of second electrode.

18. a display unit is characterized in that comprising:

The one scan driver is in order to provide at least one sweep signal;

One data driver is in order to provide at least one data-signal; And

A plurality of pixel cells receive described sweep signal and data-signal, and each pixel cell comprises:

One the first metal layer has a gate electrode and one first electrode, and this gate electrode receives described sweep signal; And

One second metal level, have a drain electrode, one source pole electrode and one second electrode, the overlapping gate electrode part of drain electrode is one first overlay region, and the overlapping gate electrode part of source electrode is one second overlay region, and the overlapping first electrode part of second electrode is one the 3rd overlay region; Wherein, first and second electrode big or small close, and stagger mutually.

19. display unit as claimed in claim 18 is characterized in that, the rate of change of the area of the rate of change of the area of described first overlay region and the 3rd overlay region is a positive relation.

20. display unit as claimed in claim 19 is characterized in that, described positive correlation is a proportional relation.

21. display unit as claimed in claim 18 is characterized in that, by changing the shape of first and second electrode, makes the area of the 3rd overlay region change along with the area change of first overlay region.

22. display unit as claimed in claim 21 is characterized in that, the shape of described first and second electrode is herring-bone form.

23. display unit as claimed in claim 21 is characterized in that, the shape of described first and second electrode is paliform.

24. display unit as claimed in claim 18 is characterized in that, also comprises a connection electrode, is coupled between second electrode and the drain electrode, when the area change of first overlay region, this connection electrode can the overlapping gate electrode or first electrode.

25. display unit as claimed in claim 24 is characterized in that, described connection electrode is made of second metal level.

26. display unit as claimed in claim 24 is characterized in that, during overlapping first electrode of described second electrode, then constitutes an electric capacity.

27. display unit as claimed in claim 26 is characterized in that, described gate electrode, drain electrode and source electrode constitute a transistor.

28. display unit as claimed in claim 18 is characterized in that, when described second metal level level or vertical moving, will change the area of first, second and the 3rd overlay region.

29. display unit as claimed in claim 18, it is characterized in that described pixel cell also comprises semi-conductor layer, be arranged between first and second metal level, the overlapping gate electrode part of this semiconductor layer is one the 4th overlay region, and the overlapping first electrode part is one the 5th overlay region.

30. display unit as claimed in claim 29 is characterized in that, when described semiconductor layer level or vertical moving, will change the area of the 4th and the 5th overlay region.

31. display unit as claimed in claim 30 is characterized in that, the part of described the 4th overlay region is overlapping with first overlay region and second overlay region, the part of described the 5th overlay region and the 3rd overlapping area overlapping.

32. display unit as claimed in claim 18 is characterized in that, described gate electrode couples a gate line; When vertical this gate line of drain electrode, vertical this gate line of the perforate of first and second electrode then.

33. display unit as claimed in claim 18 is characterized in that, described gate electrode couples a gate line; When parallel this gate line of drain electrode, parallel this gate line of the perforate of first and second electrode then.

34. display unit as claimed in claim 18 is characterized in that, the shape of described first electrode is identical with the shape of second electrode.

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