CN100405599C - Pixel unit and display device - Google Patents

Abstract

The invention provides a pixel unit and a display device. The pixel unit comprises a first metal layer and a second metal layer, wherein the first metal layer is provided with a grid electrode and a first electrode, the second metal layer is provided with a drain electrode, a source electrode and a second electrode, the drain electrode is overlapped with the grid electrode to form a first overlapped area, the source electrode is overlapped with the grid electrode to form a second overlapped area, the second electrode is overlapped with the first electrode to form a third overlapped area, and the first electrode and the second electrode are close in size and are mutually staggered. The pixel unit can be applied to a display device. The capacitance value of the storage capacitor of the invention can change along with the capacitance value change of the parasitic capacitor, so the offset of the capacitance value of the parasitic capacitor caused by the alignment error can be automatically compensated, and the voltage change of the storage capacitor is further fixed. When the voltage variation of the storage capacitor is fixed, the voltage variation of the storage capacitor can be compensated by adjusting the common voltage.

Description

Pixel unit and display device

technical field

The present invention relates to a pixel unit, in particular to a pixel unit capable of automatically compensating the capacitance of a parasitic capacitance.

Background technique

Figure 1a is a schematic diagram of a known pixel unit. As shown in the figure, the pixel unit 1 includes a thin film transistor (Thin Film Transistor; TFT) 12 and a storage capacitor (storage capacitor; C _s ) 14 . The thin film transistor 12 has a gate electrode 122 , a source electrode 124 and a drain electrode 126 . The gate electrode 122 is coupled to the gate line 16 , and the source electrode 124 is coupled to the source line 18 .

Since the gate electrode 122 is made of the first metal layer, and the source electrode 124 and the drain electrode 126 are made of the second metal layer, when the region 128 of a semiconductor layer is disposed on the first metal layer and the second metal layer When between the two metal layers, the gate electrode 122 , the overlapping region A where the drain electrode 126 overlaps the gate electrode 122 , and the drain electrode 126 can form a parasitic capacitor (C _P ). In addition, the gate electrode 122 , the overlapping region B where the source electrode 124 overlaps the gate electrode 122 , and the source electrode 124 may constitute another parasitic capacitance.

FIG. 1b shows an equivalent circuit diagram of the pixel unit in FIG. 1a. FIG. 1c shows a timing diagram of the pixel unit of FIG. 1a. Please refer to FIG. 1b and FIG. 1c , the scanning signal on the gate line 16 is converted from a low logic level to a high logic level at time _t1 to turn on the thin film transistor 12 . The storage capacitor 14 and the liquid crystal capacitor C _LC start to charge according to the data signal on the source line 18 , and charge to the voltage V ₁ within the time t ₁ .

After time _t1 , the scanning signal on the gate line 16 is converted from a high logic level to a low logic level, so that the thin film transistor 12 is converted from a conduction state to a non-conduction state, and the voltage V 14 of the storage capacitor ₁₄ is now Should be kept at voltage V ₁ . However, due to the parasitic capacitance C _p between the gate electrode 122 and the drain electrode 126 of the thin film transistor 12 , the voltage V ₁₄ of the storage capacitor 14 will drop by ΔV from the voltage V1 .

Since the voltage stored in the storage capacitor 14 and the liquid crystal capacitor C _LC represents the brightness to be displayed by the pixel unit 1 , when the voltage of the storage capacitor 14 changes, the pixel unit 1 will display a wrong brightness. A known solution is to vary the common voltage V _com applied to the first electrode 22 . When the voltage V 14 of the storage capacitor ₁₄ drops by ΔV, the original common voltage V _com1 is reduced by ΔV to become V _com2 , so as to compensate the influence caused by the parasitic capacitance C _p .

When manufacturing a large-sized display panel, since the area of the photolithography mask is not enough to cover the large-sized display panel, the display panel must be divided into many areas, and then the pixel units in different areas are exposed, developed, and etched. And other lithography process.

When an alignment error occurs in a certain lithography process, it may affect the area of the overlapping region A in the pixel unit. When the area of the overlapping region A changes, the capacitance value of the parasitic capacitor C _p will also change accordingly. Since the pixel units in each area are not manufactured at the same time, each area may have its own alignment error, thus resulting in different capacitance values of the parasitic capacitors of the pixel units in each area.

When the capacitance values of the parasitic capacitors on the same display panel are different, the influence caused by the parasitic capacitors cannot be compensated by adjusting the common voltage.

Contents of the invention

The present invention is proposed in order to solve the deficiency of the above-mentioned prior art.

The invention provides a pixel unit including a first and a second metal layer. The first metal layer has a gate electrode and a first electrode. The second metal layer has a drain electrode, a source electrode, and a second electrode. The place where the drain electrode overlaps the gate electrode is a first overlapping region. The place where the source electrode overlaps the gate electrode is a second overlapping region. The place where the second electrode overlaps the first electrode is a third overlapping region. The first and second electrodes are similar in size and staggered from each other.

In addition, the rate of change of the area of the first overlapping region and the rate of change of the area of the third overlapping region have a positive phase relationship, that is, a proportional relationship.

The present invention further provides a display device including a scan driver, a data driver and a plurality of pixel units. The scan driver is used for providing scan signals. The data driver is used for providing data signals. Each pixel unit includes a first and a second metal layer. The first metal layer has a gate electrode and a first electrode. The second metal layer has a drain electrode, a source electrode, and a second electrode. The place where the drain electrode overlaps the gate electrode is a first overlapping region. The place where the source electrode overlaps the gate electrode is a second overlapping region. The place where the second electrode overlaps the first electrode is a third overlapping region. The first and second electrodes are similar in size and staggered from each other.

Since the capacitance value of the storage capacitor of the present invention changes with the capacitance value of the parasitic capacitor, the offset of the capacitance value of the parasitic capacitor due to the alignment error can be automatically compensated, thereby fixing the voltage variation of the storage capacitor.

When the voltage variation of the storage capacitor is fixed, the method of adjusting the common voltage can be used to compensate the voltage variation of the storage capacitor.

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments are specifically listed below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

Fig. 1a is a schematic diagram of a known pixel unit.

FIG. 1b shows an equivalent circuit diagram of the pixel unit in FIG. 1a.

FIG. 1c shows a timing diagram of the pixel unit of FIG. 1a.

Fig. 2a shows a first embodiment of the pixel unit of the present invention.

Fig. 2b shows a second embodiment of the pixel unit of the present invention.

Fig. 3a shows a third embodiment of the pixel unit of the present invention.

Fig. 3b shows a fourth embodiment of the pixel unit of the present invention.

4a-5b show other embodiments of the pixel unit of the present invention.

Description of main component symbols:

1: pixel unit; 12: thin film transistor;

14: Storage capacitor; 122, 21: Gate electrode;

124, 23: source electrodes; 126, 24: drain electrodes;

16, 20: gate line; 18, 27: source line;

128, 42, 44: area; A, B, C: overlapping area;

22: first electrode; 25: second electrode;

26: connecting line.

Detailed ways

Due to the existence of the parasitic capacitance _Cp , when the thin film transistor 12 is switched from the conduction state to the non-conduction state, the voltage of the storage capacitor 14 will change, and the voltage change ΔV is as follows:

$\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gate\; off</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gateon</span>}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, C _gd is the capacitance value of the parasitic capacitance C _p , C _S is the capacitance value of the storage capacitor 14 , C _other is the capacitance value of other capacitances (such as the liquid crystal capacitance C _LC ); V _gateoff is the capacitance value of the thin film transistor 12 when it is not conducting Gate voltage; V _gateon is the gate voltage when the thin film transistor 12 is turned on.

When no alignment error occurs, if the thin film transistor 12 is switched from the conduction state to the non-conduction state, the voltage variation ΔV ₁ of the storage capacitor 14 is expressed as follows:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gate\; off</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gateon</span>}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Wherein, C _gd1 is the capacitance value of the parasitic capacitor C _p when no alignment error occurs; C _S1 is the capacitance value of the storage capacitor 14 when no alignment error occurs.

When an alignment error occurs, if the thin film transistor 12 is switched from the conduction state to the non-conduction state, the voltage variation ΔV ₂ of the storage capacitor 14 is as follows:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gate\; off</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gateon</span>}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Wherein, C _gd2 is the capacitance value of the parasitic capacitance C _p when the alignment error occurs; C _S2 is the capacitance value of the storage capacitor 14 when the alignment error occurs.

In order to fix the voltage variation of the storage capacitor 14, after setting ΔV ₁ =ΔV ₂ , it can be obtained:

$<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gate\; off</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gateon</span>}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="1"\; label="C\; gd"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gate\; off</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gateon</span>}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

After simplifying formula (4), the following formula can be obtained:

$\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="1"\; label="C\; S"\; filenames="C20061000127700151.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; other</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

It can be known from formula (5) that when the capacitance C _gd of the parasitic capacitance C _p is shifted from the original C _gd1 to C _gd2 due to the alignment error, if the capacitance of the storage capacitor 14 is adjusted from the original C _S1 to C _S2 , the voltage variation of the storage capacitor 14 will not be affected by the alignment error.

For example, assuming no alignment error occurs, the capacitance C _gd1 of the parasitic capacitor C _p is 0.05 pF, the capacitance C _S1 of the storage capacitor 14 is 0.7 pF, and the other capacitances C _other are 0.8 pF. When an alignment error occurs, the capacitance C _gd2 of the parasitic capacitance C _p is 0.05+ΔC _gd pF, the capacitance C _S2 of the storage capacitor 14 is 0.8+ΔC _S pF, and the other capacitance C _other is 0.8pF , after substituting into formula (5), we can get:

$\frac{\mathrm{<span\; class="notranslate">\; 0.05</span>}}{\mathrm{<span\; class="notranslate">\; 0.05</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 0.7</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 0.8</span>}}{\mathrm{<span\; class="notranslate">\; 0.7</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 0.8</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1.5</span>}}{\mathrm{<span\; class="notranslate">\; 0.05</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 30</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

If the variation ΔC _{gd of the capacitance C gd of} the parasitic capacitor C _p =0.01pF, then the variation _ΔCS of the capacitance _CS of the storage capacitor 14 is equal to 0.3pF, which can compensate the influence caused by the alignment error. Therefore, it can be known from the formula (7) that the capacitance C _gd of the parasitic capacitance C _p is positively correlated with the capacitance _CS of the storage capacitor 14 (such as a proportional relationship).

Fig. 2a shows a first embodiment of the pixel unit of the present invention. The pixel unit of the present invention can be applied in a display device for receiving a scan signal output by a scan driver (not shown) and a data signal output by a data driver (not shown) of the display device.

The pixel unit at least includes first and second metal layers for forming a driving device for the pixel unit. As shown in the figure, the first metal layer has a gate electrode 21 and a first electrode 22 . The gate electrode 21 is coupled to a gate line 20 . The gate lines 20 are used to provide scan signals output by a scan driver (not shown) to the gate electrodes 21 .

The second metal layer has a source electrode 23 , a drain electrode 24 , and a second electrode 25 . The source electrode 23 is coupled to a source line 27 . The source line 27 is used for providing the data signal outputted by the data driver (not shown) to the source electrode 23 .

Where the drain electrode 24 overlaps the gate electrode 21 is an overlapping region A, and where the source electrode 23 overlaps the gate electrode 21 is an overlapping region B. The overlapping region C is where the second electrode 25 overlaps the first electrode 22 . The first electrode 22 and the second electrode 25 are similar in size and staggered from each other. The second metal layer also includes a connecting electrode 26 for connecting the drain electrode 24 and the second electrode 25 , which does not overlap any area of the first metal layer.

Since there is a semiconductor layer between the first metal layer and the second metal layer, the gate electrode 21, the overlapping region A and the drain electrode 24 can form a parasitic capacitance _Cp as shown in FIG. 1b, and the first electrode 22 , the overlapping region C and the second electrode 25 can form the storage capacitor 14 . The gate electrode 21 , the source electrode 23 and the drain electrode 24 can constitute a thin film transistor 12 as shown in FIG. 1 b .

Although a parasitic capacitance can also be formed at the gate electrode 21, the overlapping region B and the source electrode 23, when the thin film transistor 12 is not turned on, the parasitic capacitance between the gate electrode 21 and the source electrode 23 will not affect The electric charge stored in the storage capacitor 14, therefore, the parasitic capacitance between the gate electrode 21 and the source electrode 23 is not considered here.

By changing the shapes of the first electrode 22 and the second electrode 25 , the area of the overlapping area C can be changed along with the area of the overlapping area A. Referring to FIG. The present invention does not limit the shapes of the first electrodes 22 and the second electrodes 25 . In this embodiment, the shapes of the first electrodes 22 and the second electrodes 25 are fishbone shapes.

It can be seen from FIG. 2a that when the drain electrode 24 and the second electrode 25 are shifted to the left due to the alignment error, the areas of the overlapping regions A and C will become smaller, so that the parasitic capacitance C _p and the capacitance of the storage capacitor 14 The value becomes smaller; and when the drain electrode 24 and the second electrode 25 are shifted to the right due to the alignment error, the area of the overlapping regions A and C will become larger, so that the parasitic capacitance C _p and the capacitance value of the storage capacitor 14 get bigger. And when the area of the overlapping area A does not change, the area of the overlapping area C will not change either.

Fig. 2b shows a second embodiment of the pixel unit of the present invention. The pixel unit shown in FIG. 2b is similar to that in FIG. 2a, except that the shapes of the first electrode 22 and the second electrode 25 are different. In this embodiment, the shape of the first electrode 22 and the second electrode 25 is a fence shape. When the drain electrode 24 moves horizontally due to the misalignment, the second electrode 25 also moves horizontally. As shown in FIG. 2 b , the drain electrode 24 is perpendicular to the gate line 20 , therefore, the openings of the first electrode 22 and the second electrode 25 are perpendicular to the gate line 20 .

Fig. 3a shows a third embodiment of the pixel unit of the present invention. The pixel unit shown in FIG. 3a can compensate the alignment error in the vertical direction. When the drain electrode 24 moves vertically due to the misalignment, the second electrode 25 also moves vertically, so that the area of the overlapping region C changes with the area of the overlapping region A. As shown in the figure, the drain electrode 24 is parallel to the gate line 20 , therefore, the openings of the first electrode 22 and the second electrode 25 are parallel to the gate line 20 .

Fig. 3b shows a fourth embodiment of the pixel unit of the present invention. The pixel unit shown in FIG. 3b is similar to that in FIG. 3a, except that the shapes of the first electrode 22 and the second electrode 25 are different.

The alignment errors mentioned in FIGS. 2 a to 3 b occur in the source electrode 23 , the drain electrode 24 and the second electrode 25 of the second metal layer. However, the pixel units shown in FIGS. 4 a to 5 b can compensate the alignment error of the semiconductor layer between the first metal layer and the second metal layer.

As shown in FIGS. 4 a and 4 b , the semiconductor layer has regions 42 and 44 , the region 42 overlaps the gate electrode 21 , and the region 44 overlaps the first electrode 22 . When the region 42 moves to the left due to the alignment error, the overlapping area of the gate electrode 21 and the region 42 decreases; and when the region 42 of the semiconductor layer moves to the right, the overlap between the gate electrode 21 and the region 42 The area of overlap increases.

In order to prevent the overlapping area of the gate electrode 21 and the region 42 from affecting the capacitance value of the parasitic capacitance _Cp , when the overlapping area of the gate electrode 21 and the region 42 changes, the overlapping of the first electrode 22 and the region 44 is also changed. area of the district. As shown in FIG. 5 a and FIG. 5 b , when the semiconductor layer moves vertically due to misalignment, the areas of the regions 42 and 44 also change accordingly.

Since the capacitance value of the storage capacitor of the present invention changes with the capacitance value of the parasitic capacitor, the offset of the capacitance value of the parasitic capacitor due to the alignment error can be automatically compensated, thereby fixing the voltage variation of the storage capacitor.

When the voltage variation of the storage capacitor is fixed, the method of adjusting the common voltage can be used to compensate the voltage variation of the storage capacitor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be determined by the scope of the patent application.

Claims (34)

1. A pixel unit, characterized in that it comprises: a first metal layer having a gate electrode and a first electrode; and A second metal layer has a drain electrode, a source electrode, and a second electrode, where the drain electrode overlaps the gate electrode is a first overlapping region, and where the source electrode overlaps the gate electrode is a In the second overlapping area, the place where the second electrode overlaps the first electrode is a third overlapping area; wherein, the first and second electrodes are similar in size and staggered from each other. 2 . The pixel unit according to claim 1 , wherein the rate of change of the area of the first overlapping region is positively related to the rate of change of the area of the third overlapping region. 3 . 3. The pixel unit according to claim 2, wherein the positive phase relationship is a proportional relationship. 4. The pixel unit as claimed in claim 1, wherein the area of the third overlapping region varies with the area of the first overlapping region by changing the shapes of the first and second electrodes. 5 . The pixel unit according to claim 4 , wherein the shapes of the first and second electrodes are both fishbone. 6 . 6 . The pixel unit according to claim 4 , wherein the shapes of the first and second electrodes are both fence-like. 7 . 7. The pixel unit according to claim 1, further comprising a connection electrode coupled between the second electrode and the drain electrode, when the area of the first overlapping region changes, the connection electrodes will not overlap gate electrode or first electrode. 8. The pixel unit as claimed in claim 7, wherein the connection electrode is formed of a second metal layer. 9. The pixel unit according to claim 7, wherein when the second electrode overlaps the first electrode, a capacitor is formed. 10. The pixel unit as claimed in claim 9, wherein the gate electrode, the drain electrode and the source electrode form a transistor. 11. The pixel unit according to claim 1, wherein when the second metal layer moves horizontally or vertically, the areas of the first, second and third overlapping regions will be changed. 12. The pixel unit according to claim 1, further comprising a semiconductor layer disposed between the first and second metal layers, where the semiconductor layer overlaps the gate electrode is a fourth overlapping region, And the place overlapping the first electrode is a fifth overlapping area. 13. The pixel unit according to claim 12, wherein when the semiconductor layer moves horizontally or vertically, the areas of the fourth and fifth overlapping regions will be changed. 14 . The pixel unit according to claim 12 , wherein part of the fourth overlapping area overlaps with the first and second overlapping areas, and part of the fifth overlapping area overlaps with the third overlapping area. 15. The pixel unit according to claim 1, wherein the gate electrode is coupled to a gate line; when the drain electrode is perpendicular to the gate line, the openings of the first and second electrodes are perpendicular the gate line. 16. The pixel unit according to claim 1, wherein the gate electrode is coupled to a gate line; when the drain electrode is parallel to the gate line, the openings of the first and second electrodes are parallel the gate line. 17. The pixel unit according to claim 1, wherein the shape of the first electrode is the same as that of the second electrode. 18. A display device, characterized in that it comprises: a scan driver, used to provide at least one scan signal; a data driver for providing at least one data signal; and A plurality of pixel units receive the scanning signal and data signal, each pixel unit includes: a first metal layer having a gate electrode and a first electrode, and the gate electrode receives the scan signal; and A second metal layer has a drain electrode, a source electrode, and a second electrode, where the drain electrode overlaps the gate electrode is a first overlapping region, and where the source electrode overlaps the gate electrode is a In the second overlapping area, the place where the second electrode overlaps the first electrode is a third overlapping area; wherein, the first and second electrodes are similar in size and staggered from each other. 19. The display device according to claim 18, wherein the rate of change of the area of the first overlapping region and the rate of change of the area of the third overlapping region have a positive phase relationship. 20. The display device according to claim 19, wherein the positive correlation is a proportional relationship. 21. The display device as claimed in claim 18, wherein the area of the third overlapping region varies with the area of the first overlapping region by changing the shapes of the first and second electrodes. 22. The display device according to claim 21, wherein the first and second electrodes both have a fishbone shape. 23. The display device according to claim 21, wherein the first and second electrodes are both fence-shaped. 24. The display device according to claim 18, further comprising a connection electrode coupled between the second electrode and the drain electrode, and when the area of the first overlapping region changes, the connection electrode will not Overlapping the gate electrode or the first electrode. 25. The display device as claimed in claim 24, wherein the connection electrode is formed of a second metal layer. 26. The display device according to claim 24, wherein when the second electrode overlaps the first electrode, a capacitor is formed. 27. The display device as claimed in claim 26, wherein the gate electrode, the drain electrode and the source electrode form a transistor. 28. The display device according to claim 18, wherein when the second metal layer moves horizontally or vertically, the areas of the first, second and third overlapping regions will be changed. 29. The display device according to claim 18 , wherein the pixel unit further comprises a semiconductor layer disposed between the first and second metal layers, where the semiconductor layer overlaps the gate electrode is a first There are four overlapping regions, and the overlapping first electrode is a fifth overlapping region. 30. The display device as claimed in claim 29, wherein when the semiconductor layer moves horizontally or vertically, the areas of the fourth and fifth overlapping regions will be changed. 31. The display device according to claim 30, wherein a part of the fourth overlapping area overlaps with the first overlapping area and a second overlapping area, and a part of the fifth overlapping area overlaps with the third overlapping area . 32. The display device according to claim 18, wherein the gate electrode is coupled to a gate line; when the drain electrode is perpendicular to the gate line, the openings of the first and second electrodes are perpendicular the gate line. 33. The display device according to claim 18, wherein the gate electrode is coupled to a gate line; when the drain electrode is parallel to the gate line, the openings of the first and second electrodes are parallel the gate line. 34. The display device according to claim 18, wherein the shape of the first electrode is the same as that of the second electrode.

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