CN100403206C - Pulse frequency modulation type voltage regulator capable of extending minimum OFF time - Google Patents

Pulse frequency modulation type voltage regulator capable of extending minimum OFF time Download PDF

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CN100403206C
CN100403206C CNB2003101179379A CN200310117937A CN100403206C CN 100403206 C CN100403206 C CN 100403206C CN B2003101179379 A CNB2003101179379 A CN B2003101179379A CN 200310117937 A CN200310117937 A CN 200310117937A CN 100403206 C CN100403206 C CN 100403206C
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time
voltage
feedback signal
output voltage
pulse frequency
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CN1621988A (en
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曾光男
陈勇志
李荣钦
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Aimtron Technology Corp
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Abstract

在脉冲频率调制式(PFM)电压调节器中,使用脉冲频率调制式切换控制器产生脉冲频率调制切换信号来转换直流电压源成为输出电压。最小OFF时间控制器提供一最小OFF时间用于脉冲频率调制切换信号上。响应于该输出电压,反馈电路产生反馈信号。当输出电压低于一预定的目标电压时,OFF时间延长电路响应于该反馈信号而延长该最小OFF时间。换言之,OFF时间延长电路延长从电感传送能量至电容之时间。因而,当脉冲频率调制式电压调节器操作于重负载条件下时,输出电压之纹波有效地降低。

Figure 200310117937

In a pulse frequency modulation (PFM) voltage regulator, a pulse frequency modulation switching controller is used to generate a pulse frequency modulation switching signal to convert a DC voltage source into an output voltage. A minimum OFF time controller provides a minimum OFF time for the pulse frequency modulation switching signal. In response to the output voltage, a feedback circuit generates a feedback signal. When the output voltage is lower than a predetermined target voltage, an OFF time extension circuit extends the minimum OFF time in response to the feedback signal. In other words, the OFF time extension circuit extends the time for transferring energy from the inductor to the capacitor. Therefore, when the pulse frequency modulation voltage regulator is operated under heavy load conditions, the ripple of the output voltage is effectively reduced.

Figure 200310117937

Description

可延长最小OFF时间之脉冲频率调制式电压调节器 Pulse frequency modulated voltage regulator with extended minimum OFF time

技术领域 technical field

本发明涉及一种脉冲频率调制式(Pulse Frequency Modulated,PFM)电压调节器,尤其是涉及一种可延长最小OFF时间之PFM电压调节器,以便降低在重负载条件下的PFM电压调节器之输出电压之纹波。The present invention relates to a pulse frequency modulated (Pulse Frequency Modulated, PFM) voltage regulator, in particular to a PFM voltage regulator that can extend the minimum OFF time, so as to reduce the output of the PFM voltage regulator under heavy load conditions voltage ripple.

背景技术 Background technique

典型上,电压调节器通过适当地控制功率切换晶体管之工作循环(Duty Cycle)而实现将直流电压源调节成具有所期望的电压位准之输出电压。依据实际应用上需求,调节后的输出电压之电压位准得大于或小于原始的直流电压源之位准。在电压调节器用以控制功率切换晶体管之工作循环的各种方式中,最常见的有PFM切换控制模式以及脉冲宽度调变(Pulse Width Modulated,PWM)切换控制模式。PFM电压调节器在每当输出电压下降至目标电压时,即利用一具有固定宽度之脉冲导通功率切换晶体管,以便调节输出电压。另一方面,PWM电压调节器则通过具有一预定的工作循环之矩形波控制功率切换晶体管之开与关,以实现调节输出电压之效果。Typically, the voltage regulator adjusts the DC voltage source to an output voltage with a desired voltage level by properly controlling the duty cycle of the power switching transistor. According to actual application requirements, the voltage level of the adjusted output voltage must be greater than or lower than that of the original DC voltage source. Among the various methods used by the voltage regulator to control the duty cycle of the power switching transistor, the most common ones are the PFM switching control mode and the Pulse Width Modulated (PWM) switching control mode. The PFM voltage regulator uses a pulse with a fixed width to turn on the power switching transistor whenever the output voltage drops to the target voltage, so as to regulate the output voltage. On the other hand, the PWM voltage regulator controls the on and off of the power switching transistor through a rectangular wave with a predetermined duty cycle to achieve the effect of regulating the output voltage.

无论是PFM电压调节器或者PWM电压调节器,任一者皆无法同时在轻负载条件与重负载条件下都实现令人满意的性能。具体而言,PFM电压调节器在重负载条件下遭遇到输出电压之纹波过大的缺点。另一方面,PWM电压调节器在轻负载条件下,由于功率切换晶体管造成之功率消耗相对于输出功率而言变得相对大,导致成为一低效率的电压调节器。Whether it is a PFM voltage regulator or a PWM voltage regulator, neither can achieve satisfactory performance under light load conditions and heavy load conditions at the same time. Specifically, PFM voltage regulators suffer from excessive ripple in the output voltage under heavy load conditions. On the other hand, the PWM voltage regulator becomes an inefficient voltage regulator under light load conditions because the power consumption by the power switching transistor becomes relatively large relative to the output power.

美国专利第5,568,044号与美国专利第6,545,882号皆揭露一种:PWM电压调节器,其特征在于通过侦测电感电流之大小,而于轻负载条件下将原先的PWM控制模式改换成PFM控制模式,以改善PWM电压调节器于轻负载条件下之效率。然而,此等现有技术之电压调节器需要复杂的PWM与PFM双重模式切换电路。U.S. Patent No. 5,568,044 and U.S. Patent No. 6,545,882 both disclose a PWM voltage regulator, which is characterized in that the original PWM control mode is changed to the PFM control mode under light load conditions by detecting the magnitude of the inductor current , to improve the efficiency of the PWM voltage regulator under light load conditions. However, these prior art voltage regulators require complicated PWM and PFM dual mode switching circuits.

另外,美国专利第5,801,518号揭露一种PFM电压调节器,其特征在于按照输出电压下降的程度,延长功率切换晶体管之ON时间并/或缩短功率切换晶体管之OFF时间。此现有技术认为,更长的ON时间能储存更多的能量于电感中,同时更短的OFF时间能防止电容过度放电,因此可改善重负载条件下PFM电压调节器之输出纹波。然而,此现有技术实际上反而造成更大的输出纹波。参照美国专利第5,801,518号说明书中第8栏第31行至第35行之描述,此现有技术假设在储存于电感中的能量供给至电容后(亦即切换晶体管关闭之瞬间),PFM电压调节器之输出电压立刻上升至最大可能的峰值,随后按时间流逝而下降。实际上,此项假设在重负载的PFM电压调节器中并无法成立,下文将有详细说明。此即美国专利第5,801,518号失败的原因。In addition, US Patent No. 5,801,518 discloses a PFM voltage regulator, which is characterized in that the ON time of the power switching transistor is extended and/or the OFF time of the power switching transistor is shortened according to the degree of output voltage drop. According to the prior art, a longer ON time can store more energy in the inductor, and a shorter OFF time can prevent excessive discharge of the capacitor, thus improving the output ripple of the PFM voltage regulator under heavy load conditions. However, this prior art actually results in larger output ripple. Referring to the description in column 8, line 31 to line 35 of US Patent No. 5,801,518, this prior art assumes that after the energy stored in the inductor is supplied to the capacitor (that is, the moment the switching transistor is turned off), the PFM voltage regulation The output voltage of the device immediately rises to the maximum possible peak value and then decreases with the lapse of time. In practice, this assumption does not hold in a heavily loaded PFM voltage regulator, as will be explained in detail below. This is why US Patent No. 5,801,518 fails.

图1(a)显示现有的PFM电压调节器10之电路区块图。参照图1(a),当功率切换晶体管Q(例如NMOS晶体管)处于ON状态时,节点A之电位低于输出端点B之电位(亦即输出电压Vout),使得二极管D不导通。因而,电感L储存从直流电压源Vin所供应的能量,导致电感电流IL线性增加。此时,电容C进行放电以供应负载电流Iload,导致输出端点B处之输出电压Vout下降。当功率切换晶体管O处于OFF状态时,电感L先前所储存的能量即经由导通的二极管D传送至电容C,以提高输出端点B处之输出电压VoutFIG. 1( a ) shows a circuit block diagram of a conventional PFM voltage regulator 10 . Referring to FIG. 1(a), when the power switching transistor Q (such as an NMOS transistor) is in the ON state, the potential of the node A is lower than the potential of the output terminal B (ie, the output voltage V out ), so that the diode D is non-conductive. Therefore, the inductor L stores the energy supplied from the DC voltage source Vin , causing the inductor current I L to increase linearly. At this moment, the capacitor C discharges to supply the load current I load , causing the output voltage V out at the output terminal B to drop. When the power switching transistor O is in the OFF state, the energy previously stored in the inductor L is transferred to the capacitor C through the conduction diode D, so as to increase the output voltage V out at the output terminal B.

具体而言,PFM切换控制器11产生一PFM切换信号12,用以经由驱动器13控制功率切换晶体管Q之开与关。PFM切换信号12为一脉冲信号,其中举例而言每一脉冲得用以导通功率切换晶体管Q,而相邻脉冲间之间隔即代表功率切换晶体管Q关闭之时间。PFM切换信号12之脉冲宽度原则上是一固定的值,其由固定ON时间控制器14所决定。然而,当过电流保护电路15经由串联于功率切换晶体管Q之电阻R侦测到电感电流IL超过一预定的电流上限时,过电流保护电路15会使PFM切换控制器11缩短PFM切换信号12之脉冲宽度。另一方面,PFM切换信号12之相邻脉冲间之间隔则由反馈电路16所决定。当反馈电路16侦测到输出端点B处之输出电压Vout因电容C放电而低于目标电压时,反馈电路16触发PFM切换控制器11输出一脉冲以导通功率切换晶体管Q。然而,相邻脉冲间之间隔不可小于由最小OFF时间控制器17所决定的最小OFF时间。Specifically, the PFM switching controller 11 generates a PFM switching signal 12 for controlling the switching on and off of the power switching transistor Q via the driver 13 . The PFM switching signal 12 is a pulse signal, wherein, for example, each pulse is used to turn on the power switching transistor Q, and the interval between adjacent pulses represents the time when the power switching transistor Q is turned off. The pulse width of the PFM switching signal 12 is a fixed value in principle, which is determined by the fixed ON time controller 14 . However, when the overcurrent protection circuit 15 detects that the inductor current I L exceeds a predetermined current upper limit through the resistor R connected in series with the power switching transistor Q, the overcurrent protection circuit 15 will cause the PFM switching controller 11 to shorten the PFM switching signal 12 The pulse width. On the other hand, the interval between adjacent pulses of the PFM switching signal 12 is determined by the feedback circuit 16 . When the feedback circuit 16 detects that the output voltage V out at the output terminal B is lower than the target voltage due to the discharge of the capacitor C, the feedback circuit 16 triggers the PFM switching controller 11 to output a pulse to turn on the power switching transistor Q. However, the interval between adjacent pulses cannot be smaller than the minimum OFF time determined by the minimum OFF time controller 17 .

图1(b)显示图1(a)所示的现有PFM电压调节器10于重负载条件下之操作波形时序图。在周期P1中,当输出电压Vout下降至低于目标电压Vo(亦即输出电压Vout之直流成分)时,PFM切换信号12进入具有一固定脉冲宽度(或称ON时间)TON.con之高位准状态H,使电感电流IL线性增加以储存能量于电感L中。从图1(b)可清楚看见,在重负载条件下,输出电压Vout于固定ON时间TON.com经过后所下降的程度相当大。过了固定ON时间TON.con后,PFM切换信号12进入低位准状态L,储存于电感L中的能量释放至电容C,使输出电压Vout上升。然而,在重负载条件下,电感电流IL中可用于对电容C充电之部分相对变小,导致电容C在经过最小OFF时间TOFF.min的充电之后仍无法使输出电压Vout增加超过目标电压Vo。此时,PFM切换控制器11使PFM切换信号12再次进入具有一固定ON时间TON.com之高位准状态H。从图1(b)可清楚看见,在最小OFF时间TOFFmin内,储存于电感L中的能量并未能如同美国专利第5,801,518号所假设地完全释放至电容C(电感电流IL并未降低至零),导致输出电压Vout无法上升至最大可能的峰值。在此情况下,由于电感电流IL持续地累积,电感电流IL在周期P2与P3中终于超过电流上限Imax,迫使PFM切换信号12之固定ON时间TON.con被缩短。FIG. 1( b ) shows a timing diagram of operating waveforms of the conventional PFM voltage regulator 10 shown in FIG. 1( a ) under heavy load conditions. In the period P1, when the output voltage V out drops below the target voltage V o (that is, the DC component of the output voltage V out ), the PFM switching signal 12 enters a constant pulse width (or ON time) T ON. The high level state H of con makes the inductor current IL increase linearly to store energy in the inductor L. It can be clearly seen from FIG. 1(b) that under heavy load conditions, the output voltage V out drops considerably after the fixed ON time T ON.com passes. After the fixed ON time T ON.con , the PFM switching signal 12 enters the low level state L, and the energy stored in the inductor L is released to the capacitor C, so that the output voltage V out rises. However, under heavy load conditions, the part of the inductor current I L that can be used to charge the capacitor C is relatively small, so that the capacitor C cannot increase the output voltage V out beyond the target after the minimum OFF time T OFF.min is charged. voltage V o . At this time, the PFM switching controller 11 makes the PFM switching signal 12 enter the high level state H with a constant ON time T ON.com again. It can be clearly seen from Fig. 1(b) that within the minimum OFF time T OFFmin , the energy stored in the inductor L is not completely released to the capacitor C as assumed in US Patent No. 5,801,518 (the inductor current I L does not decrease to zero), causing the output voltage V out to fail to rise to the maximum possible peak value. In this case, since the inductor current IL continues to accumulate, the inductor current IL finally exceeds the current upper limit I max in the periods P2 and P3, forcing the fixed ON time T ON.con of the PFM switching signal 12 to be shortened.

在功率切换晶体管Q经过许多次切换之后,当周期P3中功率切换晶体管Q再次关闭时,输出电压Vout终于超过目标电压Vo。结果,连续累积于电感L中的大量能量全部释放至电容C中,造成一个非常大的输出纹波。经过一相当长的OFF时间后,输出电压Vout才从最大值Vhigh、下降至目标电压Vo,使PFM切换信号12进入固定ON时间TON.con之高位准状态H,重新导通功率切换晶体管Q以重复前述之操作。从图1(b)可清楚看见,现有的PFM电压调节器10于重负载条件下所产生的输出电压Vout具有一相当大的纹波19。After the power switching transistor Q switches many times, when the power switching transistor Q is turned off again in period P3, the output voltage V out finally exceeds the target voltage V o . As a result, a large amount of energy continuously accumulated in the inductor L is completely discharged into the capacitor C, causing a very large output ripple. After a rather long OFF time, the output voltage V out drops from the maximum value V high to the target voltage V o , so that the PFM switching signal 12 enters the high level state H of the fixed ON time T ON.con , and the power is turned on again The transistor Q is switched to repeat the aforementioned operations. It can be clearly seen from FIG. 1( b ) that the output voltage V out generated by the conventional PFM voltage regulator 10 has a rather large ripple 19 under heavy load conditions.

如前所述,由于电感L与电容C间之能量传送无法实现良好的效率,故现有的PFM电压调节器10从激活到实现稳定操作状态(亦即输出电压Vout达到目标电压Vo)所花费的过渡时间将无可避免地冗长。As mentioned above, since the energy transfer between the inductor L and the capacitor C cannot achieve good efficiency, the existing PFM voltage regulator 10 realizes a stable operation state from activation (that is, the output voltage V out reaches the target voltage V o ). The transition time taken will inevitably be lengthy.

发明内容 Contents of the invention

有鉴于前述问题,本发明之一目的在于提供一种PFM电压调节器,可延长最小OFF时间,以便降低在重负载条件下输出电压之纹波。In view of the aforementioned problems, an object of the present invention is to provide a PFM voltage regulator that can prolong the minimum OFF time so as to reduce the ripple of the output voltage under heavy load conditions.

本发明之另一目的在于提供一种PFM电压调节器,可延长最小OFF时间,不仅可有效率地操作于轻负载条件下亦可有效率地操作于重负载条件下。Another object of the present invention is to provide a PFM voltage regulator that can prolong the minimum OFF time, and can efficiently operate not only under light load conditions but also under heavy load conditions.

本发明之又一目的在于提供一种PFM电压调节器,可延长最小OFF时间,以便缩短从激活到实现稳定操作状态所花费的过渡时间。It is still another object of the present invention to provide a PFM voltage regulator that can extend the minimum OFF time so as to shorten the transition time it takes from activation to achieve a stable operating state.

在PFM电压调节器中,使用PFM切换控制器产生PFM切换信号来转换直流电压源成为输出电压。最小OFF时间控制器提供一最小OFF时间用于PFM切换信号上。响应于该输出电压,反馈电路产生反馈信号。当输出电压低于一预定的目标电压时,OFF时间延长电路响应于该反馈信号而延长该最小OFF时间。因而,当PFM电压调节器操作于重负载条件下时,输出电压之纹波有效地降低。In a PFM voltage regulator, a PFM switching controller is used to generate a PFM switching signal to convert a DC voltage source into an output voltage. The minimum OFF time controller provides a minimum OFF time for the PFM switching signal. In response to the output voltage, a feedback circuit generates a feedback signal. When the output voltage is lower than a predetermined target voltage, the OFF time extension circuit extends the minimum OFF time in response to the feedback signal. Therefore, when the PFM voltage regulator operates under heavy load conditions, the ripple of the output voltage is effectively reduced.

较佳地,PFM切换信号之最小OFF时间随着输出电压与目标电压间之差异绝对值增加而延长。Preferably, the minimum OFF time of the PFM switching signal is extended as the absolute value of the difference between the output voltage and the target voltage increases.

较佳地,该最小OFF时间控制器包括:一电容,以及一最小OFF时间设定电流源,用以对该电容充电,以便利用跨坐于该电容两极之一电位差从零增加至一预定的参考电压所花费的时间作为该预定的最小OFF时间。Preferably, the minimum OFF time controller includes: a capacitor, and a minimum OFF time setting current source for charging the capacitor so that a potential difference across the two poles of the capacitor increases from zero to a predetermined The time spent on the reference voltage serves as the predetermined minimum OFF time.

较佳地,该OFF时间延长电路包括:一延长参考电压,设定成小于一目标反馈信号,该目标反馈信号由该反馈电路响应于该预定的目标电压所产生,以及一差动电流对,用以基于该反馈信号与该延长参考电压间之差异绝对值而决定一排流电流。当该反馈信号小于该延长参考电压时,通过使用该排流电流而延长该预定的最小OFF时间。Preferably, the OFF time extension circuit includes: an extended reference voltage set to be smaller than a target feedback signal generated by the feedback circuit in response to the predetermined target voltage, and a differential current pair, It is used for determining a drain current based on the absolute value of the difference between the feedback signal and the extended reference voltage. When the feedback signal is less than the extended reference voltage, the predetermined minimum OFF time is extended by using the drain current.

依据本发明之另一态样,PFM电压调节器包括一电感性装置以及一电容性装置。该电感性装置耦合于一直流电压源。该电容性装置具有一端点耦合于该电感性装置并提供一输出电压。一PFM切换控制器产生一PFM切换信号来转换该直流电压源成为该输出电压。响应于该输出电压,一反馈电路产生一反馈信号。一最小时间控制器耦合于该PFM切换控制器,用以控制从该电感性装置传送能量至该电容性装置之一最小时间。当该输出电压低于一预定的目标电压时,一时间延长电路响应于该反馈信号而延长从该电感性装置传送能量至该电容性装置之该最小时间。According to another aspect of the present invention, a PFM voltage regulator includes an inductive device and a capacitive device. The inductive device is coupled to a DC voltage source. The capacitive device has an end coupled to the inductive device and provides an output voltage. A PFM switching controller generates a PFM switching signal to convert the DC voltage source into the output voltage. In response to the output voltage, a feedback circuit generates a feedback signal. A minimum time controller is coupled to the PFM switching controller for controlling a minimum time for transferring energy from the inductive device to the capacitive device. A time extension circuit extends the minimum time for transferring energy from the inductive device to the capacitive device in response to the feedback signal when the output voltage is lower than a predetermined target voltage.

较佳地,从该电感性装置传送能量至该电容性装置之该最小时间随着该输出电压与该目标电压间之该差异绝对值增加而延长。Preferably, the minimum time for transferring energy from the inductive device to the capacitive device increases as the absolute value of the difference between the output voltage and the target voltage increases.

依据本发明之又一态样,提供一种OFF时间延长电路,用于一PFM电压调节器。该PFM电压调节器通过具有一预定的最小OFF时间之一PFM切换信号来转换一直流电压源成一输出电压。该直流电压之一直流成分是一预定的目标电压。一反馈信号指示该输出电压。当该输出电压等于该预定的目标电压时,该反馈信号称为一目标反馈信号。一第一参考电压设定成小于该目标反馈信号。一第一差动电流对基于该反馈信号与该第一参考电压间之差异绝对值而决定一第一排流电流。当该反馈信号小于该第一参考电压时,通过使用该第一排流电流而延长该预定的最小OFF时间。According to yet another aspect of the present invention, an OFF time extension circuit for a PFM voltage regulator is provided. The PFM voltage regulator converts a DC voltage source into an output voltage through a PFM switching signal with a predetermined minimum OFF time. A DC component of the DC voltage is a predetermined target voltage. A feedback signal indicates the output voltage. When the output voltage is equal to the predetermined target voltage, the feedback signal is called a target feedback signal. A first reference voltage is set to be smaller than the target feedback signal. A first differential current pair determines a first drain current based on the absolute value of the difference between the feedback signal and the first reference voltage. When the feedback signal is less than the first reference voltage, the predetermined minimum OFF time is extended by using the first drain current.

较佳地,当该反馈信号愈低于该第一参考电压时,该第一排流电流愈大。Preferably, when the feedback signal is lower than the first reference voltage, the first drain current is larger.

较佳地,OFF时间延长电路更包含:一第二参考电压,设定成小于该第一参考电压,以及一第二差动电流对,用以基于该反馈信号与该第二参考电压间之差异绝对值而决定一第二排流电流。当该反馈信号小于该第二参考电压时,通过使用该第一与该第二排流电流而延长该预定的最小OFF时间。Preferably, the OFF time extension circuit further includes: a second reference voltage set to be smaller than the first reference voltage, and a second differential current pair for The absolute value of the difference determines a second drain current. When the feedback signal is less than the second reference voltage, the predetermined minimum OFF time is extended by using the first and the second drain currents.

较佳地,该预定的最小OFF时间是通过使用一充电电流对于一电容充电使其电位差从零增加至一预定的电压所花费的时间而决定。较佳地,该第一排流电流用以减少该充电电流。Preferably, the predetermined minimum OFF time is determined by using a charging current to charge a capacitor so that the potential difference increases from zero to a predetermined voltage. Preferably, the first drain current is used to reduce the charging current.

附图说明 Description of drawings

图1(a)显示现有的PFM电压调节器之电路区块图。FIG. 1( a ) shows a circuit block diagram of a conventional PFM voltage regulator.

图1(b)显示图1(a)所示的现有PFM电压调节器于重负载条件下之操作波形时序图。FIG. 1( b ) shows a timing diagram of operation waveforms of the conventional PFM voltage regulator shown in FIG. 1( a ) under heavy load conditions.

图2(a)至2(c)显示依据本发明之可延长最小OFF时间之PFM电压调节器之示意图。2(a) to 2(c) show schematic diagrams of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention.

图3(a)与3(b)显示依据本发明之PFM电压调节器于重负载条件下之操作时序图。3(a) and 3(b) show the timing diagrams of the operation of the PFM voltage regulator under heavy load conditions according to the present invention.

图4显示依据本发明之可延长最小OFF时间之PFM电压调节器之部分详细电路图。FIG. 4 shows a partial detailed circuit diagram of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention.

附图标记说明:Explanation of reference signs:

10         现有的PFM电压调节器10 Existing PFM voltage regulators

11                 FM切换控制器11 FM switching controller

12,22             PFM切换信号12, 22 PFM switching signal

13                 驱动器13 Drivers

14                 固定ON时间控制器14 Fixed ON time controller

15                 过电流保护电路15 Over-current protection circuit

16                 反馈电路16 Feedback circuit

17                 最小OFF时间控制器17 Minimum OFF time controller

18                 反馈信号18 Feedback signal

19,39             纹波19, 39 Ripple

21                 OFF时间延长电路21 OFF time extension circuit

31,32             输出电压从激活至稳定状态之过渡特征31, 32 Transition Characteristics of Output Voltage from Active to Steady State

211~213           排流装置211~213 Drainage device

A                  节点A node

B                  输出端点B output endpoint

C,COFF            电容C, C OFF capacitance

Comp               电压比较器Comp Voltage Comparator

D                  二极管D diode

IC.OFF             充电电流I C.OFF charge current

IL                 电感电流I L inductor current

Iload              负载电流I load load current

IOFF               最小OFF时间设定电流源I OFF minimum OFF time setting current source

Iref1~Iret3       参考电流I ref1 ~I ret3 reference current

Isk,Isk1~Isk3    排放电流I sk , I sk1 ~ I sk3 discharge current

L                  电感L Inductance

N1.1~N3.3         NMOS晶体管N 1.1 ~N 3.3 NMOS transistors

P1~P3             周期P1~P3 cycle

P1.1~P3.2         PMOS晶体管P 1.1 ~P 3.2 PMOS transistors

Q               功率切换晶体管Q Power Switching Transistor

R,R1,R2       电阻R, R1, R2 resistors

S               开关S switch

TOFF.min        最小OFF时间T OFF.min Minimum OFF time

TON.con         固定ON时间T ON.con fixed ON time

Vin             直流电压源V in DC voltage source

Vo              目标电压V o target voltage

VOFF            OFF时间参考电压V OFF OFF time reference voltage

Vout            输出电压V out output voltage

Vref1~Vref3    参考电压V ref1 ~ V ref3 reference voltage

具体实施方式 Detailed ways

下文中之说明与附图将使本发明之前述与其它目的、特征、与优点更明显。兹将参照图式详细说明依据本发明之较佳实施例。The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Preferred embodiments according to the present invention will be described in detail with reference to the drawings.

为了使本发明之技术特征更容易被了解,首先说明美国专利第5,801,518号如何错误地造成更大的输出纹波。由于在重负载条件下输出电压Vout于功率切换晶体管Q关闭之时间(下文简称为OFF时间)内下降的程度较大,此现有技术认为可利用更短的OFF时间来防止输出电压Vout降低,同时利用更长的功率切换晶体管Q导通之时间(下文简称为ON时间)来储存更多的能量于电感L中,随后补充至电容C。然而,从图1(b)可知,一旦输出电压Vout低于目标电压Vo,更长的ON时间只会导致输出电压Vout下降得更低,且使电感电流IL变得更大。再者,更短的OFF时间使得储存于电感L中的能量愈无法获得足够的时间释放至电容C,洽与现有技术原先所期望实现的补充效果背道而驰。In order to make the technical features of the present invention easier to understand, firstly, it is explained how the U.S. Patent No. 5,801,518 erroneously causes larger output ripple. Since the output voltage V out drops greatly during the time when the power switching transistor Q is turned off (hereinafter referred to as OFF time) under heavy load conditions, this prior art believes that a shorter OFF time can be used to prevent the output voltage V out from At the same time, a longer turn-on time of the power switching transistor Q (hereinafter referred to as ON time) is used to store more energy in the inductor L, and then replenish it to the capacitor C. However, as can be seen from Figure 1(b), once the output voltage V out is lower than the target voltage V o , a longer ON time will only cause the output voltage V out to drop even lower and the inductor current IL to become larger. Furthermore, the shorter OFF time makes it impossible for the energy stored in the inductor L to have enough time to be released to the capacitor C, which runs counter to the expected supplementary effect of the prior art.

图2(a)至2(c)显示依据本发明之可延长最小OFF时间之PFM电压调节器之示意图。参照图2(a),依据本发明之PFM电压调节器与图1(a)所示的PFM电压调节器10不同之处在于依据本发明之PFM电压调节器额外设置有一OFF时间延长电路21,以便实现降低输出纹波之目的。为了更容易了解本发明之技术特征,图2(a)中仅显示依据本发明之PFM电压调节器之一部分的电路,至于其余未显示的电路部分与图1(a)相同。具体而言,反馈电路16于监看输出电压Vout后,除了将反馈信号18输入PFM切换控制器11以外,也同时将反馈信号18输入至OFF时间延长电路21。当输出电压Vout低于目标电压Vo时,OFF时间延长电路21使由最小OFF时间控制器17所决定的最小OFF时间TOFF,min变长,以便导致PFM切换控制器11产生具有被延长的最小OFF时间之PFM切换信号22。2(a) to 2(c) show schematic diagrams of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention. Referring to Fig. 2 (a), the PFM voltage regulator according to the present invention is different from the PFM voltage regulator 10 shown in Fig. 1 (a) in that the PFM voltage regulator according to the present invention is additionally provided with an OFF time extension circuit 21, In order to achieve the purpose of reducing the output ripple. In order to understand the technical characteristics of the present invention more easily, only a part of the circuit of the PFM voltage regulator according to the present invention is shown in Fig. 2(a), and the remaining unshown circuit parts are the same as Fig. 1(a). Specifically, after monitoring the output voltage Vout , the feedback circuit 16 not only inputs the feedback signal 18 to the PFM switching controller 11 , but also simultaneously inputs the feedback signal 18 to the OFF time extension circuit 21 . When the output voltage V out is lower than the target voltage V o , the OFF time extension circuit 21 makes the minimum OFF time T OFF,min determined by the minimum OFF time controller 17 longer, so as to cause the PFM switching controller 11 to generate The PFM switching signal 22 of the minimum OFF time.

具体而言,OFF时间延长电路21与最小OFF时间控制器17一起合作,用以基于输出电压Vout而决定PFM切换信号22之可延长的最小OFF时间TOFF.min。举例而言,如图2(b)所示,PFM切换信号22之可延长的最小OFF时间TOFF.min得为输出电压Vout之一区域性连续递减函数,在数学上可表示为TOFF.min(Vout)。当输出电压Vout大于或等于目标电压Vo时,可延长的最小OFF时间TOFF.min为一最小值TOFF.min(Vo)。当输出电压Vout小于目标电压Vo时,可延长的最小OF时间TOFF.min随着输出电压Vout与目标电压Vo间之差异绝对值增大而逐渐增加。应注意本发明亦得应用于可延长的最小OFF时间TOFF.min为输出电压Vout之一阶梯式(stepwise)递减函数或是其它合适的函数,只要可延长的最小OFF时间TOFF.min与输出电压Vout间之函数关系满足下列不等式(1)即可:Specifically, the OFF time extension circuit 21 cooperates with the minimum OFF time controller 17 to determine the prolongable minimum OFF time T OFF.min of the PFM switching signal 22 based on the output voltage V out . For example, as shown in FIG. 2(b), the prolongable minimum OFF time T OFF.min of the PFM switching signal 22 is a regional continuous decreasing function of the output voltage V out , which can be expressed mathematically as T OFF .min (V out ). When the output voltage V out is greater than or equal to the target voltage V o , the prolongable minimum OFF time T OFF.min is a minimum value T OFF.min (V o ). When the output voltage V out is less than the target voltage V o , the extendable minimum OF time T OFF.min gradually increases as the absolute value of the difference between the output voltage V out and the target voltage V o increases. It should be noted that the present invention can also be applied to extendable minimum OFF time T OFF.min as a stepwise (stepwise) decreasing function of the output voltage V out or other suitable functions, as long as the extendable minimum OFF time T OFF.min The functional relationship with the output voltage V out can satisfy the following inequality (1):

TOFF.min(Vout<Vo)>TOFF.min(Vout=Vo)=TOFF.min(Vout>Vo)             …(1)T OFF.min (V out <V o )>T OFF.min (V out =V o )=T OFF.min (V out >V o ) …(1)

参照图2(c),当输出电压Vout低于目标电压Vo时,现有的PFM切换信号12之OFF时间维持于最小OFF时间TOFF.min(Vo),无论输出电压Vout为何。对照之下,在依据本发明之PFM电压调节器中,当输出电压Vout低于目标电压Vo时,PFM切换信号22之OFF时间按照输出电压Vout而决定之一被延长的最小OFF时间TOFF.min(Vout<Vo)。Referring to Fig. 2(c), when the output voltage V out is lower than the target voltage V o , the OFF time of the existing PFM switching signal 12 is maintained at the minimum OFF time T OFF.min (V o ), regardless of the output voltage V out . In contrast, in the PFM voltage regulator according to the present invention, when the output voltage V out is lower than the target voltage V o , the OFF time of the PFM switching signal 22 is determined according to the output voltage V out and a minimum OFF time is extended. T OFF.min (V out <V o ).

在依据本发明之PFM电压调节器中,因为PFM切换信号22之最小OFF时间TOFF.min被延长,所以储存于电感L中的能量获得更充分的时间得以传送至电容C中,避免电感电流IL持续地累积。此外,由于有更充分的时间传送电感L所储存的能量至电容C中,输出电压Vout之下降程度也因此减缓。结果,输出电压Vout之纹波有效地降低。In the PFM voltage regulator according to the present invention, since the minimum OFF time T OFF.min of the PFM switching signal 22 is extended, the energy stored in the inductor L can be transferred to the capacitor C in sufficient time to avoid the inductor current IL accumulates continuously. In addition, because there is more time to transfer the energy stored in the inductor L to the capacitor C, the drop of the output voltage V out is also slowed down. As a result, the ripple of the output voltage V out is effectively reduced.

图3(a)与3(b)显示依据本发明之PFM电压调节器于重负载条件下之操作时序图。参照图3(a),当输出电压Vout低于目标电压Vo时,依据本发明之PFM电压调节器只需进行一次晶体管切换即可使输出电压Vout提升至大于目标电压Vo,有效地防止输出电压Vout大幅度地下降。此外,由于电感电流IL避免持续地累积,故其峰值Ipeak不会超过电流上限Imax且当储存于电感L中的能量于OFF时间内释放至电容C时,输出电压Vout不会产生巨大的突起波形。比较图3(a)与图1(b)可清楚发现,依据本发明之PFM电压调节器于重负载条件下有效地降低输出电压Vout之纹波39。3(a) and 3(b) show the timing diagrams of the operation of the PFM voltage regulator under heavy load conditions according to the present invention. Referring to Fig. 3(a), when the output voltage V out is lower than the target voltage V o , the PFM voltage regulator according to the present invention only needs to perform one transistor switching to increase the output voltage V out to be higher than the target voltage V o , effectively Ground prevents the output voltage V out from dropping significantly. In addition, since the inductor current IL avoids continuous accumulation, its peak value I peak will not exceed the current upper limit I max and when the energy stored in the inductor L is released to the capacitor C during the OFF time, the output voltage V out will not be generated Huge protruding waves. Comparing FIG. 3( a ) with FIG. 1( b ), it can be clearly found that the PFM voltage regulator according to the present invention effectively reduces the ripple 39 of the output voltage V out under heavy load conditions.

除了降低输出纹波之优点以外,依据本发明之PFM电压调节器亦额外提供另一优点:缩短PFM电压调节器从激活到实现稳定操作状态(亦即输出电压Vout达到目标电压Vo)所花费的过渡时间。参照图3(b)所示,实线31代表依据本发明之PFM电压调节器从激活到实现稳定操作状态之输出电压Vout随时间之变化;虚线32则代表现有的PFM电压调节器从激活到实现稳定操作状态之输出电压Vout随时间之变化。因为依据本发明之PFM电压调节器在输出电压Vout低于目标电压Vo时延长最小OFF时间,所以更有效率地传送电感L所储存的能量至电容C中、避免电感电流IL持续地累积、且减缓输出电压Vout之下降程度。结果,输出电压Vout更迅速地达到目标电压VoIn addition to the advantage of reducing the output ripple, the PFM voltage regulator according to the present invention also provides another additional advantage: shortening the time required for the PFM voltage regulator to achieve a stable operation state (that is, the output voltage V out reaches the target voltage V o ) from being activated. Transition time spent. Shown with reference to Fig. 3 (b), solid line 31 represents according to the PFM voltage regulator of the present invention from being activated to realize the output voltage V out of the stable operating state change with time; Dotted line 32 then represents the existing PFM voltage regulator from The output voltage V out that activates to achieve a stable operating state as a function of time. Because the PFM voltage regulator according to the present invention prolongs the minimum OFF time when the output voltage V out is lower than the target voltage V o , it is more efficient to transfer the energy stored in the inductor L to the capacitor C, avoiding the continuous current IL of the inductor Accumulate and slow down the drop of the output voltage V out . As a result, the output voltage V out reaches the target voltage V o more quickly.

应注意虽然前文所述之实施例应用于升压式PFM电压调节器,但本发明不限于此而得应用于降压式PFM电压调节器,降低输出纹波并缩短从激活到实现稳定操作状态所花费的过渡时间。再者,虽然前文所述之实施例应用于不连续模式(Discontinuous Mode)PFM电压调节器,但本发明不限于此而得应用于连续模式(ContinuousMode)PFM电压调节器。It should be noted that although the foregoing embodiments are applied to a boost PFM voltage regulator, the present invention is not limited thereto but can be applied to a buck PFM voltage regulator, reducing output ripple and shortening the time from activation to steady state operation. Transition time spent. Moreover, although the foregoing embodiments are applied to a Discontinuous Mode PFM voltage regulator, the present invention is not limited thereto and can be applied to a Continuous Mode (Continuous Mode) PFM voltage regulator.

图4显示依据本发明之可延长最小OFF时间之PFM电压调节器之部分详细电路图。参照图4,最小OFF时间控制器17利用使跨坐于电容COFF两极之电位差从零达到一预定的参考电压所需花费的充电时间ΔTC来设定最小OFF时间TOFF.min。具体而言,最小OFF时间控制器17包括一电压比较器Comp,其反相端(以参考符号“-”标示)则耦合于OFF时间参考电压VOFF。电容COFF耦合于电压比较器Comp之非反相端(以参考符号“+”标示)与地面间,且受到最小OFF时间设定电流源IOFF充电。开关S耦合于电容COFF充电路径与地面间。FIG. 4 shows a partial detailed circuit diagram of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention. Referring to FIG. 4 , the minimum OFF time controller 17 uses the charging time ΔT C required to make the potential difference across the two poles of the capacitor C OFF from zero to a predetermined reference voltage to set the minimum OFF time T OFF.min . Specifically, the minimum OFF time controller 17 includes a voltage comparator Comp, whose inverting terminal (marked with a reference symbol “-”) is coupled to the OFF time reference voltage V OFF . The capacitor C OFF is coupled between the non-inverting terminal of the voltage comparator Comp (indicated by the reference symbol “+”) and the ground, and is charged by the minimum OFF time setting current source I OFF . The switch S is coupled between the charging path of the capacitor C OFF and the ground.

兹将说明最小OFF时间控制器17之操作如下。起初,开关S处于短路状态,使得跨坐于电容COFF两极之电位差为零。因为非反相端之电位低于反相端之电位VOFF,电压比较器Comp之输出端位于低位准。一旦开关S从短路状态切换至开路状态,电容COFF开始被一充电电流IC.OFF充电,导致电压比较器Comp之非反相端之电位上升。当电压比较器Comp之非反相端之电位上升至大于OFF时间参考电压VOFF时,电压比较器Comp之输出端被反相成高位准。跨坐于电容COFF两极之电位差从零达到OFF时间参考电压VOFF所需花费的充电时间ΔTC可以下列方程式(2)来表示:The operation of the minimum OFF time controller 17 will be described as follows. Initially, the switch S is in a short-circuit state, so that the potential difference across the two poles of the capacitor C OFF is zero. Because the potential of the non-inverting terminal is lower than the potential V OFF of the inverting terminal, the output terminal of the voltage comparator Comp is at a low level. Once the switch S switches from the short-circuit state to the open-circuit state, the capacitor C OFF starts to be charged by a charging current I C.OFF , causing the potential of the non-inverting terminal of the voltage comparator Comp to rise. When the potential of the non-inverting terminal of the voltage comparator Comp rises higher than the OFF time reference voltage V OFF , the output terminal of the voltage comparator Comp is inverted to a high level. The charging time ΔT C required for the potential difference across the two poles of the capacitor C OFF to reach the OFF time reference voltage V OFF from zero can be expressed by the following equation (2):

ΔTC=COFF·(VOFF/IC.OFF)        …(2)ΔT C =C OFF ·(V OFF /I C.OFF ) …(2)

最小OFF时间控制器17即利用充电时间ΔTC作为最小OFF时间TOFF.minThe minimum OFF time controller 17 uses the charging time ΔT C as the minimum OFF time T OFF.min .

在本发明中,OFF时间延长电路21通过减少充电电流IC.OFF而实现延长充电时间ΔTC(亦即最小OFF时间TOFF.min)之目的。具体而言,OFF时间延长电路21包括三组排流(Current Sinking)装置211至213,分别独立地提供三个排放电流Isk1至Isk3,以便对最小OFF时间设定电流源IOFF进行电流排放之功能。排流装置211具有两个相等的PMOS晶体管P1.1与P1.2与两个相等的NMOS晶体管N1.1与N1.2,共同形成一差动电流对(Differential Current Pair)。PMOS晶体管P1.1与P1.2之源极耦合于一起,且一电流源Iref1供应至其上。NMOS晶体管N1.1之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P1.1之漏极。NMOS晶体管N1.2之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P1.2之漏极。参考电压Vref1用以控制PMOS晶体管P1.1之栅极:而从反馈电路16而来的反馈信号18则用以控制PMOS晶体管P1.2之栅极。当反馈信号18愈大于参考电压Vref1时,PMOS晶体管P1.2之漏极电流愈接近零。当反馈信号18愈小于参考电压Vref1时,PMOS晶体管P1.2之漏极电流愈接近电流源Iref1。由于使用一NMOS晶体管N1.3来与NMOS晶体管N1.2共同形成一对电流镜(Current Mirror,),故NMOS晶体管N1.3之漏极电流等于NMOS晶体管N1.2之漏极电流,亦即PMOS晶体管P1.2之漏极电流。NMOS晶体管N1.3之漏极耦合于电容COFF之充电路径,以使NMOS晶体管N1.3之漏极电流作为排放电流Isk1In the present invention, the OFF time extension circuit 21 achieves the purpose of extending the charging time ΔT C (that is, the minimum OFF time T OFF.min ) by reducing the charging current I C.OFF . Specifically, the OFF time extension circuit 21 includes three groups of current sinking (Current Sinking) devices 211 to 213, which respectively independently provide three sinking currents I sk1 to I sk3 , so as to conduct current sinking for the minimum OFF time setting current source I OFF Emission function. The drain device 211 has two equal PMOS transistors P 1.1 and P 1.2 and two equal NMOS transistors N 1.1 and N 1.2 to form a differential current pair (Differential Current Pair). The sources of PMOS transistors P 1.1 and P 1.2 are coupled together, and a current source I ref1 is supplied thereto. The gate and drain of NMOS transistor N 1.1 are coupled together and further coupled to the drain of PMOS transistor P 1.1 . The gate and drain of NMOS transistor N 1.2 are coupled together and further coupled to the drain of PMOS transistor P 1.2 . The reference voltage V ref1 is used to control the gate of the PMOS transistor P 1.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P 1.2 . When the feedback signal 18 is greater than the reference voltage V ref1 , the drain current of the PMOS transistor P 1.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V ref1 , the drain current of the PMOS transistor P 1.2 is closer to the current source I ref1 . Since an NMOS transistor N 1.3 is used to form a pair of current mirrors (Current Mirror,) together with the NMOS transistor N 1.2 , the drain current of the NMOS transistor N 1.3 is equal to the drain current of the NMOS transistor N 1.2 , that is, the PMOS transistor P 1.2 the drain current. The drain of the NMOS transistor N 1.3 is coupled to the charging path of the capacitor C OFF , so that the drain current of the NMOS transistor N 1.3 serves as the discharge current I sk1 .

排流装置212具有两个相等的PMOS晶体管P2.1与P2.2与两个相等的NMOS晶体管N2.1与N2.2,共同形成一差动电流对。PMOS晶体管P2.1与P2.2之源极耦合于一起,且一电流源Iref2供应至其上。NMOS晶体管N2.1之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P2.1之漏极。NMOS晶体管N2.2之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P2.2之漏极。参考电压Vref2用以控制PMOS晶体管P2.1之栅极:而从反馈电路16而来的反馈信号18则用以控制PMOS晶体管P2.2之栅极。当反馈信号18愈大于参考电压Vref2时,PMOS晶体管P2.2之漏极电流愈接近零。当反馈信号18愈小于参考电压Vref2时,PMOS晶体管P2.2之漏极电流愈接近电流源Iref2。由于使用一NMOS晶体管N2.3来与NMOS晶体管N2.2共同形成一对电流镜(Current Mirror,),故NMOS晶体管N2.3之漏极电流等于NMOS晶体管N2.2之漏极电流,亦即PMOS晶体管P2.2之漏极电流。NMOS晶体管N2.3之漏极耦合于电容COFF之充电路径,以使NMOS晶体管N2.3之漏极电流作为排放电流Isk2The drain device 212 has two equal PMOS transistors P 2.1 and P 2.2 and two equal NMOS transistors N 2.1 and N 2.2 to form a differential current pair. The sources of PMOS transistors P 2.1 and P 2.2 are coupled together and a current source I ref2 is supplied thereto. The gate and drain of NMOS transistor N 2.1 are coupled together and further coupled to the drain of PMOS transistor P 2.1 . The gate and drain of NMOS transistor N 2.2 are coupled together and further coupled to the drain of PMOS transistor P 2.2 . The reference voltage V ref2 is used to control the gate of the PMOS transistor P 2.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P 2.2 . When the feedback signal 18 is greater than the reference voltage V ref2 , the drain current of the PMOS transistor P 2.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V ref2 , the drain current of the PMOS transistor P 2.2 is closer to the current source I ref2 . Since an NMOS transistor N 2.3 is used to form a pair of current mirrors (Current Mirror,) together with the NMOS transistor N 2.2 , the drain current of the NMOS transistor N 2.3 is equal to the drain current of the NMOS transistor N 2.2 , that is, the PMOS transistor P 2.2 the drain current. The drain of the NMOS transistor N 2.3 is coupled to the charging path of the capacitor C OFF , so that the drain current of the NMOS transistor N 2.3 serves as the discharge current I sk2 .

排流装置213具有两个相等的PMOS晶体管P3.1与P3.2与两个相等的NMOS晶体管N3.1与N3.2,共同形成一差动电流对。PMOS晶体管P3.1与P3.2之源极耦合于一起,且一电流源ref3供应至其上。NMOS晶体管N3.1之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P3.1之漏极。NMOS晶体管N3.2之栅极与漏极耦合于一起,且更耦合于PMOS晶体管P3.2之漏极。参考电压Vref3用以控制PMOS晶体管P3.1之栅极;而从反馈电路16而来的反馈信号18则用以控制PMOS晶体管P3.2之栅极。当反馈信号18愈大于参考电压Vref3时,PMOS晶体管P3.2之漏极电流愈接近零。当反馈信号18愈小于参考电压Vref3时,PMOS晶体管P3.2之漏极电流愈接近电流源Iref3。由于使用一NMOS晶体管N3.3来与NMOS晶体管N3.2共同形成一对电流镜(Current Mirror),故NMOS晶体管N3.3之漏极电流等于NMOS晶体管N3.2之漏极电流,亦即PMOS晶体管P3.2之漏极电流。NMOS晶体管N3.3之漏极耦合于电容COFF之充电路径,以使NMOS晶体管N3.3之漏极电流作为排放电流Isk3The drain device 213 has two equal PMOS transistors P 3.1 and P 3.2 and two equal NMOS transistors N 3.1 and N 3.2 to form a differential current pair. The sources of PMOS transistors P 3.1 and P 3.2 are coupled together and a current source ref3 is supplied thereto. The gate and drain of NMOS transistor N 3.1 are coupled together and further coupled to the drain of PMOS transistor P 3.1 . The gate and drain of NMOS transistor N 3.2 are coupled together and further coupled to the drain of PMOS transistor P 3.2 . The reference voltage V ref3 is used to control the gate of the PMOS transistor P 3.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P 3.2 . When the feedback signal 18 is greater than the reference voltage V ref3 , the drain current of the PMOS transistor P 3.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V ref3 , the drain current of the PMOS transistor P 3.2 is closer to the current source I ref3 . Since an NMOS transistor N 3.3 is used to form a pair of current mirrors (Current Mirror) together with the NMOS transistor N 3.2 , the drain current of the NMOS transistor N 3.3 is equal to the drain current of the NMOS transistor N 3.2 , that is, the drain current of the PMOS transistor P 3.2 drain current. The drain of the NMOS transistor N 3.3 is coupled to the charging path of the capacitor C OFF , so that the drain current of the NMOS transistor N 3.3 serves as the discharge current I sk3 .

因此,OFF时间延长电路21提供一总排放电流Isk,其为三个排放电流Isk1至Isk3之和。在本实施例中,参考电压Vref1设定成大于参考电压Vref2,且参考电压Vref2设定成大于参考电压Vref3。因此,当反馈信号18足够小于参考电压Vref1时,总排放电流Isk达到一最大值,其为三个电流源Iref1至Iref3之和。当反馈信号18足够大于参考电压Vref1时,总排放电流Isk达到一最小值,亦即零。由于反馈信号18用以指示着输出电压Vout,例如在本实施例中反馈信号18为输出电压Vout之分压Vout·[R2/(R1+R2)],故总排放电流Isk为输出电压Vout之一区域性连续递减函数。为了使OFF时间延长电路21在输出电压Vout小于目标电压Vo时开始对于最小OFF时间设定电流源IOFF进行电流排放之作用,参考电压Vref1得设定成些微小于由目标电压Vo经过反馈电路16所产生的一分压Vo·[R2/(R1+R2)]。Therefore, the OFF time extension circuit 21 provides a total discharge current I sk , which is the sum of the three discharge currents I sk1 to I sk3 . In this embodiment, the reference voltage V ref1 is set to be greater than the reference voltage V ref2 , and the reference voltage V ref2 is set to be greater than the reference voltage V ref3 . Therefore, when the feedback signal 18 is sufficiently smaller than the reference voltage V ref1 , the total discharge current I sk reaches a maximum value, which is the sum of the three current sources I ref1 to I ref3 . When the feedback signal 18 is sufficiently greater than the reference voltage V ref1 , the total discharge current I sk reaches a minimum value, ie, zero. Since the feedback signal 18 is used to indicate the output voltage V out , for example, in this embodiment, the feedback signal 18 is the divided voltage V out of the output voltage V out [R2/(R1+R2)], so the total discharge current I sk is One of the regionally continuously decreasing functions of the output voltage V out . In order to make the OFF time extension circuit 21 start to discharge current for the minimum OFF time setting current source I OFF when the output voltage V out is lower than the target voltage V o , the reference voltage V ref1 must be set to be slightly lower than the target voltage V o A divided voltage V o ·[R2/(R1+R2)] generated by the feedback circuit 16 .

从图3清楚可见,因为OFF时间延长电路21提供一总排放电流Isk,所以电容COFF之充电电流IC.OFF如下列方程式(3)所示:It can be clearly seen from FIG. 3 that since the OFF time extension circuit 21 provides a total discharge current I sk , the charging current I C.OFF of the capacitor C OFF is shown in the following equation (3):

IC.OFF=IOFF-Isk                 …(3)I C.OFF =I OFF -I sk …(3)

将方程式(3)代入方程式(2),跨坐于电容COFF.两极之电位差从零达到OFF时间参考电压VOFF所需花费的充电时间ΔTC可以下列方程式(4)来表示:Substitute Equation (3) into Equation (2), and straddle the capacitor C OFF . The charging time ΔT C required for the potential difference between the two poles to reach the OFF time reference voltage V OFF from zero can be expressed by the following equation (4):

ΔTC=COFF·[VOFF/(IOFF-Isk)]    …(4)ΔT C =C OFF ·[V OFF /(I OFF -I sk )] …(4)

如前所述,最小OFF时间控制器17利用充电时间ΔTC作为最小OFF时间TOFF.min且总排放电流Isk为输出电压Vout之区域性连续递减函数,故最小OFF时间TOFF.min为输出电压Vout之区域性连续递减函数,如图2(b)所示。As mentioned above, the minimum OFF time controller 17 uses the charging time ΔT C as the minimum OFF time T OFF.min and the total discharge current I sk is a regional continuous decreasing function of the output voltage V out , so the minimum OFF time T OFF.min It is a regional continuous decreasing function of the output voltage V out , as shown in Fig. 2(b).

应注意虽然在前述实施例中,OFF时间延长电路21设有三组排流装置211至213,但本发明不限于此而得应用于OFF时间延长电路21具有三组排流装置211至213中之至少一组的情况。It should be noted that although in the foregoing embodiment, the OFF time extension circuit 21 is provided with three sets of drainage devices 211 to 213, the present invention is not limited thereto and can be applied to the OFF time extension circuit 21 having three groups of drainage devices 211 to 213. At least one set of cases.

虽然本发明业已通过较佳实施例作为例示加以说明,应了解者为:本发明不限于此被揭露的实施例。相反地,本发明意欲涵盖对于熟习此项技艺之人士而言属明显的各种修改与相似配置。因此,申请专利范围之范围应根据最广的诠释,以包容所有此类修改与相似配置。Although the present invention has been described by way of illustration of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (13)

1. pulse frequency modulated voltage regulator in order to convert a direct current voltage source to an output voltage, comprises:
One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;
One feedback circuit is in order to produce a feedback signal, in response to this output voltage;
One minimal OFF time controller is used for this pulse frequency modulation switching signal in order to a predetermined minimal OFF time to be provided: and
One OFF time lengthening circuit in order to when this output voltage is lower than a predetermined target voltage, prolongs this predetermined minimal OFF time, so that reduce the ripple of this output voltage in response to this feedback signal.
2. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulation switching signal should be predetermined minimal OFF time along with absolute difference increase one of between this output voltage and this target voltage and prolong.
3. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulated voltage regulator operates under the heavy duty condition, and this predetermined target voltage is one of this an output voltage flip-flop.
4. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this minimal OFF time controller comprises:
One electric capacity, and
One minimal OFF time is set current source, in order to this electric capacity charging, increases to time that a predetermined reference voltage spent as should predetermined minimal OFF time so that utilize to ride in one of these electric capacity the two poles of the earth potential difference (PD) from zero, and
This OFF time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, and at least a portion that prevents this minimal OFF time setting current source in response to this feedback signal is to this electric capacity charging, so that prolong this predetermined minimal OFF time.
5. pulse frequency modulated voltage regulator as claimed in claim 4, wherein: this OFF time lengthening circuit comprises:
One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and
One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, prolong this predetermined minimal OFF time by using this discharging electric current.
6. pulse frequency modulated voltage regulator comprises:
One inductive means is coupled in a direct current voltage source:
One capacitive device has an end points and is coupled in this inductive means and an output voltage is provided;
One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;
One feedback circuit is in order to produce a feedback signal, in response to this output voltage;
One minimum time controller is coupled in this modulation type change-over controller, in order in each cycle of controlling this pulse frequency modulation switching signal in order to transmit energy to one of this capacitive device minimum time from this inductive means; And
One time prolonged circuit, in order to when this output voltage is lower than a predetermined target voltage, prolonged this minimum time from this inductive means transmission energy to this capacitive device in response to this feedback signal.
7. pulse frequency modulated voltage regulator as claimed in claim 6, wherein: from this inductive means transmit energy to this minimum time of this capacitive device along with absolute difference increase one of between this output voltage and this predetermined target voltage and prolong.
8. add right and require 6 pulse frequency modulated voltage regulator, wherein: this minimum time controller comprises:
One sets electric capacity, and
One sets current source, in order to this is set the electric capacity charging, increase to time that a predetermined reference voltage spent as this minimum time so that utilize to ride on from zero from this inductive means transmission energy to this capacitive device in one of these settings electric capacity the two poles of the earth potential difference (PD), and
This time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, the at least a portion that prevents this setting current source in response to this feedback signal transmits energy this minimum time to this capacitive device to this setting electric capacity charging so that prolong from this inductive means.
9. pulse frequency modulated voltage regulator as claimed in claim 8, wherein: this time lengthening circuit comprises:
One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and
One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, transmit energy this minimum time to this capacitive device by using this discharging electric current to prolong from this inductive means.
10. OFF time lengthening circuit, be used for a pulse frequency modulated voltage regulator, this pulse frequency modulated voltage regulator is changed a direct current voltage source and is become an output voltage by having one of predetermined minimal OFF time pulse frequency modulation switching signal, one of this output voltage flip-flop is a predetermined target voltage, and this OFF time lengthening circuit comprises:
One feedback signal, in order to indicate this output voltage, wherein when this output voltage equaled this predetermined target voltage, this feedback signal was an object feedback signal;
One first reference voltage, set for less than this object feedback signal: and
One first difference current is right, in order to determine one first discharging electric current based on absolute difference one of between this feedback signal and this first reference voltage, make when this feedback signal during, prolong the minimal OFF time that this is scheduled to by using this first discharging electric current less than this first reference voltage.
11. as the OFF time lengthening circuit of claim 10, wherein: when this feedback signal more was lower than this first reference voltage, this first discharging electric current was bigger.
12. OFF time lengthening circuit as claim 10, more comprise: one second reference voltage, set for less than this first reference voltage, and one second difference current right, in order to determine one second discharging electric current based on absolute difference one of between this feedback signal and this second reference voltage, make when this feedback signal during, first prolong the minimal OFF time that this is scheduled to this second discharging electric current by using this less than this second reference voltage.
13. OFF time lengthening circuit as claim 10, wherein: charging makes its potential difference (PD) determine from the zero predetermined time that voltage spent that increases to this predetermined minimal OFF time for an electric capacity by using a charging current, and this first discharging electric current is in order to reduce this charging current.
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CN1452307A (en) * 2002-04-16 2003-10-29 精工电子有限公司 Switch adjusting controlling circuit for modulation and control of pulse frequency

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