CN100403206C - Pulse frequency modulation type voltage regulator capable of extending minimum OFF time - Google Patents

Abstract

In a pulse frequency modulation (PFM) voltage regulator, a pulse frequency modulation switching controller is used to generate a pulse frequency modulation switching signal to convert a DC voltage source into an output voltage. A minimum OFF time controller provides a minimum OFF time for the pulse frequency modulation switching signal. In response to the output voltage, a feedback circuit generates a feedback signal. When the output voltage is lower than a predetermined target voltage, an OFF time extension circuit extends the minimum OFF time in response to the feedback signal. In other words, the OFF time extension circuit extends the time for transferring energy from the inductor to the capacitor. Therefore, when the pulse frequency modulation voltage regulator is operated under heavy load conditions, the ripple of the output voltage is effectively reduced.

Description

Pulse frequency modulated voltage regulator with extended minimum OFF time

technical field

The present invention relates to a pulse frequency modulated (Pulse Frequency Modulated, PFM) voltage regulator, in particular to a PFM voltage regulator that can extend the minimum OFF time, so as to reduce the output of the PFM voltage regulator under heavy load conditions voltage ripple.

Background technique

Typically, the voltage regulator adjusts the DC voltage source to an output voltage with a desired voltage level by properly controlling the duty cycle of the power switching transistor. According to actual application requirements, the voltage level of the adjusted output voltage must be greater than or lower than that of the original DC voltage source. Among the various methods used by the voltage regulator to control the duty cycle of the power switching transistor, the most common ones are the PFM switching control mode and the Pulse Width Modulated (PWM) switching control mode. The PFM voltage regulator uses a pulse with a fixed width to turn on the power switching transistor whenever the output voltage drops to the target voltage, so as to regulate the output voltage. On the other hand, the PWM voltage regulator controls the on and off of the power switching transistor through a rectangular wave with a predetermined duty cycle to achieve the effect of regulating the output voltage.

Whether it is a PFM voltage regulator or a PWM voltage regulator, neither can achieve satisfactory performance under light load conditions and heavy load conditions at the same time. Specifically, PFM voltage regulators suffer from excessive ripple in the output voltage under heavy load conditions. On the other hand, the PWM voltage regulator becomes an inefficient voltage regulator under light load conditions because the power consumption by the power switching transistor becomes relatively large relative to the output power.

U.S. Patent No. 5,568,044 and U.S. Patent No. 6,545,882 both disclose a PWM voltage regulator, which is characterized in that the original PWM control mode is changed to the PFM control mode under light load conditions by detecting the magnitude of the inductor current , to improve the efficiency of the PWM voltage regulator under light load conditions. However, these prior art voltage regulators require complicated PWM and PFM dual mode switching circuits.

In addition, US Patent No. 5,801,518 discloses a PFM voltage regulator, which is characterized in that the ON time of the power switching transistor is extended and/or the OFF time of the power switching transistor is shortened according to the degree of output voltage drop. According to the prior art, a longer ON time can store more energy in the inductor, and a shorter OFF time can prevent excessive discharge of the capacitor, thus improving the output ripple of the PFM voltage regulator under heavy load conditions. However, this prior art actually results in larger output ripple. Referring to the description in column 8, line 31 to line 35 of US Patent No. 5,801,518, this prior art assumes that after the energy stored in the inductor is supplied to the capacitor (that is, the moment the switching transistor is turned off), the PFM voltage regulation The output voltage of the device immediately rises to the maximum possible peak value and then decreases with the lapse of time. In practice, this assumption does not hold in a heavily loaded PFM voltage regulator, as will be explained in detail below. This is why US Patent No. 5,801,518 fails.

FIG. 1( a ) shows a circuit block diagram of a conventional PFM voltage regulator 10 . Referring to FIG. 1(a), when the power switching transistor Q (such as an NMOS transistor) is in the ON state, the potential of the node A is lower than the potential of the output terminal B (ie, the output voltage V _out ), so that the diode D is non-conductive. Therefore, the inductor L stores the energy supplied from the DC voltage source _Vin , causing the inductor current I _L to increase linearly. At this moment, the capacitor C discharges to supply the load current I _load , causing the output voltage V _out at the output terminal B to drop. When the power switching transistor O is in the OFF state, the energy previously stored in the inductor L is transferred to the capacitor C through the conduction diode D, so as to increase the output voltage V _out at the output terminal B.

Specifically, the PFM switching controller 11 generates a PFM switching signal 12 for controlling the switching on and off of the power switching transistor Q via the driver 13 . The PFM switching signal 12 is a pulse signal, wherein, for example, each pulse is used to turn on the power switching transistor Q, and the interval between adjacent pulses represents the time when the power switching transistor Q is turned off. The pulse width of the PFM switching signal 12 is a fixed value in principle, which is determined by the fixed ON time controller 14 . However, when the overcurrent protection circuit 15 detects that the inductor current I _L exceeds a predetermined current upper limit through the resistor R connected in series with the power switching transistor Q, the overcurrent protection circuit 15 will cause the PFM switching controller 11 to shorten the PFM switching signal 12 The pulse width. On the other hand, the interval between adjacent pulses of the PFM switching signal 12 is determined by the feedback circuit 16 . When the feedback circuit 16 detects that the output voltage V _out at the output terminal B is lower than the target voltage due to the discharge of the capacitor C, the feedback circuit 16 triggers the PFM switching controller 11 to output a pulse to turn on the power switching transistor Q. However, the interval between adjacent pulses cannot be smaller than the minimum OFF time determined by the minimum OFF time controller 17 .

FIG. 1( b ) shows a timing diagram of operating waveforms of the conventional PFM voltage regulator 10 shown in FIG. 1( a ) under heavy load conditions. In the period P1, when the output voltage V _out drops below the target voltage V _o (that is, the DC component of the output voltage V _out ), the PFM switching signal 12 enters a constant pulse width (or ON time) T _ON. The high level state H of _con makes the inductor current _IL increase linearly to store energy in the inductor L. It can be clearly seen from FIG. 1(b) that under heavy load conditions, the output voltage V _out drops considerably after the fixed ON time T _ON.com passes. After the fixed ON time T _ON.con , the PFM switching signal 12 enters the low level state L, and the energy stored in the inductor L is released to the capacitor C, so that the output voltage V _out rises. However, under heavy load conditions, the part of the inductor current I _L that can be used to charge the capacitor C is relatively small, so that the capacitor C cannot increase the output voltage V _out beyond the target after the minimum OFF time T _OFF.min is charged. voltage V _o . At this time, the PFM switching controller 11 makes the PFM switching signal 12 enter the high level state H with a constant ON time T _ON.com again. It can be clearly seen from Fig. 1(b) that within the minimum OFF time T _OFFmin , the energy stored in the inductor L is not completely released to the capacitor C as assumed in US Patent No. 5,801,518 (the inductor current I _L does not decrease to zero), causing the output voltage V _out to fail to rise to the maximum possible peak value. In this case, since the inductor current _IL continues to accumulate, the inductor current _IL finally exceeds the current upper limit I _max in the periods P2 and P3, forcing the fixed ON time T _ON.con of the PFM switching signal 12 to be shortened.

After the power switching transistor Q switches many times, when the power switching transistor Q is turned off again in period P3, the output voltage V _out finally exceeds the target voltage V _o . As a result, a large amount of energy continuously accumulated in the inductor L is completely discharged into the capacitor C, causing a very large output ripple. After a rather long OFF time, the output voltage V _out drops from the maximum value V _high to the target voltage V _o , so that the PFM switching signal 12 enters the high level state H of the fixed ON time T _ON.con , and the power is turned on again The transistor Q is switched to repeat the aforementioned operations. It can be clearly seen from FIG. 1( b ) that the output voltage V _out generated by the conventional PFM voltage regulator 10 has a rather large ripple 19 under heavy load conditions.

As mentioned above, since the energy transfer between the inductor L and the capacitor C cannot achieve good efficiency, the existing PFM voltage regulator 10 realizes a stable operation state from activation (that is, the output voltage V _out reaches the target voltage V _o ). The transition time taken will inevitably be lengthy.

Contents of the invention

In view of the aforementioned problems, an object of the present invention is to provide a PFM voltage regulator that can prolong the minimum OFF time so as to reduce the ripple of the output voltage under heavy load conditions.

Another object of the present invention is to provide a PFM voltage regulator that can prolong the minimum OFF time, and can efficiently operate not only under light load conditions but also under heavy load conditions.

It is still another object of the present invention to provide a PFM voltage regulator that can extend the minimum OFF time so as to shorten the transition time it takes from activation to achieve a stable operating state.

In a PFM voltage regulator, a PFM switching controller is used to generate a PFM switching signal to convert a DC voltage source into an output voltage. The minimum OFF time controller provides a minimum OFF time for the PFM switching signal. In response to the output voltage, a feedback circuit generates a feedback signal. When the output voltage is lower than a predetermined target voltage, the OFF time extension circuit extends the minimum OFF time in response to the feedback signal. Therefore, when the PFM voltage regulator operates under heavy load conditions, the ripple of the output voltage is effectively reduced.

Preferably, the minimum OFF time of the PFM switching signal is extended as the absolute value of the difference between the output voltage and the target voltage increases.

Preferably, the minimum OFF time controller includes: a capacitor, and a minimum OFF time setting current source for charging the capacitor so that a potential difference across the two poles of the capacitor increases from zero to a predetermined The time spent on the reference voltage serves as the predetermined minimum OFF time.

Preferably, the OFF time extension circuit includes: an extended reference voltage set to be smaller than a target feedback signal generated by the feedback circuit in response to the predetermined target voltage, and a differential current pair, It is used for determining a drain current based on the absolute value of the difference between the feedback signal and the extended reference voltage. When the feedback signal is less than the extended reference voltage, the predetermined minimum OFF time is extended by using the drain current.

According to another aspect of the present invention, a PFM voltage regulator includes an inductive device and a capacitive device. The inductive device is coupled to a DC voltage source. The capacitive device has an end coupled to the inductive device and provides an output voltage. A PFM switching controller generates a PFM switching signal to convert the DC voltage source into the output voltage. In response to the output voltage, a feedback circuit generates a feedback signal. A minimum time controller is coupled to the PFM switching controller for controlling a minimum time for transferring energy from the inductive device to the capacitive device. A time extension circuit extends the minimum time for transferring energy from the inductive device to the capacitive device in response to the feedback signal when the output voltage is lower than a predetermined target voltage.

Preferably, the minimum time for transferring energy from the inductive device to the capacitive device increases as the absolute value of the difference between the output voltage and the target voltage increases.

According to yet another aspect of the present invention, an OFF time extension circuit for a PFM voltage regulator is provided. The PFM voltage regulator converts a DC voltage source into an output voltage through a PFM switching signal with a predetermined minimum OFF time. A DC component of the DC voltage is a predetermined target voltage. A feedback signal indicates the output voltage. When the output voltage is equal to the predetermined target voltage, the feedback signal is called a target feedback signal. A first reference voltage is set to be smaller than the target feedback signal. A first differential current pair determines a first drain current based on the absolute value of the difference between the feedback signal and the first reference voltage. When the feedback signal is less than the first reference voltage, the predetermined minimum OFF time is extended by using the first drain current.

Preferably, when the feedback signal is lower than the first reference voltage, the first drain current is larger.

Preferably, the OFF time extension circuit further includes: a second reference voltage set to be smaller than the first reference voltage, and a second differential current pair for The absolute value of the difference determines a second drain current. When the feedback signal is less than the second reference voltage, the predetermined minimum OFF time is extended by using the first and the second drain currents.

Preferably, the predetermined minimum OFF time is determined by using a charging current to charge a capacitor so that the potential difference increases from zero to a predetermined voltage. Preferably, the first drain current is used to reduce the charging current.

Description of drawings

FIG. 1( a ) shows a circuit block diagram of a conventional PFM voltage regulator.

FIG. 1( b ) shows a timing diagram of operation waveforms of the conventional PFM voltage regulator shown in FIG. 1( a ) under heavy load conditions.

2(a) to 2(c) show schematic diagrams of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention.

3(a) and 3(b) show the timing diagrams of the operation of the PFM voltage regulator under heavy load conditions according to the present invention.

FIG. 4 shows a partial detailed circuit diagram of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention.

Explanation of reference signs:

10 Existing PFM voltage regulators

11 FM switching controller

12, 22 PFM switching signal

13 Drivers

14 Fixed ON time controller

15 Over-current protection circuit

16 Feedback circuit

17 Minimum OFF time controller

18 Feedback signal

19, 39 Ripple

21 OFF time extension circuit

31, 32 Transition Characteristics of Output Voltage from Active to Steady State

211～213 Drainage device

A node

B output endpoint

C, C _OFF capacitance

Comp Voltage Comparator

D diode

I _C.OFF charge current

I _L inductor current

I _load load current

I _OFF minimum OFF time setting current source

I _ref1 ～I _ret3 reference current

I _sk , I _sk1 ~ I _sk3 discharge current

L Inductance

N _1.1 ～N _3.3 NMOS transistors

P1～P3 cycle

P _1.1 ~P _3.2 PMOS transistors

Q Power Switching Transistor

R, R1, R2 resistors

S switch

T _OFF.min Minimum OFF time

T _ON.con fixed ON time

V _in DC voltage source

V _o target voltage

V _OFF OFF time reference voltage

V _out output voltage

V _ref1 ~ V _ref3 reference voltage

Detailed ways

The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Preferred embodiments according to the present invention will be described in detail with reference to the drawings.

In order to make the technical features of the present invention easier to understand, firstly, it is explained how the U.S. Patent No. 5,801,518 erroneously causes larger output ripple. Since the output voltage V _out drops greatly during the time when the power switching transistor Q is turned off (hereinafter referred to as OFF time) under heavy load conditions, this prior art believes that a shorter OFF time can be used to prevent the output voltage V _{out from} At the same time, a longer turn-on time of the power switching transistor Q (hereinafter referred to as ON time) is used to store more energy in the inductor L, and then replenish it to the capacitor C. However, as can be seen from Figure 1(b), once the output voltage V _out is lower than the target voltage V _o , a longer ON time will only cause the output voltage V _out to drop even lower and the inductor current _IL to become larger. Furthermore, the shorter OFF time makes it impossible for the energy stored in the inductor L to have enough time to be released to the capacitor C, which runs counter to the expected supplementary effect of the prior art.

2(a) to 2(c) show schematic diagrams of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention. Referring to Fig. 2 (a), the PFM voltage regulator according to the present invention is different from the PFM voltage regulator 10 shown in Fig. 1 (a) in that the PFM voltage regulator according to the present invention is additionally provided with an OFF time extension circuit 21, In order to achieve the purpose of reducing the output ripple. In order to understand the technical characteristics of the present invention more easily, only a part of the circuit of the PFM voltage regulator according to the present invention is shown in Fig. 2(a), and the remaining unshown circuit parts are the same as Fig. 1(a). Specifically, after monitoring the output voltage _Vout , the feedback circuit 16 not only inputs the feedback signal 18 to the PFM switching controller 11 , but also simultaneously inputs the feedback signal 18 to the OFF time extension circuit 21 . When the output voltage V _out is lower than the target voltage V _o , the OFF time extension circuit 21 makes the minimum OFF time T _OFF,min determined by the minimum OFF time controller 17 longer, so as to cause the PFM switching controller 11 to generate The PFM switching signal 22 of the minimum OFF time.

Specifically, the OFF time extension circuit 21 cooperates with the minimum OFF time controller 17 to determine the prolongable minimum OFF time T _OFF.min of the PFM switching signal 22 based on the output voltage V _out . For example, as shown in FIG. 2(b), the prolongable minimum OFF time T _OFF.min of the PFM switching signal 22 is a regional continuous decreasing function of the output voltage V _out , which can be expressed mathematically as T _{OFF .min} (V _out ). When the output voltage V _out is greater than or equal to the target voltage V _o , the prolongable minimum OFF time T _OFF.min is a minimum value T _OFF.min (V _o ). When the output voltage V _out is less than the target voltage V _o , the extendable minimum OF time T _OFF.min gradually increases as the absolute value of the difference between the output voltage V _out and the target voltage V _o increases. It should be noted that the present invention can also be applied to extendable minimum OFF time T _OFF.min as a stepwise (stepwise) decreasing function of the output voltage V _out or other suitable functions, as long as the extendable minimum OFF time T _OFF.min The functional relationship with the output voltage V _out can satisfy the following inequality (1):

T _OFF.min (V _out ＜V _o )＞T _OFF.min (V _out ＝V _o )＝T _OFF.min (V _out ＞V _o ) …(1)

Referring to Fig. 2(c), when the output voltage V _out is lower than the target voltage V _o , the OFF time of the existing PFM switching signal 12 is maintained at the minimum OFF time T _OFF.min (V _o ), regardless of the output voltage V _out . In contrast, in the PFM voltage regulator according to the present invention, when the output voltage V _out is lower than the target voltage V _o , the OFF time of the PFM switching signal 22 is determined according to the output voltage V _out and a minimum OFF time is extended. T _OFF.min (V _out <V _o ).

In the PFM voltage regulator according to the present invention, since the minimum OFF time T _OFF.min of the PFM switching signal 22 is extended, the energy stored in the inductor L can be transferred to the capacitor C in sufficient time to avoid the inductor current _IL accumulates continuously. In addition, because there is more time to transfer the energy stored in the inductor L to the capacitor C, the drop of the output voltage V _out is also slowed down. As a result, the ripple of the output voltage V _out is effectively reduced.

3(a) and 3(b) show the timing diagrams of the operation of the PFM voltage regulator under heavy load conditions according to the present invention. Referring to Fig. 3(a), when the output voltage V _out is lower than the target voltage V _o , the PFM voltage regulator according to the present invention only needs to perform one transistor switching to increase the output voltage V _out to be higher than the target voltage V _o , effectively Ground prevents the output voltage V _out from dropping significantly. In addition, since the inductor current _IL avoids continuous accumulation, its peak value I _peak will not exceed the current upper limit I _max and when the energy stored in the inductor L is released to the capacitor C during the OFF time, the output voltage V _out will not be generated Huge protruding waves. Comparing FIG. 3( a ) with FIG. 1( b ), it can be clearly found that the PFM voltage regulator according to the present invention effectively reduces the ripple 39 of the output voltage V _out under heavy load conditions.

In addition to the advantage of reducing the output ripple, the PFM voltage regulator according to the present invention also provides another additional advantage: shortening the time required for the PFM voltage regulator to achieve a stable operation state (that is, the output voltage V _out reaches the target voltage V _o ) from being activated. Transition time spent. Shown with reference to Fig. 3 (b), solid line 31 represents according to the PFM voltage regulator of the present invention from being activated to realize the output voltage V _out of the stable operating state change with time; Dotted line 32 then represents the existing PFM voltage regulator from The output voltage V _out that activates to achieve a stable operating state as a function of time. Because the PFM voltage regulator according to the present invention prolongs the minimum OFF time when the output voltage V _out is lower than the target voltage V _o , it is more efficient to transfer the energy stored in the inductor L to the capacitor C, avoiding the continuous current _{IL of} the inductor Accumulate and slow down the drop of the output voltage V _out . As a result, the output voltage V _out reaches the target voltage V _o more quickly.

It should be noted that although the foregoing embodiments are applied to a boost PFM voltage regulator, the present invention is not limited thereto but can be applied to a buck PFM voltage regulator, reducing output ripple and shortening the time from activation to steady state operation. Transition time spent. Moreover, although the foregoing embodiments are applied to a Discontinuous Mode PFM voltage regulator, the present invention is not limited thereto and can be applied to a Continuous Mode (Continuous Mode) PFM voltage regulator.

FIG. 4 shows a partial detailed circuit diagram of a PFM voltage regulator capable of extending the minimum OFF time according to the present invention. Referring to FIG. 4 , the minimum OFF time controller 17 uses the charging time ΔT _C required to make the potential difference across the two poles of the capacitor C _OFF from zero to a predetermined reference voltage to set the minimum OFF time T _OFF.min . Specifically, the minimum OFF time controller 17 includes a voltage comparator Comp, whose inverting terminal (marked with a reference symbol “-”) is coupled to the OFF time reference voltage V _OFF . The capacitor C _OFF is coupled between the non-inverting terminal of the voltage comparator Comp (indicated by the reference symbol “+”) and the ground, and is charged by the minimum OFF time setting current source I _OFF . The switch S is coupled between the charging path of the capacitor C _OFF and the ground.

The operation of the minimum OFF time controller 17 will be described as follows. Initially, the switch S is in a short-circuit state, so that the potential difference across the two poles of the capacitor C _OFF is zero. Because the potential of the non-inverting terminal is lower than the potential V _OFF of the inverting terminal, the output terminal of the voltage comparator Comp is at a low level. Once the switch S switches from the short-circuit state to the open-circuit state, the capacitor C _OFF starts to be charged by a charging current I _C.OFF , causing the potential of the non-inverting terminal of the voltage comparator Comp to rise. When the potential of the non-inverting terminal of the voltage comparator Comp rises higher than the OFF time reference voltage V _OFF , the output terminal of the voltage comparator Comp is inverted to a high level. The charging time ΔT _C required for the potential difference across the two poles of the capacitor C _OFF to reach the OFF time reference voltage V _OFF from zero can be expressed by the following equation (2):

ΔT _C ＝C _OFF ·(V _OFF /I _C.OFF ) …(2)

The minimum OFF time controller 17 uses the charging time ΔT _C as the minimum OFF time T _OFF.min .

In the present invention, the OFF time extension circuit 21 achieves the purpose of extending the charging time ΔT _C (that is, the minimum OFF time T _OFF.min ) by reducing the charging current I _C.OFF . Specifically, the OFF time extension circuit 21 includes three groups of current sinking (Current Sinking) devices 211 to 213, which respectively independently provide three sinking currents I _sk1 to I _sk3 , so as to conduct current sinking for the minimum OFF time setting current source I _OFF Emission function. The drain device 211 has two equal PMOS transistors P _1.1 and P _1.2 and two equal NMOS transistors N _1.1 and N _1.2 to form a differential current pair (Differential Current Pair). The sources of PMOS transistors P _1.1 and P _1.2 are coupled together, and a current source I _ref1 is supplied thereto. The gate and drain of NMOS transistor N _1.1 are coupled together and further coupled to the drain of PMOS transistor P _1.1 . The gate and drain of NMOS transistor N _1.2 are coupled together and further coupled to the drain of PMOS transistor P _1.2 . The reference voltage V _ref1 is used to control the gate of the PMOS transistor P _1.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P _1.2 . When the feedback signal 18 is greater than the reference voltage V _ref1 , the drain current of the PMOS transistor P _1.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V _ref1 , the drain current of the PMOS transistor P _1.2 is closer to the current source I _ref1 . Since an NMOS transistor N _1.3 is used to form a pair of current mirrors (Current Mirror,) together with the NMOS transistor N _1.2 , the drain current of the NMOS transistor N _1.3 is equal to the drain current of the NMOS transistor N _1.2 , that is, the PMOS transistor P _1.2 the drain current. The drain of the NMOS transistor N _1.3 is coupled to the charging path of the capacitor C _OFF , so that the drain current of the NMOS transistor N _1.3 serves as the discharge current I _sk1 .

The drain device 212 has two equal PMOS transistors P _2.1 and P _2.2 and two equal NMOS transistors N _2.1 and N _2.2 to form a differential current pair. The sources of PMOS transistors P _2.1 and P _2.2 are coupled together and a current source I _ref2 is supplied thereto. The gate and drain of NMOS transistor N _2.1 are coupled together and further coupled to the drain of PMOS transistor P _2.1 . The gate and drain of NMOS transistor N _2.2 are coupled together and further coupled to the drain of PMOS transistor P _2.2 . The reference voltage V _ref2 is used to control the gate of the PMOS transistor P _2.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P _2.2 . When the feedback signal 18 is greater than the reference voltage V _ref2 , the drain current of the PMOS transistor P _2.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V _ref2 , the drain current of the PMOS transistor P _2.2 is closer to the current source I _ref2 . Since an NMOS transistor N _2.3 is used to form a pair of current mirrors (Current Mirror,) together with the NMOS transistor N _2.2 , the drain current of the NMOS transistor N _2.3 is equal to the drain current of the NMOS transistor N _2.2 , that is, the PMOS transistor P _2.2 the drain current. The drain of the NMOS transistor N _2.3 is coupled to the charging path of the capacitor C _OFF , so that the drain current of the NMOS transistor N _2.3 serves as the discharge current I _sk2 .

The drain device 213 has two equal PMOS transistors P _3.1 and P _3.2 and two equal NMOS transistors N _3.1 and N _3.2 to form a differential current pair. The sources of PMOS transistors P _3.1 and P _3.2 are coupled together and a current source _ref3 is supplied thereto. The gate and drain of NMOS transistor N _3.1 are coupled together and further coupled to the drain of PMOS transistor P _3.1 . The gate and drain of NMOS transistor N _3.2 are coupled together and further coupled to the drain of PMOS transistor P _3.2 . The reference voltage V _ref3 is used to control the gate of the PMOS transistor P _3.1 ; and the feedback signal 18 from the feedback circuit 16 is used to control the gate of the PMOS transistor P _3.2 . When the feedback signal 18 is greater than the reference voltage V _ref3 , the drain current of the PMOS transistor P _3.2 is closer to zero. When the feedback signal 18 is smaller than the reference voltage V _ref3 , the drain current of the PMOS transistor P _3.2 is closer to the current source I _ref3 . Since an NMOS transistor N _3.3 is used to form a pair of current mirrors (Current Mirror) together with the NMOS transistor N _3.2 , the drain current of the NMOS transistor N _3.3 is equal to the drain current of the NMOS transistor N _3.2 , that is, the drain current of the PMOS transistor P _3.2 drain current. The drain of the NMOS transistor N _3.3 is coupled to the charging path of the capacitor C _OFF , so that the drain current of the NMOS transistor N _3.3 serves as the discharge current I _sk3 .

Therefore, the OFF time extension circuit 21 provides a total discharge current I _sk , which is the sum of the three discharge currents I _sk1 to I _sk3 . In this embodiment, the reference voltage V _ref1 is set to be greater than the reference voltage V _ref2 , and the reference voltage V _ref2 is set to be greater than the reference voltage V _ref3 . Therefore, when the feedback signal 18 is sufficiently smaller than the reference voltage V _ref1 , the total discharge current I _sk reaches a maximum value, which is the sum of the three current sources I _ref1 to I _ref3 . When the feedback signal 18 is sufficiently greater than the reference voltage V _ref1 , the total discharge current I _sk reaches a minimum value, ie, zero. Since the feedback signal 18 is used to indicate the output voltage V _out , for example, in this embodiment, the feedback signal 18 is the divided voltage V _out of the output voltage V _out [R2/(R1+R2)], so the total discharge current I _sk is One of the regionally continuously decreasing functions of the output voltage V _out . In order to make the OFF time extension circuit 21 start to discharge current for the minimum OFF time setting current source I _OFF when the output voltage V _out is lower than the target voltage V _o , the reference voltage V _ref1 must be set to be slightly lower than the target voltage V _o A divided voltage V _o ·[R2/(R1+R2)] generated by the feedback circuit 16 .

It can be clearly seen from FIG. 3 that since the OFF time extension circuit 21 provides a total discharge current I _sk , the charging current I _C.OFF of the capacitor C _OFF is shown in the following equation (3):

I _C.OFF ＝I _OFF -I _sk …(3)

Substitute Equation (3) into Equation (2), and straddle the capacitor C _OFF . The charging time ΔT _C required for the potential difference between the two poles to reach the OFF time reference voltage V _OFF from zero can be expressed by the following equation (4):

ΔT _C ＝C _OFF ·[V _OFF /(I _OFF -I _sk )] …(4)

As mentioned above, the minimum OFF time controller 17 uses the charging time ΔT _C as the minimum OFF time T _OFF.min and the total discharge current I _sk is a regional continuous decreasing function of the output voltage V _out , so the minimum OFF time T _OFF.min It is a regional continuous decreasing function of the output voltage V _out , as shown in Fig. 2(b).

It should be noted that although in the foregoing embodiment, the OFF time extension circuit 21 is provided with three sets of drainage devices 211 to 213, the present invention is not limited thereto and can be applied to the OFF time extension circuit 21 having three groups of drainage devices 211 to 213. At least one set of cases.

Although the present invention has been described by way of illustration of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (13)

1. pulse frequency modulated voltage regulator in order to convert a direct current voltage source to an output voltage, comprises:

One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;

One feedback circuit is in order to produce a feedback signal, in response to this output voltage;

One minimal OFF time controller is used for this pulse frequency modulation switching signal in order to a predetermined minimal OFF time to be provided: and

One OFF time lengthening circuit in order to when this output voltage is lower than a predetermined target voltage, prolongs this predetermined minimal OFF time, so that reduce the ripple of this output voltage in response to this feedback signal.

2. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulation switching signal should be predetermined minimal OFF time along with absolute difference increase one of between this output voltage and this target voltage and prolong.

3. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulated voltage regulator operates under the heavy duty condition, and this predetermined target voltage is one of this an output voltage flip-flop.

4. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this minimal OFF time controller comprises:

One electric capacity, and

One minimal OFF time is set current source, in order to this electric capacity charging, increases to time that a predetermined reference voltage spent as should predetermined minimal OFF time so that utilize to ride in one of these electric capacity the two poles of the earth potential difference (PD) from zero, and

This OFF time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, and at least a portion that prevents this minimal OFF time setting current source in response to this feedback signal is to this electric capacity charging, so that prolong this predetermined minimal OFF time.

5. pulse frequency modulated voltage regulator as claimed in claim 4, wherein: this OFF time lengthening circuit comprises:

One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and

One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, prolong this predetermined minimal OFF time by using this discharging electric current.

6. pulse frequency modulated voltage regulator comprises:

One inductive means is coupled in a direct current voltage source:

One capacitive device has an end points and is coupled in this inductive means and an output voltage is provided;

One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;

One feedback circuit is in order to produce a feedback signal, in response to this output voltage;

One minimum time controller is coupled in this modulation type change-over controller, in order in each cycle of controlling this pulse frequency modulation switching signal in order to transmit energy to one of this capacitive device minimum time from this inductive means; And

One time prolonged circuit, in order to when this output voltage is lower than a predetermined target voltage, prolonged this minimum time from this inductive means transmission energy to this capacitive device in response to this feedback signal.

7. pulse frequency modulated voltage regulator as claimed in claim 6, wherein: from this inductive means transmit energy to this minimum time of this capacitive device along with absolute difference increase one of between this output voltage and this predetermined target voltage and prolong.

8. add right and require 6 pulse frequency modulated voltage regulator, wherein: this minimum time controller comprises:

One sets electric capacity, and

One sets current source, in order to this is set the electric capacity charging, increase to time that a predetermined reference voltage spent as this minimum time so that utilize to ride on from zero from this inductive means transmission energy to this capacitive device in one of these settings electric capacity the two poles of the earth potential difference (PD), and

This time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, the at least a portion that prevents this setting current source in response to this feedback signal transmits energy this minimum time to this capacitive device to this setting electric capacity charging so that prolong from this inductive means.

9. pulse frequency modulated voltage regulator as claimed in claim 8, wherein: this time lengthening circuit comprises:

One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and

One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, transmit energy this minimum time to this capacitive device by using this discharging electric current to prolong from this inductive means.

10. OFF time lengthening circuit, be used for a pulse frequency modulated voltage regulator, this pulse frequency modulated voltage regulator is changed a direct current voltage source and is become an output voltage by having one of predetermined minimal OFF time pulse frequency modulation switching signal, one of this output voltage flip-flop is a predetermined target voltage, and this OFF time lengthening circuit comprises:

One feedback signal, in order to indicate this output voltage, wherein when this output voltage equaled this predetermined target voltage, this feedback signal was an object feedback signal;

One first reference voltage, set for less than this object feedback signal: and

One first difference current is right, in order to determine one first discharging electric current based on absolute difference one of between this feedback signal and this first reference voltage, make when this feedback signal during, prolong the minimal OFF time that this is scheduled to by using this first discharging electric current less than this first reference voltage.

11. as the OFF time lengthening circuit of claim 10, wherein: when this feedback signal more was lower than this first reference voltage, this first discharging electric current was bigger.

12. OFF time lengthening circuit as claim 10, more comprise: one second reference voltage, set for less than this first reference voltage, and one second difference current right, in order to determine one second discharging electric current based on absolute difference one of between this feedback signal and this second reference voltage, make when this feedback signal during, first prolong the minimal OFF time that this is scheduled to this second discharging electric current by using this less than this second reference voltage.

13. OFF time lengthening circuit as claim 10, wherein: charging makes its potential difference (PD) determine from the zero predetermined time that voltage spent that increases to this predetermined minimal OFF time for an electric capacity by using a charging current, and this first discharging electric current is in order to reduce this charging current.

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