CN100403206C - Pulse-frequency modulation type voltage regulator capable of extending least OFF time - Google Patents
Pulse-frequency modulation type voltage regulator capable of extending least OFF time Download PDFInfo
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- CN100403206C CN100403206C CNB2003101179379A CN200310117937A CN100403206C CN 100403206 C CN100403206 C CN 100403206C CN B2003101179379 A CNB2003101179379 A CN B2003101179379A CN 200310117937 A CN200310117937 A CN 200310117937A CN 100403206 C CN100403206 C CN 100403206C
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Abstract
In a pulse frequency modulation (PFM) voltage regulator, a pulse frequency modulation switching controller is used for generating a pulse frequency modulation switching signal for converting a direct current voltage source to an output voltage. A minimum OFF time controller provides the minimum OFF time for the pulse frequency modulation switching signal. In response to the output voltage, a feedback circuit generates a feedback signal. When an output voltage is lower than a preset target voltage, an OFF time expansion circuit is in response to the feedback signal, and the minimum OFF time is prolonged. In other word, the time for transmitting energy from an inductor to a capacitor is prolonged by the OFF time expansion circuit. Thus, when the pulse frequency modulation voltage regulator is operated in a heavy load condition, the ripple of the output voltage is effectively reduced.
Description
Technical field
The present invention relates to a kind of pulse frequency modulated (Pulse Frequency Modulated, PFM) voltage regulator, especially relate to a kind of PFM voltage regulator that prolongs minimal OFF time, so that be reduced in the ripple of the output voltage of the PFM voltage regulator under the heavy duty condition.
Background technology
On the typical case, voltage regulator is realized direct voltage source is adjusted to the output voltage with desired voltage level by the working cycle of power controlling switching transistor (Duty Cycle) suitably.According to demand in the practical application, it is accurate that the voltage level of the output voltage after the adjusting must be greater than or less than the position of original direct voltage source.In the variety of way of voltage regulator in order to the working cycle of power controlling switching transistor, modal have PFM switching controls pattern and pulse width modulation (Pulse Width Modulated, PWM) a switching controls pattern.The PFM voltage regulator promptly utilizes one to have the pulse conducting power switching transistor of fixed width, so that regulate output voltage when output voltage drops to target voltage.On the other hand, the PWM voltage regulator is the Push And Release of the square wave power controlling switching transistor by having a predetermined working cycle then, to realize regulating the effect of output voltage.
No matter be PFM voltage regulator or PWM voltage regulator, any one all can't all realize satisfactory performance simultaneously under light-load conditions and heavy duty condition.Particularly, the PFM voltage regulator suffers from the excessive shortcoming of ripple of output voltage under the heavy duty condition.On the other hand, the PWM voltage regulator because the power consumption that the power switching transistor causes becomes big relatively for output power, causes becoming the voltage regulator of a poor efficiency under light-load conditions.
United States Patent (USP) the 5th, 568, No. 044 and United States Patent (USP) the 6th, 545, all disclose a kind of No. 882: the PWM voltage regulator, it is characterized in that size, and under light-load conditions, original pwm pattern is changed into the PFM control model, to improve the efficient of PWM voltage regulator under light-load conditions by the detecting inductive current.Yet the voltage regulator of these prior aries needs complicated PWM and PFM double-mode commutation circuit.
In addition, United States Patent (USP) the 5th, 801 discloses a kind of PFM voltage regulator No. 518, it is characterized in that the degree that descends according to output voltage, the ON time that prolongs the power switching transistor also/or shorten OFF time of power switching transistor.This prior art thinks that the longer ON time can store more energy in inductance, and the shorter OFF time can prevent the electric capacity over-discharge can simultaneously, therefore can improve the output ripple of PFM voltage regulator under the heavy duty condition.Yet this prior art causes bigger output ripple in fact on the contrary.With reference to United States Patent (USP) the 5th, 801, the 8th hurdle the 31st walks to the description of the 35th row in No. 518 instructionss, after the energy of this prior art hypothesis in being stored in inductance is supplied to electric capacity (that is switching transistor close moment), the output voltage of PFM voltage regulator rises to the peak value of maximum possible at once, descends by the time passage subsequently.In fact, this hypothesis also can't be set up in heavy duty PFM voltage regulator, hereinafter detailed description will be arranged.This is a United States Patent (USP) the 5th, 801, the reason of No. 518 failures.
Fig. 1 (a) shows the circuit blocks figure of existing P FM voltage regulator 10.With reference to Fig. 1 (a), as power switching transistor Q (for example nmos pass transistor) when being in the ON state, the current potential of node A is lower than current potential (that is the output voltage V of exit point B
Out), make not conducting of diode D.Thereby inductance L stores from direct voltage source V
InThe energy of being supplied causes inductive current I
LLinear increasing.At this moment, capacitor C is discharged with supply load current I
Load, cause the output voltage V at exit point B place
OutDescend.When power switching transistor O was in the OFF state, the previous stored energy of inductance L promptly was sent to capacitor C via the diode D of conducting, to improve the output voltage V at exit point B place
Out
Particularly, PFM switch controller 11 produces a PFM switching signal 12, in order to the Push And Release via driver 13 power controlling switching transistor Q.PFM switching signal 12 is a pulse signal, and wherein each pulse for example must be in order to conducting power switching transistor Q, and between between adjacent pulse every the time of promptly representing power switching transistor Q to close.The pulse width of PFM switching signal 12 is a fixing value in principle, and it is determined by fixing ON time controller 14.Yet, when circuit overcurrent protection 15 detects inductive current I via the resistance R that is series at power switching transistor Q
LSurpass on the predetermined current and prescribe a time limit, circuit overcurrent protection 15 can make PFM switch controller 11 shorten the pulse width of PFM switching signals 12.On the other hand, between between the adjacent pulse of PFM switching signal 12 every then being determined by feedback circuit 16.Detect the output voltage V at exit point B place when feedback circuit 16
OutWhen being lower than target voltage because of the capacitor C discharge, feedback circuit 16 triggers PFM switch controller 11 outputs one pulse with conducting power switching transistor Q.Yet, between adjacent pulse between every can not be less than the minimal OFF time that is determined by minimal OFF time controller 17.
The operation waveform sequential chart of existing PFM voltage regulator 10 under the heavy duty condition shown in Fig. 1 (b) displayed map 1 (a).In cycle P1, work as output voltage V
OutDrop to and be lower than target voltage V
o(that is output voltage V
OutFlip-flop) time, PFM switching signal 12 enters and has a fixed pulse width (or claiming ON time) T
ON.conHigh levels state H, make inductive current I
LLinear increasing with storage power in inductance L.Can know from Fig. 1 (b) and to see, under the heavy duty condition, output voltage V
OutIn fixing ON time T
ON.comDegree through being descended later is quite big.Crossed fixedly ON time T
ON.conAfter, PFM switching signal 12 enters low level state L, and the energy that is stored in the inductance L is released into capacitor C, makes output voltage V
OutRise.Yet, under the heavy duty condition, inductive current I
LIn can be used for the part of capacitor C charging is diminished relatively, cause capacitor C through minimal OFF time T
OFF.minCharging after still can't make output voltage V
OutIncrease and surpass target voltage V
oAt this moment, PFM switch controller 11 enters PFM switching signal 12 to have a fixing ON time T once more
ON.comHigh levels state H.Can know from Fig. 1 (b) and to see, at minimal OFF time T
OFFminIn, be stored in the energy in the inductance L and fail as United States Patent (USP) the 5th, 801 No. 518 capacitor C (the inductive current I that are released into fully hypothetically
LBe not reduced to zero), cause output voltage V
OutCan't rise to the peak value of maximum possible.In the case, because inductive current I
LAccumulation constantly, inductive current I
LIn cycle P2 and P3, surpass upper current limit I finally
Max, force the fixedly ON time T of PFM switching signal 12
ON.conBe shortened.
After power switching transistor Q is through switching many times, when power switching transistor Q closes once more among the cycle P3, output voltage V
OutFinally surpass target voltage V
oAs a result, the big energy that accumulates on continuously in the inductance L all is released in the capacitor C, causes a very large output ripple.Through a quite long OFF after the time, output voltage V
OutJust from maximal value V
High, drop to target voltage V
o, make PFM switching signal 12 enter fixedly ON time T
ON.conHigh levels state H, conducting power switching transistor Q is to repeat aforementioned operation again.Can know from Fig. 1 (b) and see the output voltage V that existing P FM voltage regulator 10 is produced under the heavy duty condition
OutHas a sizable ripple 19.
As previously mentioned,, the energy between inductance L and capacitor C can't realize good efficiency, so existing P FM voltage regulator 10 is realized steady state operation (that is output voltage V from being activated to because transmitting
OutReach target voltage V
o) transit time of being spent is tediously long unavoidablely.
Summary of the invention
Because foregoing problems, one of the present invention purpose is to provide a kind of PFM voltage regulator, can prolong minimal OFF time, so that be reduced in the ripple of output voltage under the heavy duty condition.
Another object of the present invention is to provide a kind of PFM voltage regulator, can prolong minimal OFF time, not only can operate in efficiently under the light-load conditions also can operate in efficiently under the heavy duty condition.
The present invention's another purpose is to provide a kind of PFM voltage regulator, can prolong minimal OFF time, so that shorten the transit time of realizing that from being activated to steady state operation spent.
In the PFM voltage regulator, use the PFM switch controller to produce the PFM switching signal and come the conversion dc voltage source to become output voltage.The minimal OFF time controller provides a minimal OFF time to be used for the PFM switching signal.In response to this output voltage, feedback circuit produces feedback signal.When output voltage was lower than a predetermined target voltage, OFF time lengthening circuit prolonged this minimal OFF time in response to this feedback signal.Thereby when the PFM voltage regulator operates in heavy duty condition following time, the ripple of output voltage reduces effectively.
Preferably, the minimal OFF time of PFM switching signal increases and prolongs along with the absolute difference between output voltage and target voltage.
Preferably, this minimal OFF time controller comprises: an electric capacity, and one minimal OFF time set current source, in order to the charging of this electric capacity, increase to time that a predetermined reference voltage spent as should predetermined minimal OFF time from zero so that utilize to ride in one of these electric capacity the two poles of the earth potential difference (PD).
Preferably, this OFF time lengthening circuit comprises: one prolongs reference voltage, set for less than an object feedback signal, this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and one difference current right, in order to determine a drainage current based on the absolute difference between this feedback signal and this prolongation reference voltage.When this feedback signal prolongs reference voltage less than this, prolong this predetermined minimal OFF time by using this drainage current.
According to another aspect of the present invention, the PFM voltage regulator comprises an inductive means and a capacitive device.This inductive means is coupled in a direct current voltage source.This capacitive device has an end points and is coupled in this inductive means and an output voltage is provided.One PFM switch controller produces a PFM switching signal and changes this direct voltage source and become this output voltage.In response to this output voltage, a feedback circuit produces a feedback signal.One minimum time controller is coupled in this PFM switch controller, transmits energy to one of this capacitive device minimum time in order to control from this inductive means.When this output voltage was lower than a predetermined target voltage, time prolongation circuit prolonged this minimum time from this inductive means transmission energy to this capacitive device in response to this feedback signal.
Preferably, this minimum time from this inductive means transmission energy to this capacitive device is along with this absolute difference between this output voltage and this target voltage increases and prolongs.
According to the present invention's another aspect, a kind of OFF time lengthening circuit is provided, be used for a PFM voltage regulator.This PFM voltage regulator is changed a direct current voltage source and is become an output voltage by having one of predetermined minimal OFF time PFM switching signal.One of this DC voltage flip-flop is a predetermined target voltage.One feedback signal is indicated this output voltage.When this output voltage equaled this predetermined target voltage, this feedback signal was called an object feedback signal.One first reference voltage is set for less than this object feedback signal.One first difference current is to determining one first drainage current based on the absolute difference between this feedback signal and this first reference voltage.When this feedback signal during, prolong this predetermined minimal OFF time by using this first drainage current less than this first reference voltage.
Preferably, when this feedback signal more was lower than this first reference voltage, this first drainage current was bigger.
Preferably, OFF time lengthening circuit more comprises: one second reference voltage, set for less than this first reference voltage, and one second difference current is right, in order to determine one second drainage current based on the absolute difference between this feedback signal and this second reference voltage.When this feedback signal during, first prolong this predetermined minimal OFF time with this second drainage current by using this less than this second reference voltage.
Preferably, this predetermined minimal OFF time is that charging makes its potential difference (PD) determine from the zero predetermined time that voltage spent that increases to for an electric capacity by using a charging current.Preferably, this first drainage current is in order to reduce this charging current.
Description of drawings
Fig. 1 (a) shows the circuit blocks figure of existing P FM voltage regulator.
The operation waveform sequential chart of existing PFM voltage regulator under the heavy duty condition shown in Fig. 1 (b) displayed map 1 (a).
Fig. 2 (a) is to the synoptic diagram of 2 (c) demonstration according to the present invention's the PFM voltage regulator that can prolong minimal OFF time.
Fig. 3 (a) and PFM voltage regulator the time sequential routine figure in heavy duty condition under of 3 (b) demonstration according to the present invention.
Fig. 4 shows the part detailed circuit diagram according to the present invention's the PFM voltage regulator that can prolong minimal OFF time.
Description of reference numerals:
10 existing P FM voltage regulators
11 FM switch controllers
12,22 PFM switching signals
13 drivers
14 fixing ON time controllers
15 circuit overcurrent protections
16 feedback circuits
17 minimal OFF time controllers
18 feedback signals
19,39 ripples
21 OFF time lengthening circuit
31,32 output voltages are from activating the Interim to steady state (SS)
211～213 drain means
The A node
The B exit point
C, C
OFFElectric capacity
The Comp voltage comparator
The D diode
I
C.OFFCharging current
I
LInductive current
I
LoadLoad current
I
OFFMinimal OFF time is set current source
I
Ref1～I
Ret3Reference current
I
Sk, I
Sk1～I
Sk3The discharging electric current
The L inductance
N
1.1～N
3.3Nmos pass transistor
P1～P3 cycle
P
1.1～P
3.2The PMOS transistor
Q power switching transistor
R, R1, R2 resistance
The S switch
T
OFF.minMinimal OFF time
T
ON.conFixing ON time
V
InDirect voltage source
V
oTarget voltage
V
OFFOFF time reference voltage
V
OutOutput voltage
V
Ref1～V
Ref3Reference voltage
Embodiment
Explanation hereinafter and accompanying drawing will be stated and other purpose, feature, more obvious with advantage before will making the present invention.Now with reference to the preferred embodiment of graphic detailed description according to the present invention.
Understand for the easier quilt of the technical characterictic that makes the present invention, United States Patent (USP) the 5th, 801 at first is described, how to cause bigger output ripple mistakenly No. 518.Because output voltage V under the heavy duty condition
OutThe degree that descends in the time (hereinafter referred is the OFF time) that power switching transistor Q closes is bigger, and this prior art is thought and can be utilized the shorter OFF time to prevent output voltage V
OutReduce, utilize the time (hereinafter referred is the ON time) of longer power switching transistor Q conducting to store more energy in inductance L simultaneously, be supplemented to capacitor C subsequently.Yet, from Fig. 1 (b) as can be known, in case output voltage V
OutBe lower than target voltage V
o, the longer ON time only can cause output voltage V
OutUnder be even lower, and make inductive current I
LBecome bigger.Moreover the shorter OFF time makes that be stored in energy in the inductance L more can't obtain time enough and be released into capacitor C, and the supplementary result of being in harmony with the original desired realization of prior art runs in the opposite direction.
Fig. 2 (a) is to the synoptic diagram of 2 (c) demonstration according to the present invention's the PFM voltage regulator that can prolong minimal OFF time.With reference to Fig. 2 (a), PFM voltage regulator and PFM voltage regulator 10 differences shown in Fig. 1 (a) according to the present invention are additionally to be provided with an OFF time lengthening circuit 21 according to the present invention's PFM voltage regulator, so that realize reducing the purpose of output ripple.In order to be easier to understand the present invention's technical characterictic, only show circuit among Fig. 2 (a) according to the part of the present invention's PFM voltage regulator, identical as for all the other circuit parts that do not show with Fig. 1 (a).Particularly, feedback circuit 16 is in supervising output voltage
VoutAfter, except with the feedback signal 18 input PFM switch controllers 11, also simultaneously feedback signal 18 is inputed to OFF time lengthening circuit 21.Work as output voltage V
OutBe lower than target voltage V
oThe time, OFF time lengthening circuit 21 makes the minimal OFF time T that is determined by minimal OFF time controller 17
OFF, minElongated, so that cause PFM switch controller 11 to produce PFM switching signal 22 with the minimal OFF time that is extended.
Particularly, OFF time lengthening circuit 21 is cooperated with minimal OFF time controller 17, in order to based on output voltage V
OutAnd the extensible minimal OFF time T of decision PFM switching signal 22
OFF.minFor example, shown in Fig. 2 (b), the extensible minimal OFF time T of PFM switching signal 22
OFF.minMust be output voltage V
OutOne of regional decreasing function continuously, on mathematics, can be expressed as T
OFF.min(V
Out).Work as output voltage V
OutMore than or equal to target voltage V
oThe time, extensible minimal OFF time T
OFF.minBe a minimum value T
OFF.min(V
o).Work as output voltage V
OutLess than target voltage V
oThe time, extensible minimum OF time T
OFF.minAlong with output voltage V
OutWith target voltage V
oBetween absolute difference increase and increase gradually.Should notice that the present invention also must be applied to extensible minimal OFF time T
OFF.minBe output voltage V
OutOne of staged (stepwise) decreasing function or other suitable function, as long as extensible minimal OFF time T
OFF.minWith output voltage V
OutBetween funtcional relationship satisfy following inequality (1) and get final product:
T
OFF.min(V
out＜V
o)＞T
OFF.min(V
out＝V
o)＝T
OFF.min(V
out＞V
o) …(1)
With reference to Fig. 2 (c), work as output voltage V
OutBe lower than target voltage V
oThe time, the OFF time dimension of existing P FM switching signal 12 is held in minimal OFF time T
OFF.min(V
o), output voltage V no matter
OutWhy.Under the contrast, in foundation the present invention's PFM voltage regulator, work as output voltage V
OutBe lower than target voltage V
oThe time, the OFF time of PFM switching signal 22 is according to output voltage V
OutAnd the minimal OFF time T that one of decision is extended
OFF.min(V
Out＜V
o).
In foundation the present invention's PFM voltage regulator, because the minimal OFF time T of PFM switching signal 22
OFF.minBe extended, obtain more fully that the time is sent in the capacitor C, avoid inductive current I so be stored in energy in the inductance L
LAccumulation constantly.In addition, the time is transmitted the stored energy of inductance L to capacitor C, output voltage V more fully owing to having
OutUnder the degree of falling therefore also slow down.As a result, output voltage V
OutRipple reduce effectively.
Fig. 3 (a) and PFM voltage regulator the time sequential routine figure in heavy duty condition under of 3 (b) demonstration according to the present invention.With reference to Fig. 3 (a), work as output voltage V
OutBe lower than target voltage V
oThe time, only need carry out a transistor according to the present invention's PFM voltage regulator and switch and can make output voltage V
OutBe promoted to greater than target voltage V
o, prevent output voltage V effectively
OutDescend significantly.In addition, because inductive current I
LAvoid accumulating constantly, so its peak I
PeakCan not surpass upper current limit I
MaxAnd when the energy in being stored in inductance L is released into capacitor C in OFF in the time, output voltage V
OutCan not produce huge projection waveform.Comparison diagram 3 (a) and Fig. 1 (b) can know discovery, reduce output voltage V effectively according to the present invention's PFM voltage regulator under the heavy duty condition
OutRipple 39.
Except the advantage that reduces output ripple, also additionally provide another advantage according to the present invention's PFM voltage regulator: shorten the PFM voltage regulator and realize steady state operation (that is output voltage V from being activated to
OutReach target voltage V
o) transit time of being spent.Shown in Fig. 3 (b), solid line 31 representative according to the present invention's PFM voltage regulator from being activated to the output voltage V that realizes steady state operation
OutVariation in time; 32 in dotted line represents existing P FM voltage regulator from being activated to the output voltage V that realizes steady state operation
OutVariation in time.Because according to the present invention's PFM voltage regulator in output voltage V
OutBe lower than target voltage V
oThe Shi Yanchang minimal OFF time, thus transmit more efficiently the stored energy of inductance L to capacitor C, avoid inductive current I
LAccumulation and slow down output voltage V constantly
OutUnder degree is fallen.As a result, output voltage V
OutMore promptly reach target voltage V
o
Be applied to the PFM Boost voltage regulator though should note the described embodiment of preamble, the invention is not restricted to this and must be applied to buck PFM voltage regulator, reduce output ripple and shorten the transit time of realizing that from being activated to steady state operation spent.Moreover, though the described embodiment of preamble is applied to discontinuous mode (Discontinuous Mode) PFM voltage regulator, the invention is not restricted to this and must be applied to continuous mode (ContinuousMode) PFM voltage regulator.
Fig. 4 shows the part detailed circuit diagram according to the present invention's the PFM voltage regulator that can prolong minimal OFF time.With reference to Fig. 4, minimal OFF time controller 17 utilizes to make and rides in capacitor C
OFFThe potential difference (PD) at the two poles of the earth is from the zero duration of charging Δ T that reaches the required cost of a predetermined reference voltage
CSet minimal OFF time T
OFF.minParticularly, minimal OFF time controller 17 comprises a voltage comparator Comp, and its end of oppisite phase (indicating with reference symbol "-") then is coupled in OFF time reference voltage V
OFFCapacitor C
OFFBe coupled between the non-oppisite phase end (indicating) and ground of voltage comparator Comp, and be subjected to minimal OFF time setting current source I with reference symbol "+"
OFFCharging.Switch S is coupled in capacitor C
OFFBetween charge path and ground.
The operation that minimal OFF time controller 17 will be described now is as follows.Originally, switch S is in short-circuit condition, makes to ride in capacitor C
OFFThe potential difference (PD) at the two poles of the earth is zero.Because the current potential of non-oppisite phase end is lower than the current potential V of end of oppisite phase
OFF, the output terminal of voltage comparator Comp is positioned at low level.In case switch S switches to open-circuit condition from short-circuit condition, capacitor C
OFFBeginning is by a charging current I
C.OFFCharging causes the current potential of the non-oppisite phase end of voltage comparator Comp to rise.When the current potential of the non-oppisite phase end of voltage comparator Comp rises to greater than OFF time reference voltage V
OFFThe time, the output terminal of voltage comparator Comp is inverted into high levels.Ride in capacitor C
OFFThe potential difference (PD) at the two poles of the earth reaches OFF time reference voltage V from zero
OFFThe duration of charging Δ T of required cost
CCan represent by following equation (2):
ΔT
C＝C
OFF·(V
OFF/I
C.OFF) …(2)
Minimal OFF time controller 17 promptly utilizes duration of charging Δ T
CAs minimal OFF time T
OFF.min
In the present invention, OFF time lengthening circuit 21 is by reducing charging current I
C.OFFAnd realization prolongs duration of charging Δ T
C(that is minimal OFF time T
OFF.min) purpose.Particularly, OFF time lengthening circuit 21 comprises three groups of current drainages (Current Sinking) device 211 to 213, and three discharging electric current I are provided respectively independently
Sk1To I
Sk3, so that minimal OFF time is set current source I
OFFCarry out the function of current drain.Drain means 211 has two equal PMOS transistor P
1.1With P
1.2The nmos pass transistor N that equates with two
1.1With N
1.2, form a difference current jointly to (Differential Current Pair).PMOS transistor P
1.1With P
1.2Source-coupled in together, an and current source I
Ref1Be supplied on it.Nmos pass transistor N
1.1Grid with drain coupled in, and more be coupled in PMOS transistor P
1.1Drain electrode.Nmos pass transistor N
1.2Grid with drain coupled in, and more be coupled in PMOS transistor P
1.2Drain electrode.Reference voltage V
Ref1In order to control PMOS transistor P
1.1Grid: the feedback signal 18 of coming from feedback circuit 16 is then in order to control PMOS transistor P
1.2Grid.When feedback signal 18 heals greater than reference voltage V
Ref1The time, PMOS transistor P
1.2Drain current more near zero.When feedback signal 18 heals less than reference voltage V
Ref1The time, PMOS transistor P
1.2Drain current more near current source I
Ref1Owing to use a nmos pass transistor N
1.3Come and nmos pass transistor N
1.2So the common a pair of current mirror (Current Mirror) that forms is nmos pass transistor N
1.3Drain current equal nmos pass transistor N
1.2Drain current, that is PMOS transistor P
1.2Drain current.Nmos pass transistor N
1.3Drain coupled in capacitor C
OFFCharge path so that nmos pass transistor N
1.3Drain current as the discharging electric current I
Sk1
Drain means 212 has two equal PMOS transistor P
2.1With P
2.2The nmos pass transistor N that equates with two
2.1With N
2.2, it is right to form a difference current jointly.PMOS transistor P
2.1With P
2.2Source-coupled in together, an and current source I
Ref2Be supplied on it.Nmos pass transistor N
2.1Grid with drain coupled in, and more be coupled in PMOS transistor P
2.1Drain electrode.Nmos pass transistor N
2.2Grid with drain coupled in, and more be coupled in PMOS transistor P
2.2Drain electrode.Reference voltage V
Ref2In order to control PMOS transistor P
2.1Grid: the feedback signal 18 of coming from feedback circuit 16 is then in order to control PMOS transistor P
2.2Grid.When feedback signal 18 heals greater than reference voltage V
Ref2The time, PMOS transistor P
2.2Drain current more near zero.When feedback signal 18 heals less than reference voltage V
Ref2The time, PMOS transistor P
2.2Drain current more near current source I
Ref2Owing to use a nmos pass transistor N
2.3Come and nmos pass transistor N
2.2So the common a pair of current mirror (Current Mirror) that forms is nmos pass transistor N
2.3Drain current equal nmos pass transistor N
2.2Drain current, that is PMOS transistor P
2.2Drain current.Nmos pass transistor N
2.3Drain coupled in capacitor C
OFFCharge path so that nmos pass transistor N
2.3Drain current as the discharging electric current I
Sk2
Drain means 213 has two equal PMOS transistor P
3.1With P
3.2The nmos pass transistor N that equates with two
3.1With N
3.2, it is right to form a difference current jointly.PMOS transistor P
3.1With P
3.2Source-coupled in together, an and current source r
Ef3Be supplied on it.Nmos pass transistor N
3.1Grid with drain coupled in, and more be coupled in PMOS transistor P
3.1Drain electrode.Nmos pass transistor N
3.2Grid with drain coupled in, and more be coupled in PMOS transistor P
3.2Drain electrode.Reference voltage V
Ref3In order to control PMOS transistor P
3.1Grid; The feedback signal 18 of coming from feedback circuit 16 is then in order to control PMOS transistor P
3.2Grid.When feedback signal 18 heals greater than reference voltage V
Ref3The time, PMOS transistor P
3.2Drain current more near zero.When feedback signal 18 heals less than reference voltage V
Ref3The time, PMOS transistor P
3.2Drain current more near current source I
Ref3Owing to use a nmos pass transistor N
3.3Come and nmos pass transistor N
3.2So the common a pair of current mirror (Current Mirror) that forms is nmos pass transistor N
3.3Drain current equal nmos pass transistor N
3.2Drain current, that is PMOS transistor P
3.2Drain current.Nmos pass transistor N
3.3Drain coupled in capacitor C
OFFCharge path so that nmos pass transistor N
3.3Drain current as the discharging electric current I
Sk3
Therefore, OFF time lengthening circuit 21 provides a total discharging electric current I
Sk, it is three discharging electric current I
Sk1To I
Sk3Sum.In the present embodiment, reference voltage V
Ref1Set for greater than reference voltage V
Ref2, and reference voltage V
Ref2Set for greater than reference voltage V
Ref3Therefore, when feedback signal 18 enough less than reference voltage V
Ref1The time, always discharge electric current I
SkReach a maximal value, it is three current source I
Ref1To I
Ref3Sum.When feedback signal 18 is sufficiently more than reference voltage V
Ref1The time, always discharge electric current I
SkReach a minimum value, that is zero.Because feedback signal 18 is in order to indicate output voltage V
Out, for example feedback signal 18 is an output voltage V in the present embodiment
OutDividing potential drop V
Out[R2/ (R1+R2)] is so total discharging electric current I
SkBe output voltage V
OutOne of regional decreasing function continuously.In order to make OFF time lengthening circuit 21 in output voltage V
OutLess than target voltage V
oIn time, begin to set current source I for minimal OFF time
OFFCarry out the effect of current drain, reference voltage V
Ref1Must set for slightly less than by target voltage V
oThe dividing potential drop V that process feedback circuit 16 is produced
o[R2/ (R1+R2)].
Clearly visible from Fig. 3, because OFF time lengthening circuit 21 provides a total discharging electric current I
SkSo, capacitor C
OFFCharging current I
C.OFFShown in following equation (3):
I
C.OFF＝I
OFF-I
sk …(3)
With equation (3) substitution equation (2), ride in capacitor C
OFF. the potential difference (PD) at the two poles of the earth reaches OFF time reference voltage V from zero
OFFThe duration of charging Δ T of required cost
CCan represent by following equation (4):
ΔT
C＝C
OFF·[V
OFF/(I
OFF-I
sk)] …(4)
As previously mentioned, minimal OFF time controller 17 utilizes duration of charging Δ T
CAs minimal OFF time T
OFF.minAnd always discharge electric current I
SkBe output voltage V
OutThe continuous decreasing function of regionality, so minimal OFF time T
OFF.minBe output voltage V
OutThe continuous decreasing function of regionality, shown in Fig. 2 (b).
Though should note in the aforementioned embodiment, OFF time lengthening circuit 21 is provided with three groups of drain means 211 to 213, the invention is not restricted to this and must be applied to OFF time lengthening circuit 21 have at least one group situation in three groups of drain means 211 to 213.
Though the present invention was illustrated as illustration by preferred embodiment already, the person of should be appreciated that is: the invention is not restricted to the embodiment that this is disclosed.On the contrary, this invention is intended to contain genus tangible various modifications and similar configuration for the personage who has the knack of this skill.Therefore, the scope of claim should be according to the widest annotation, and this type of is revised and similar configuration to contain all.
Claims (13)
1. pulse frequency modulated voltage regulator in order to convert a direct current voltage source to an output voltage, comprises:
One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;
One feedback circuit is in order to produce a feedback signal, in response to this output voltage;
One minimal OFF time controller is used for this pulse frequency modulation switching signal in order to a predetermined minimal OFF time to be provided: and
One OFF time lengthening circuit in order to when this output voltage is lower than a predetermined target voltage, prolongs this predetermined minimal OFF time, so that reduce the ripple of this output voltage in response to this feedback signal.
2. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulation switching signal should be predetermined minimal OFF time along with absolute difference increase one of between this output voltage and this target voltage and prolong.
3. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this pulse frequency modulated voltage regulator operates under the heavy duty condition, and this predetermined target voltage is one of this an output voltage flip-flop.
4. pulse frequency modulated voltage regulator as claimed in claim 1, wherein: this minimal OFF time controller comprises:
One electric capacity, and
One minimal OFF time is set current source, in order to this electric capacity charging, increases to time that a predetermined reference voltage spent as should predetermined minimal OFF time so that utilize to ride in one of these electric capacity the two poles of the earth potential difference (PD) from zero, and
This OFF time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, and at least a portion that prevents this minimal OFF time setting current source in response to this feedback signal is to this electric capacity charging, so that prolong this predetermined minimal OFF time.
5. pulse frequency modulated voltage regulator as claimed in claim 4, wherein: this OFF time lengthening circuit comprises:
One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and
One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, prolong this predetermined minimal OFF time by using this discharging electric current.
6. pulse frequency modulated voltage regulator comprises:
One inductive means is coupled in a direct current voltage source:
One capacitive device has an end points and is coupled in this inductive means and an output voltage is provided;
One modulation type change-over controller is changed this direct voltage source and is become this output voltage in order to produce a pulse frequency modulation switching signal;
One feedback circuit is in order to produce a feedback signal, in response to this output voltage;
One minimum time controller is coupled in this modulation type change-over controller, in order in each cycle of controlling this pulse frequency modulation switching signal in order to transmit energy to one of this capacitive device minimum time from this inductive means; And
One time prolonged circuit, in order to when this output voltage is lower than a predetermined target voltage, prolonged this minimum time from this inductive means transmission energy to this capacitive device in response to this feedback signal.
7. pulse frequency modulated voltage regulator as claimed in claim 6, wherein: from this inductive means transmit energy to this minimum time of this capacitive device along with absolute difference increase one of between this output voltage and this predetermined target voltage and prolong.
8. add right and require 6 pulse frequency modulated voltage regulator, wherein: this minimum time controller comprises:
One sets electric capacity, and
One sets current source, in order to this is set the electric capacity charging, increase to time that a predetermined reference voltage spent as this minimum time so that utilize to ride on from zero from this inductive means transmission energy to this capacitive device in one of these settings electric capacity the two poles of the earth potential difference (PD), and
This time lengthening circuit is in order to when this output voltage is lower than this predetermined target voltage, the at least a portion that prevents this setting current source in response to this feedback signal transmits energy this minimum time to this capacitive device to this setting electric capacity charging so that prolong from this inductive means.
9. pulse frequency modulated voltage regulator as claimed in claim 8, wherein: this time lengthening circuit comprises:
One prolongs reference voltage, sets for less than an object feedback signal, and this object feedback signal is produced in this predetermined target voltage by this feedback circuit response, and
One difference current is right, in order to determine a discharging electric current based on absolute difference one of between this feedback signal and this prolongation reference voltage, make when this feedback signal prolongs reference voltage less than this, transmit energy this minimum time to this capacitive device by using this discharging electric current to prolong from this inductive means.
10. OFF time lengthening circuit, be used for a pulse frequency modulated voltage regulator, this pulse frequency modulated voltage regulator is changed a direct current voltage source and is become an output voltage by having one of predetermined minimal OFF time pulse frequency modulation switching signal, one of this output voltage flip-flop is a predetermined target voltage, and this OFF time lengthening circuit comprises:
One feedback signal, in order to indicate this output voltage, wherein when this output voltage equaled this predetermined target voltage, this feedback signal was an object feedback signal;
One first reference voltage, set for less than this object feedback signal: and
One first difference current is right, in order to determine one first discharging electric current based on absolute difference one of between this feedback signal and this first reference voltage, make when this feedback signal during, prolong the minimal OFF time that this is scheduled to by using this first discharging electric current less than this first reference voltage.
11. as the OFF time lengthening circuit of claim 10, wherein: when this feedback signal more was lower than this first reference voltage, this first discharging electric current was bigger.
12. OFF time lengthening circuit as claim 10, more comprise: one second reference voltage, set for less than this first reference voltage, and one second difference current right, in order to determine one second discharging electric current based on absolute difference one of between this feedback signal and this second reference voltage, make when this feedback signal during, first prolong the minimal OFF time that this is scheduled to this second discharging electric current by using this less than this second reference voltage.
13. OFF time lengthening circuit as claim 10, wherein: charging makes its potential difference (PD) determine from the zero predetermined time that voltage spent that increases to this predetermined minimal OFF time for an electric capacity by using a charging current, and this first discharging electric current is in order to reduce this charging current.
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| CNB2003101179379A CN100403206C (en) | 2003-11-26 | 2003-11-26 | Pulse-frequency modulation type voltage regulator capable of extending least OFF time |
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| CNB2003101179379A CN100403206C (en) | 2003-11-26 | 2003-11-26 | Pulse-frequency modulation type voltage regulator capable of extending least OFF time |
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| CN1621988A CN1621988A (en) | 2005-06-01 |
| CN100403206C true CN100403206C (en) | 2008-07-16 |
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| CN101079576B (en) * | 2006-05-24 | 2010-04-07 | 昂宝电子（上海）有限公司 | System for providing switch of power adjuster |
| CN101505096B (en) * | 2008-03-14 | 2011-04-13 | 天津英诺华微电子技术有限公司 | Pulse width frequency modulation mode DC/DC boosting circuit |
| CN113381589B (en) * | 2020-02-25 | 2024-08-27 | 瑞昱半导体股份有限公司 | Power supply device and pulse frequency modulation method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195222A (en) * | 1997-03-31 | 1998-10-07 | 富士通株式会社 | Regulating circuit |
| JPH1189222A (en) * | 1997-09-03 | 1999-03-30 | Hitachi Ltd | Voltage converter circuit |
| JPH11136929A (en) * | 1997-10-31 | 1999-05-21 | Nec Home Electron Ltd | Dc/dc converter device |
| US6281668B1 (en) * | 1998-02-18 | 2001-08-28 | Seiko Instruments Inc. | Switching regulator control circuit of PFM system and switching regulator thereof |
| US6486645B1 (en) * | 2001-06-13 | 2002-11-26 | Sipex Corporation | Voltage regulation circuit and related methods having a dynamically determined minimum discharge time |
| CN1392659A (en) * | 2002-08-01 | 2003-01-22 | 上海交通大学 | DC-DC conversion integrated circuit |
| JP2003259630A (en) * | 2002-03-01 | 2003-09-12 | Hitachi Ltd | Oscillator for power unit and power unit using it |
| CN1452307A (en) * | 2002-04-16 | 2003-10-29 | 精工电子有限公司 | Switch adjusting controlling circuit for modulation and control of pulse frequency |
-
2003
- 2003-11-26 CN CNB2003101179379A patent/CN100403206C/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195222A (en) * | 1997-03-31 | 1998-10-07 | 富士通株式会社 | Regulating circuit |
| JPH1189222A (en) * | 1997-09-03 | 1999-03-30 | Hitachi Ltd | Voltage converter circuit |
| JPH11136929A (en) * | 1997-10-31 | 1999-05-21 | Nec Home Electron Ltd | Dc/dc converter device |
| US6281668B1 (en) * | 1998-02-18 | 2001-08-28 | Seiko Instruments Inc. | Switching regulator control circuit of PFM system and switching regulator thereof |
| US6486645B1 (en) * | 2001-06-13 | 2002-11-26 | Sipex Corporation | Voltage regulation circuit and related methods having a dynamically determined minimum discharge time |
| JP2003259630A (en) * | 2002-03-01 | 2003-09-12 | Hitachi Ltd | Oscillator for power unit and power unit using it |
| CN1452307A (en) * | 2002-04-16 | 2003-10-29 | 精工电子有限公司 | Switch adjusting controlling circuit for modulation and control of pulse frequency |
| CN1392659A (en) * | 2002-08-01 | 2003-01-22 | 上海交通大学 | DC-DC conversion integrated circuit |
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