CN100395601C - Liquid crystal display panel and its driving method - Google Patents
Liquid crystal display panel and its driving method Download PDFInfo
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- CN100395601C CN100395601C CNB2006101056071A CN200610105607A CN100395601C CN 100395601 C CN100395601 C CN 100395601C CN B2006101056071 A CNB2006101056071 A CN B2006101056071A CN 200610105607 A CN200610105607 A CN 200610105607A CN 100395601 C CN100395601 C CN 100395601C
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Abstract
The present invention discloses a liquid crystal display device panel which comprises a first basal plate, a second basal plate and a liquid crystal layer, wherein the basal plate comprises a first substrate, a first pattern structure and a second pattern structure, wherein the first pattern structure and the second pattern structure are arranged above the first substrate by the method of being symmetrical to a first central line, and the second pattern structure is a mirror structure that the first pattern structure corresponds to the first central line. The second basal plate comprises a second substrate, a first pixel and a second pixel, wherein the first pixel is provided with a first thin film transistor, and the thin film transistor is coupled to a first scan line and a first data line. The second pixel is provided with a second thin film transistor which is coupled to a second scan line and the first data line. The liquid crystal layer is arranged between the first basal plate and the second basal plate.
Description
Technical field
The present invention relates to a kind of display panels and its driving method, and particularly relate to a kind of display panels and its driving method of tool high aperture.
Background technology
Please refer to Fig. 1, it illustrates the layout of traditional display panels of part.Display panels 10 comprises thin film transistor base plate (not indicating) and colored filter substrate (not illustrating).Colored filter substrate relatively is arranged at the top of thin film transistor base plate, and comprises liquid crystal layer (not illustrating) between this two substrate.Thin film transistor base plate comprises the first sweep trace G1, the second sweep trace G2, the first data line D1, the second data line D2 and the 3rd data line D3.These a little sweep trace G1 are parallel each other with G2, and this a little data line D1, D2 are parallel each other with D3 and with sweep trace G1 and G2 vertical interlaced, and define the first pixel P1 and the second pixel P2.The first pixel P1 comprises the first film transistor T 1 and first pixel electrode 18.Wherein, the first film transistor T 1 and the second sweep trace G2, the second data line D2 and first pixel electrode, 18 electric couplings.The second pixel P2 comprises the second thin film transistor (TFT) T2 and second pixel electrode 19.Wherein, the second thin film transistor (TFT) T2 and the second sweep trace G2, the 3rd data line D3 and second pixel electrode, 19 electric couplings.Colored filter substrate comprises first projection 15 and second projection 16.First projection 15 and second projection 16 are a plurality of display fields in order to the liquid crystal molecule of adjusting liquid crystal layer.For example, first projection 15 is divided into first area A1, second area A2 and the 3rd regional A3 with the first pixel P1.The first area A1 on first projection, 15 the right and the 3rd regional A3 control user are in the transmittance of right apparent time, and the second area A2 on first projection, 15 left sides control user is in the transmittance of left apparent time.Preferably, the area summation of first area A1 and the 3rd regional A3 equals the area of second area A2 in fact, makes the transmittance of right apparent time equal the transmittance of left apparent time in fact.
In the technology of display panels, when carrying out the step of upper and lower plates joint, the situation of upper and lower base plate dislocation takes place easily.When colored filter substrate is offset to the right, the area of second area A2 will increase, so that the area of second area A2 in fact will be greater than the area summation of first area A1 and the 3rd regional A3.In addition, in the second adjacent pixel P2, the area of the 5th regional A5 in fact will be greater than the area summation of the 4th regional A4 and the 6th regional A6.Thus, for the user, the transmittance of left apparent time will be significantly greater than the transmittance of right apparent time, to change pairing brightness rate of change asymmetric and cause right apparent time GTG value to change pairing brightness rate of change and left apparent time GTG value.Therefore, it is inaccurate and the different problem of left and right sides brightness rate of change of the display panels that causes is still the problem that waits to solve how to overcome two traditional substrate contrapositions.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of display panels and its driving method exactly, change the symmetry that pairing brightness rate of change and left apparent time GTG value change pairing brightness rate of change except increasing right apparent time GTG value, more can improve aperture ratio of pixels, to improve the image display quality of display panels.
According to purpose of the present invention, a kind of panel of LCD is proposed, it comprises first substrate, second substrate and liquid crystal layer.First substrate comprises first ground and first patterning and second patterning.First patterning and second patterning are arranged on first ground in the mode that is symmetrical in first center line, and second patterning is the mirror-image structure of first patterning corresponding to first center line.Second substrate comprises second ground, first pixel and second pixel.First pixel has the first film transistor, and the first film transistor is coupled to first sweep trace and first data line.Second pixel has second thin film transistor (TFT), and second thin film transistor (TFT) is coupled to second sweep trace and first data line.Liquid crystal layer is arranged between first substrate and second substrate.
According to purpose of the present invention, a kind of driving method is more proposed, be applicable to above-mentioned display panels.Driving method is at first during first sequential, in regular turn via first sweep trace and second sweep trace difference conducting the first film transistor AND gate transistor seconds.Then, provide pixel voltage to the first film transistor and second thin film transistor (TFT) via first data line.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 illustrates the section layout figure of traditional display panels of part.
It is the section layout figure of enantiomorphous display panels that Fig. 2 A illustrates according to projection.
Fig. 2 B illustrates the fragmentary cross-sectional view of the display panels of being looked along the profile line 2B-2B ' of Fig. 2 A.
The local figure of the part of the display panels after the colored filter substrate that Fig. 2 C illustrates Fig. 2 A moves right.
Fig. 3 illustrates the section layout figure that thin film transistor (TFT) is enantiomorphous display panels.
Fig. 4 A illustrates the section layout figure according to the display panels of one embodiment of the invention.
Fig. 4 B illustrates another example according to the section layout figure of the display panels of one embodiment of the invention.
Fig. 5 illustrates second example according to the section layout figure of the display panels of the embodiment of the invention.
Fig. 6 illustrates the 3rd example according to the section layout figure of the display panels of the embodiment of the invention.
Fig. 7 illustrates the 4th example according to the section layout figure of the display panels of the embodiment of the invention.
Fig. 8 illustrates the 5th example according to the section layout figure of the display panels of the embodiment of the invention.
The simple symbol explanation
10,20,30,40,50,60,70,80: display panels
21: thin film transistor base plate
22: colored filter substrate
23: liquid crystal layer
15,25,35,45,45 ': first projection
16,26,36,46,46 ': second projection
18,28,38,41,51,61,71: the first pixel electrodes
19,29,39,42,52,62,72: the second pixel electrodes
24: common electrode
27: colored filter
43,53,63,73: the three pixel electrodes
44,54,64,74: the four pixel electrodes
47: the three projections
48: the four projections
P1: first pixel
P2: second pixel
P3: the 3rd pixel
P4: the 4th pixel
T1: the first film transistor
T2: second thin film transistor (TFT)
T3: the 3rd thin film transistor (TFT)
T4: the 4th thin film transistor (TFT)
Embodiment
In order to solve transmittance with the transmittance of the right apparent time different problem of two substrates because of the inaccurate left apparent time that causes of contraposition, the present invention solves the problems referred to above by projection is designed to mirror-image structure.Please refer to Fig. 2 A, it illustrates the section layout figure that projection is enantiomorphous display panels.Please also refer to Fig. 2 B, it illustrates the fragmentary cross-sectional view of the display panels of being looked along the profile line 2B-2B ' of Fig. 2 A.Display panels 20 comprises thin film transistor base plate 21, colored filter substrate 22 and liquid crystal layer 23.Thin film transistor base plate 21 and colored filter substrate 22 opposing parallel settings.Liquid crystal layer 23 is arranged between thin film transistor base plate 21 and the colored filter substrate 22, and has a plurality of liquid crystal molecule 23a.In addition, thin film transistor base plate 21 comprises the first sweep trace G1 and the second sweep trace G2, and the first data line D1, the second data line D2 and the 3rd data line D3.Sweep trace G1 is parallel each other with G2; Data line D1, D2 parallel each other with D3 and with sweep trace G1 and G2 vertical interlaced, and define the first pixel P1 and the second pixel P2.The first pixel P1 comprises the first film transistor T 1 and first pixel electrode 28.Wherein, the first film transistor T 1 and the second sweep trace G2, the second data line D2 and first pixel electrode, 28 electric couplings.The second pixel P2 comprises the second thin film transistor (TFT) T2 and second pixel electrode 29.Wherein, the second thin film transistor (TFT) T2 and the second sweep trace G2, the 3rd data line D3 and second pixel electrode, 29 electric couplings.Colored filter substrate 22 comprises common electrode 24, first projection 25 and second projection 26 and colored filter 27.First projection 25 and second projection 26 are arranged on the common electrode 24, and relative with second pixel electrode 29 with first pixel electrode 28 respectively.
In display panels 20, second projection 26 is the mirror-image structure of first projection 25 corresponding to the first center line C1, and promptly the top 26a of the top 25a of first projection 25 and second projection 26 is all towards the first center line C1.First projection 25 and second projection 26 are a plurality of display fields in order to the liquid crystal molecule of adjusting liquid crystal layer.For example, first projection 25 is divided into first area E1, second area E2 and the 3rd area E 3 with the first pixel P1.Suppose display panels in technology, the situation that colored filter substrate 22 is offset to the right takes place, that is to say that first projection 25 and second projection 26 are offset to the right.Please refer to Fig. 2 C, the local figure of the part of the display panels after its colored filter substrate that illustrates Fig. 2 A moves right.By Fig. 2 C as can be known, after colored filter substrate 22 is offset to the right, the area of second area E2 ' will increase, so that the area of second area E2 ' will be in fact greater than the area summation of first area E1 ' with the 3rd area E 3 '.In addition, in the second adjacent pixel P2, the area of the 5th area E 5 ' will dwindle, thus the area of the 5th area E 5 ' will be in fact less than the area summation of the 4th area E 4 ' and the 6th area E 6 '.Because second area E2 ' is symmetrical in the 5th area E 5 ', first area E1 ' is symmetrical in the 4th area E 4 ', the 3rd area E 3 ' is symmetrical in the 6th area E 6 ', so for the first pixel P1, though the transmittance of left apparent time increases and the transmittance of right apparent time reduces, but for its second adjacent pixel P2, the transmittance of left apparent time but is that the transmittance of minimizing and right apparent time increases.Thus, for the user, the transmittance of left apparent time should equal the transmittance of right apparent time in theory.
The present invention has more proposed a kind of enantiomorphous display panels of thin film transistor (TFT) that has.Please refer to Fig. 3, it illustrates the section layout figure that thin film transistor (TFT) is enantiomorphous display panels.Different with Fig. 2 A is that in panel of LCD 30, the second thin film transistor (TFT) T2 is the mirror-image structure of the first film transistor T 1 corresponding to the first center line C1.Be that the first film transistor T 1 changes into and is coupled to the second sweep trace G2, the first data line D1 and first pixel electrode 38, and the second thin film transistor (TFT) T2 is maintained at and is coupled to the second sweep trace G2, the 3rd data line D3 and second pixel electrode 39.Thus, first projection 35 does not cover the first film transistor T 1, and second projection 36 also do not cover the second thin film transistor (TFT) T2, therefore, can make that more two pixel P1 are identical with the transmittance of P2.
As shown in Figure 3, display panels 30 also comprises three scan line G3, and it is parallel to the first sweep trace G1 and the second sweep trace G2, and defines the 3rd pixel P3 and the 4th pixel P4 with data line D1～D3.The 3rd pixel P3 comprises the 3rd thin film transistor (TFT) T3 and the 3rd pixel electrode 31.The 4th pixel P4 comprises the 4th thin film transistor (TFT) T4 and the 4th pixel electrode 32.The 4th thin film transistor (TFT) T4 is the mirror-image structure of the 3rd thin film transistor (TFT) T3 corresponding to the first center line C1.The 3rd thin film transistor (TFT) T3 is coupled to three scan line G3, the second data line D2 and the 3rd pixel electrode 31.The 4th thin film transistor (TFT) T4 is coupled to three scan line G3, the second data line D2 and the 4th pixel electrode 32.
Please refer to Fig. 4 A, it is the section layout figure of the display panels of one embodiment of the invention.Display panels 40 comprises colored filter substrate, thin film transistor base plate and liquid crystal layer, and the configuration relation between it is identical with Fig. 2 B, so do not repeat them here.Colored filter substrate comprises first ground (not illustrating), first projection 45 and second projection 46.First projection 45 and second projection 46 are arranged on first ground in the mode that is symmetrical in the first center line C1, and second projection 46 is the mirror-image structure of first projection 45 corresponding to the first center line C1.In other words, first projection 45 also is the mirror-image structure of second projection 46 corresponding to the first center line C1.Thin film transistor base plate comprises second ground (not illustrating), the first data line D1, the second data line D2, the 3rd data line D3, the first sweep trace G1, the second sweep trace G2, the first pixel P1 and the second pixel P2.The first data line D1, the second data line D2 and the 3rd data line D3 are arranged on second ground in fact abreast, and the first center line C1 is positioned at the top of the second data line D2 in fact.The first sweep trace G1 and the second sweep trace G2 are arranged on second ground in fact abreast, and intersect vertically in fact with first data line.The first pixel P1 has the first film transistor T 1 and first pixel electrode 41, and the first film transistor T 1 is coupled to the first sweep trace G1, the second data line D2 and first pixel electrode 41.The second pixel P2 has the second thin film transistor (TFT) T2 and second pixel electrode, 42, the second thin film transistor (TFT) T2 are coupled to the second sweep trace G2, the second data line D2 and second pixel electrode 42.Preferably, first projection 45 and second projection 46 are a V-shape projection, and the top end face of V-shape projection is to the first center line C1.
Shown in Fig. 4 A, the first projection 45 the first film transistor T 1 of not overlapping, and second projection 46, the second thin film transistor (TFT) T2 of not overlapping.Therefore, the transmittance of the first pixel P1 equals the transmittance of the second pixel P2 in fact.In first embodiment of the invention, though the first film transistor T 1 is coupled to identical data line D2 with the second thin film transistor (TFT) T2, because the first film transistor T 1 couples with the second thin film transistor (TFT) T2 and is coupled to different sweep trace G1 and G2 respectively.Therefore, the second data line D2 can not take place provides pixel voltage to two adjacent pixel P1 and the situation of P2 simultaneously.
In addition, thin film transistor base plate also comprises three scan line G3, the 3rd pixel P3 and the 4th pixel P4.Three scan line G3 is arranged on second ground, and the second sweep trace G2 is disposed between the first sweep trace G1 and the three scan line G3.The 3rd pixel P3 has the 3rd thin film transistor (TFT) T3 and the 3rd pixel electrode 43, and the 4th pixel P4 has the 4th thin film transistor (TFT) T4 and the 4th pixel electrode 44.Wherein, the 3rd thin film transistor (TFT) T3 is coupled to the second sweep trace G2, the first data line D1 and the 3rd pixel electrode 43, the four thin film transistor (TFT) T4 are coupled to three scan line G3, the 3rd data line D3 and the 4th pixel electrode 44.Colored filter substrate also comprises the 3rd projection 47 and the 4th projection 48, and it is arranged on first ground in the mode that is symmetrical in the first center line C1, and the 4th projection 48 is the mirror-image structure that the 3rd projection 47 is symmetrical in the first center line C1.Preferably, the 3rd projection 47 and the 4th projection 48 are the V-shape projection, and the opening surface of V-shape projection is to the first center line C1, and promptly the opening direction of the 3rd projection 47 is opposite with the opening direction of first projection 45.So the 3rd projection 47 the 3rd thin film transistor (TFT) T3 of not overlapping, and the 4th projection 48 the 4th thin film transistor (TFT) T4 of not overlapping.
Next will describe the image element driving method of display panels 40 in detail.At first, during first sequential in, come conducting the first film transistor T 1 via the first sweep trace G1, and utilize the second data line D2 that corresponding pixel voltage to the first pixel P1 is provided.Then, in during second sequential, come conducting the 3rd thin film transistor (TFT) T3 and the second thin film transistor (TFT) T2 via the second sweep trace G2 in regular turn, and utilize the first data line D1 that corresponding pixel voltage to the three pixel P3 are provided, and utilize the second data line D2 that corresponding pixel voltage to the second pixel P2 is provided.At last, during the 3rd sequential in, come conducting the 4th thin film transistor (TFT) T4 via three scan line G3, and utilize the 3rd data line D3 that corresponding pixel voltage to the four pixel P4 are provided.
Please refer to Fig. 4 B, it is another example of section layout figure of the display panels of one embodiment of the invention.Different with Fig. 4 A is, first projection 45 ' and second projection 46 ', the opening surface of its V font projection is to the first center line C1, makes first projection 45 ' of the part the first film transistor T 1 of overlapping, and second projection 46 ' of part, the second thin film transistor (TFT) T2 of overlapping.Thus, the transmittance of the first pixel P1 still equals the transmittance of the second pixel P2 in fact.In addition, the 3rd projection 47 ' and the 4th projection 48 ', the top end face of its V font projection be to the first center line C1, makes the 3rd projection 47 ' of part the 3rd thin film transistor (TFT) T3 of overlapping, and the 4th projection 48 ' of part the 4th thin film transistor (TFT) T4 of overlapping.Therefore, the transmittance of the 3rd pixel P3 still equals the transmittance of the 4th pixel P4 in fact.
Please refer to Fig. 5, it is second example of section layout figure of the display panels of the embodiment of the invention.Different with Fig. 4 B with 4A is, in display panels 50, the first film transistor T 1 is coupled to the second sweep trace G2, the second data line D2 and first pixel electrode 51, the second thin film transistor (TFT) T2 is coupled to the first sweep trace G1, the second data line D2 and second pixel electrode 52, the 3rd thin film transistor (TFT) T3 is coupled to three scan line G3, the first data line D1 and the 3rd pixel electrode 53, the four thin film transistor (TFT) T4 are coupled to the second sweep trace G2, the 3rd data line D3 and the 4th pixel electrode 54.Remaining element all display panels 40 with Fig. 4 A is identical, so do not repeat them here.
Next will describe the image element driving method of display panels 50 in detail.In at first during first sequential, come the conducting second thin film transistor (TFT) T2, and utilize the second data line D2 that corresponding pixel voltage to the second pixel P2 is provided via the first sweep trace G1.Then, in during second sequential, come conducting the first film transistor T 1 and the 4th thin film transistor (TFT) T4 via the second sweep trace G2 in regular turn, and utilize the second data line D2 that corresponding pixel voltage to the first pixel P1 is provided, and utilize the 3rd data line D3 that corresponding pixel voltage to the four pixel P4 are provided.At last, during the 3rd sequential in, come conducting the 3rd thin film transistor (TFT) T3 via three scan line G3, and utilize the first data line D1 that corresponding pixel voltage to the three pixel P3 are provided.
Please refer to Fig. 6, it is the 3rd example of section layout figure of the display panels of the embodiment of the invention.Different with 4B figure with 4A is, in display panels 60, the first film transistor T 1 is coupled to the first sweep trace G1, the second data line D2 and first pixel electrode 61, the second thin film transistor (TFT) T2 is coupled to the second sweep trace G2, the second data line D2 and second pixel electrode 62, the 3rd thin film transistor (TFT) T3 is coupled to three scan line G3, the first data line D1 and the 3rd pixel electrode 63, the four thin film transistor (TFT) T4 are coupled to the second sweep trace G2, the 3rd data line D3 and the 4th pixel electrode 64.Remaining element all display panels 40 with Fig. 4 A is identical, so do not repeat them here.
Next will describe the image element driving method of display panels 60 in detail.In at first during first sequential, come conducting the first film transistor T 1, and utilize the second data line D2 that corresponding pixel voltage to the first pixel P1 is provided via the first sweep trace G1.Then, in during second sequential, come conducting second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4 via the second sweep trace G2 in regular turn, and utilize the second data line D2 that corresponding pixel voltage to the second pixel P2 is provided, and utilize the 3rd data line D3 that corresponding pixel voltage to the four pixel P4 are provided.At last, during the 3rd sequential in, come conducting the 3rd thin film transistor (TFT) T3 via three scan line G3, and utilize the first data line D1 that corresponding pixel voltage to the three pixel P3 are provided.
Please refer to Fig. 7, it is the 4th example of section layout figure of the display panels of the embodiment of the invention.Different with 4B figure with 4A is, in display panels 70, the first film transistor T 1 is coupled to the second sweep trace G2, the second data line D2 and first pixel electrode 71, the second thin film transistor (TFT) T2 is coupled to the first sweep trace G1, the second data line D2 and second pixel electrode 72, the 3rd thin film transistor (TFT) T3 is coupled to the second sweep trace G2, the first data line D1 and the 3rd pixel electrode 73, the four thin film transistor (TFT) T4 are coupled to three scan line G3, the 3rd data line D3 and the 4th pixel electrode 74.Remaining element all display panels 40 with Fig. 4 A is identical, so do not repeat them here.
Next will describe the image element driving method of display panels 70 in detail.In at first during first sequential, come the conducting second thin film transistor (TFT) T2, and utilize the second data line D2 that corresponding pixel voltage to the second pixel P2 is provided via the first sweep trace G1.Then, in during second sequential, come conducting the 3rd thin film transistor (TFT) T3 and the first film transistor T 1 via the second sweep trace G2 in regular turn, and utilize the first data line D1 that corresponding pixel voltage to the three pixel P3 are provided, and utilize the second data line D2 that corresponding pixel voltage to the first pixel P1 is provided.At last, during the 3rd sequential in, come conducting the 4th thin film transistor (TFT) T4 via three scan line G3, and utilize the 3rd data line D3 that corresponding pixel voltage to the four pixel P4 are provided.
The display panels of the above-mentioned embodiment of the invention and its driving method are example with four pixel P1, P2, P3 and P4, yet, also not subject to the limits in practical application.Please refer to Fig. 8, it is the 5th example according to the section layout figure of the display panels of the embodiment of the invention.In display panels 80, pixel P
1R, P
1GWith P
1BThin film transistor (TFT) all be arranged at the upper right corner of corresponding pixel, and pixel P
2R, P
2GWith P
2BThin film transistor (TFT) all be arranged at the lower left corner of corresponding pixel.Wherein, pixel P
1RWith P
2RReceive red pixel voltage, pixel P
1GWith P
2GReceive green pixel voltage, and pixel P
1BWith P
2BReceive blue pixels voltage.In addition, be positioned at pixel P
1R, P
1GWith P
1BThe top the V-shape projection and be positioned at pixel P
2R, P
2GWith P
2BThe V-shape projection of top is arranged on the colored filter substrate in the mode that is symmetrical in the second center line C2.Wherein, the second center line C2 is positioned at the top of the 4th data line D4 in fact.For example, be positioned at pixel P
1R, P
1GWith P
1BThe opening surface of the V-shape projection of top then is positioned at pixel P to the second center line C2
2R, P
2GWith P
2BThe V-shape projection of top makes pixel P also towards the second center line C2
1R～P
2BThin film transistor (TFT) all covered by its pairing V-shape projection.Other pixel P
3R～P
4BConfiguration mode in conjunction with above-mentioned pixel P
1R～P
2BAnd the 3rd pixel P3 of first embodiment and the collocation method of the 4th pixel P4, or cooperating the collocation method of all the foregoing descriptions or its combination, those skilled in the art are inference and going out all easily, so do not repeat them here.
In brief, connected mode between the thin film transistor (TFT) of pixel and sweep trace and the data line can four pixels be a unit, first embodiment to the, four embodiment promptly of the present invention, cooperate the arrangement of going up Red Green Blue again, and then obtain multiple permutation and combination.It should be noted that, the opening direction that is positioned at the patterning of first substrate need cooperate the set position of thin film transistor (TFT), make all thin film transistor (TFT)s all be covered by patterning, make the thin film transistor (TFT) of part be covered, or make all thin film transistor (TFT)s do not covered by patterning by patterning.In addition, the type of drive of pixel also can change to some extent along with the connected mode of different thin film transistor (TFT)s, but still the type of drive that does not break away from first embodiment to the, four embodiment of the present invention.
The disclosed display panels of the above embodiment of the present invention makes the transmittance of left apparent time identical in fact with the transmittance of right apparent time except having enantiomorphous projection, with reach make right apparent time GTG value change pairing brightness rate of change and left apparent time GTG value change pairing brightness rate of change can symmetry outside, display panels of the present invention utilizes the aperture position of enantiomorphous thin film transistor (TFT) collocation projection, more can solve the different problem of transmittance between the different pixels, make neighbor have equal aperture opening ratio, to improve the image display quality of display panels.
In sum; though the present invention discloses as above with preferred embodiment, yet it is not that those skilled in the art without departing from the spirit and scope of the present invention in order to qualification the present invention; can do a little change and retouching, thus protection scope of the present invention should with claim the person of being defined be as the criterion.
Claims (8)
1. display panels comprises:
First substrate comprises:
First ground; And
First patterning and second patterning are arranged on this first ground in the mode that is symmetrical in first center line, and this second patterning is the mirror-image structure of this first patterning corresponding to this first center line;
Second substrate comprises:
Second ground;
First data line is arranged on this second ground, and this first center line is positioned at the top of this first data line in fact;
First sweep trace and second sweep trace are arranged on this second ground in fact abreast, and intersect vertically in fact with this first data line;
First pixel has the first film transistor, and this first film transistor is coupled to this first sweep trace and this first data line; And
Second pixel has second thin film transistor (TFT), and this second thin film transistor (TFT) is coupled to this second sweep trace and this first data line; And
Liquid crystal layer is arranged between this first substrate and this second substrate.
2. display panels as claimed in claim 1, wherein, this first patterning is the V-shape projection, the opening surface of this V-shape projection is to this first center line.
3. display panels as claimed in claim 1, wherein, this first patterning is the V-shape projection, the top end face of this V-shape projection is to this first center line.
4. display panels as claimed in claim 1, wherein, this first patterning this first film transistor of overlapping of part, this second patterning of part this second thin film transistor (TFT) of overlapping.
5. display panels as claimed in claim 1, wherein, this first substrate also comprises the 3rd patterning and the 4th patterning, be arranged on this first ground in the mode that is symmetrical in this first center line, the 4th patterning is the mirror-image structure of the 3rd patterning corresponding to this first center line;
Wherein, this second substrate also comprises:
Second data line and the 3rd data line are arranged on this second ground, are disposed at the both sides of this first data line respectively;
Three scan line is arranged on this second ground, and this second sweep trace is disposed between this first sweep trace and this three scan line;
The 3rd pixel has the 3rd thin film transistor (TFT), and the 3rd thin film transistor (TFT) is coupled to this second sweep trace and this second data line; And
The 4th pixel has the 4th thin film transistor (TFT), and the 4th thin film transistor (TFT) is coupled to this three scan line and the 3rd data line;
Wherein, the opening direction with the 3rd patterning is opposite in fact for the opening direction of this first patterning.
6. display panels as claimed in claim 5, wherein, the 3rd patterning the 3rd thin film transistor (TFT) of overlapping of part, the 4th patterning of part the 4th thin film transistor (TFT) of overlapping.
7. a driving method is applicable to display panels as claimed in claim 1, and this method comprises:
During first sequential, in regular turn via this first sweep trace and this second sweep trace difference this first film transistor of conducting and this second thin film transistor (TFT); And
Provide pixel voltage to this first pixel and this second pixel via this first data line.
8. a driving method is applicable to display panels as claimed in claim 5, and this method comprises:
During first sequential, in regular turn via this this first film transistor of first sweep trace conducting, via this this second thin film transistor (TFT) of second sweep trace conducting and the 3rd thin film transistor (TFT), and via this three scan line conducting the 4th thin film transistor (TFT);
Provide first pixel voltage to this first pixel and this second pixel via this first data line;
Provide second pixel voltage to the 3rd pixel via this second data line; And
Provide the 3rd pixel voltage to the 4th pixel via the 3rd data line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101056071A CN100395601C (en) | 2006-07-10 | 2006-07-10 | Liquid crystal display panel and its driving method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101056071A CN100395601C (en) | 2006-07-10 | 2006-07-10 | Liquid crystal display panel and its driving method |
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| Publication Number | Publication Date |
|---|---|
| CN1877409A CN1877409A (en) | 2006-12-13 |
| CN100395601C true CN100395601C (en) | 2008-06-18 |
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| CNB2006101056071A Active CN100395601C (en) | 2006-07-10 | 2006-07-10 | Liquid crystal display panel and its driving method |
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| US8797231B2 (en) * | 2009-04-15 | 2014-08-05 | Nlt Technologies, Ltd. | Display controller, display device, image processing method, and image processing program for a multiple viewpoint display |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020093615A1 (en) * | 2001-01-12 | 2002-07-18 | Joong- Hyun Mun | Liquid crystal display having wide viewing angle |
| US20030202144A1 (en) * | 1998-05-20 | 2003-10-30 | Kyeong-Hyeon Kim | Liquid crystal display having wide viewing angle |
| US6798482B2 (en) * | 1997-09-08 | 2004-09-28 | Lg.Philips Lcd Co., Ltd | In-plane switching mode liquid crystal display device |
| WO2004086133A1 (en) * | 2003-03-28 | 2004-10-07 | Samsung Electronics Co. Ltd. | Liquid crystal display and thin film transistor array panel therefor |
| CN1627160A (en) * | 2003-12-11 | 2005-06-15 | Lg.菲利浦Lcd株式会社 | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
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- 2006-07-10 CN CNB2006101056071A patent/CN100395601C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6798482B2 (en) * | 1997-09-08 | 2004-09-28 | Lg.Philips Lcd Co., Ltd | In-plane switching mode liquid crystal display device |
| US20030202144A1 (en) * | 1998-05-20 | 2003-10-30 | Kyeong-Hyeon Kim | Liquid crystal display having wide viewing angle |
| US20020093615A1 (en) * | 2001-01-12 | 2002-07-18 | Joong- Hyun Mun | Liquid crystal display having wide viewing angle |
| WO2004086133A1 (en) * | 2003-03-28 | 2004-10-07 | Samsung Electronics Co. Ltd. | Liquid crystal display and thin film transistor array panel therefor |
| CN1627160A (en) * | 2003-12-11 | 2005-06-15 | Lg.菲利浦Lcd株式会社 | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
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| CN1877409A (en) | 2006-12-13 |
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