CN100392621C - Bus controller and data buffer space allocation method - Google Patents
Bus controller and data buffer space allocation method Download PDFInfo
- Publication number
- CN100392621C CN100392621C CNB2005101137587A CN200510113758A CN100392621C CN 100392621 C CN100392621 C CN 100392621C CN B2005101137587 A CNB2005101137587 A CN B2005101137587A CN 200510113758 A CN200510113758 A CN 200510113758A CN 100392621 C CN100392621 C CN 100392621C
- Authority
- CN
- China
- Prior art keywords
- master control
- bus
- control set
- data buffering
- space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The present invention relates to a bus controller a data buffering space allocation method, which is applied to control a bus. The bus can be used for a plurality of master control devices to carry out signal connection. The controller comprises a data buffering unit and a data buffering control logic circuit. The method comprises that the number of the bus master control devices of connecting with the bus can be detected; if the number of the master control devices is larger than a default, the data buffering control logic circuit can cause the bus controller to enter into a first allocation state; inversely, if the number of the master control devices is not larger than a default, the data buffering control logic circuit can cause the bus controller to enter into a second allocation state, wherein the allocated data buffering space of each master control device in the second allocation state is larger than the allocated data buffering space of each master control device in the first allocation state.
Description
Technical field
The present invention relates to a kind of bus controller and data buffer space allocation method, outstanding reference and a kind of bus controller and data buffer space allocation method that is applied on the bus.
Background technology
See also Fig. 1, it is a peripheral assembly connecting interface bus (Peripheral ComponentInterconnect Bus, abbreviation PCI Bus) function square frame connection diagram, wherein mainly be to have master control set 10 and destination apparatus 11 to be connected on the peripheral assembly connecting interface bus 1, and master control set 10 can send the request of a data read by peripheral assembly connecting interface bus 1 to destination apparatus 11, with so that destination apparatus 11 is ready to corresponding data, receive to master control set 10 corresponding data back by peripheral assembly connecting interface bus 1 again.But in traditional data read request specification, do not record the total length of master control set 10 desired datas, therefore destination apparatus 11 is in this subtask, and do not know that master control set 10 will read double-word group how long (Double Word on earth, be called for short DW), and destination apparatus 11 delay (latency) on usually all can be if having time when grasping corresponding data, therefore postpone (latency) to reach the purpose of continuous transmission in order to reach to eliminate, pre-grasping means (pre-fetch method) is just arisen at the historic moment.
The main spirit of pre-grasping means (pre-fetch method) is that destination apparatus 11 can in advance grasp some data more and temporarily leaves in the data buffer 120 in the bus controller 12, and then deals with the request of the follow-up data read of master control set 10.For instance, if the specification of peripheral assembly connecting interface bus 1 can connect for 4 bus assembly devices (master control set 10 as shown in FIG.), and provide 8 basket positions (basket) to come store data in the data buffer 120, the capacity of each basket position is 8 four word groups (Quadruple Word is called for short QW).And in order to prevent the space of 4 bus assembly devices plunder data buffers 120, the simplest practice commonly used is to use to 4 bus assembly devices 8 basket position mean allocation.But this will cause a problem, it is long that is exactly the time delay (sending a request " FRAME# " to data back " DATAR " from master control set 10) of working as reading of data, and the space of depositing pre-extracting data that some master control sets are assigned to is when apply using, and this master control set just must stop to take bus and wait for that just can continue to grasp new data after emptying inserts.And this is when being connected with three or four master control sets simultaneously on peripheral assembly connecting interface bus 1, even first master control set stops to take bus because of cushion space is not enough, still have follow-up second of waiting in line or the 3rd master control set then to use the probability of bus quite big, so the utilization factor of bus can maintain certain level.But, when only being connected with two or a master control set on the peripheral assembly connecting interface bus 1, each master control set is fixed allocation to 2 a basket position only still, and when a master control set stops to take bus because of cushion space is not enough, only Sheng another master control set (even not having another bus assembly device) to be ready waiting in line to use the certain more above-mentioned a plurality of master control sets of probability of bus to rob with the situation of bus little, and conventional means can only not know that at this moment flexible ground is in bus standby (idle) state and total line use ratio is declined to a great extent, and has a strong impact on performance of entire system.And how to improve the defective of this conventional means, be development the application's fundamental purpose.
Summary of the invention
To achieve these goals, the invention provides a kind of data buffer space allocation method, be applied to a bus controller, this bus controller includes a data buffer unit, in order to the data buffering space to be provided, this data buffer unit is deposited for the pre-data that grasp, and this method comprises the following step: detect the quantity that is connected in the Bus Master on this bus; If the quantity of Bus Master is during greater than a default value and make bus controller enter one first distribution state; When if the quantity of Bus Master is not more than default value, make bus controller enter one second distribution state, and wherein in second distribution state assigned data buffering space of each Bus Master greater than the assigned data buffering space of each Bus Master in this first distribution state.
The present invention also provides a kind of bus controller, and this controller comprises: a data buffer unit provides the cushion space of depositing the data that will be transferred to Bus Master; And a data buffering control logic circuit, be connected in data buffer unit, when detecting the number during greater than a default value that is connected in the Bus Master on the bus, then bus controller enters one first distribution state; When being not more than a default value as if the number that is connected in the Bus Master on the bus, then bus controller enters one first distribution state.Wherein under second distribution state assigned data buffering space of each Bus Master greater than the assigned data buffering space of each Bus Master under this first distribution state.
Description of drawings
Fig. 1 is the function square frame connection diagram of a peripheral assembly connecting interface bus.
Fig. 2 is the function block diagram of a peripheral assembly connecting interface bus of utilization the application preferred embodiment method.
Fig. 3 is the application's a preferred embodiment method flow diagram.
Fig. 4 is a function square frame example schematic of the application's bus controller inside.
Wherein, description of reference numerals is as follows:
1 peripheral assembly connecting interface bus, 10 master control sets
11 destination apparatus, 12 bus controllers
120 data buffers
2 buses, 22 bus controllers
200 first master control sets, 201 second master control sets
202 the 3rd master control sets 203 the 4th master control set
21 destination apparatus, 220 data buffer unit
221 data buffering control logic circuits, 0 impact damper
1 impact damper, 2 impact dampers
3 impact dampers, 4 impact dampers
5 impact dampers, 6 impact dampers
7 impact dampers, 222 first multiplexers
223 second multiplexers 224 the 3rd multiplexer
Embodiment
And be the defective that can improve above-mentioned conventional means, the application develops and a data buffer space allocation method, mainly can use among the peripheral assembly connecting interface bus functionality block diagram as shown in Figure 2.
Can provide a plurality of Bus Masters to be connected on bus 2 and the bus controller 22, be with maximum quantity-four master control set (first master control set 200 among this routine figure, second master control set 201, the 3rd master control set 202 and the 4th master control set 203) and a destination apparatus 21 describe, and data buffer unit 220 includes 8 impact dampers in this bus controller 22, the capacity of each impact damper is 8 four word groups, and be numbered basket position 0 respectively, basket position 1, basket position 2, basket position 3, basket position 4, basket position 5, basket position 6 and basket position 7, described impact damper stored target device 21 grasps the data of gained in advance.
The application's preferred embodiment method flow diagram then as shown in Figure 3.At first, in the boot program of computer system, its bus architecture is carried out coupling assembling when scanning by its operating system, detect bus 2 and in fact connected several Bus Masters, then detected master control set quantity is sent to bus controller 22 and compares and subsequent treatment.When the Bus Master quantity that detects actual connection during greater than a default value, just make bus controller 22 enter one first distribution state, and when the bus assembly device quantity that detects actual connection is not more than default value, just make bus controller 22 enter one second distribution state.
For instance, the assumed by default value is 2 o'clock, if when then being physically connected to the master control set of bus and outnumbering 2, then bus controller 22 enters first distribution state, if instead when detecting the master control set number that is physically connected to bus and be no more than 2, then bus controller 22 enters second distribution state.
And under first distribution state assigned data buffering space of each master control set less than the assigned data buffering space of each master control set under second distribution state.That is lack than the assigned number of buffers of each master control set under second distribution state in the assigned number of buffers of each master control set under first distribution state.
With this example, when first distribution state, 8 impact dampers are to distribute to 4 master control sets with two one group, and when second distribution state, 8 impact dampers are to distribute to two master control sets with 4 one group.
Thus, when the master control set that only is connected on the bus below two or two, originally idle data buffering space just can flexibly be redistributed, make each master control set can be assigned to more data buffering space, so can allow when only being connected with two or a master control set on the peripheral assembly connecting interface bus, total line use ratio still can effectively be kept, and then promotes performance of entire system, effectively improve the defective of conventional means, reach development the application's fundamental purpose.
See also Fig. 4 again, it is a function square frame example schematic of above-mentioned bus controller 22 inside, it mainly is made up of a data buffering control logic circuit 221, data buffer unit 220 (this example includes 8 impact dampers, and the capacity of each impact damper is numbered basket position 0, basket position 1, basket position 2, basket position 3, basket position 4, basket position 5, basket position 6 and basket position 7 respectively by 8 four word groups), first multiplexer 222, second multiplexer 223 and the 3rd multiplexer 224.But wherein this data buffering control logic circuit 221 just operation response system quantity that its bus architecture is carried out the bus assembly device that in fact coupling assembling detected bus 2 of when scanning connect decide and enter first distribution state or second distribution state.
In the present invention, suppose that attachable master control set quantity mostly is 4 most, and when detecting the master control set quantity that is physically connected to bus greater than 2 the time, make bus controller 22 enter first distribution state, promptly 8 impact dampers be with two one group distribute to maximum 4 master control sets (promptly express basket position 0 among the figure, basket position 1 is first group, basket position 2, basket position 3 are second group, and basket position 4, basket position 5 are the 3rd group, and basket position 6 and basket position 7 are the 4th group).And when detecting the master control set quantity that is physically connected to bus and be not more than 2, make bus controller 22 enter second distribution state, promptly 8 impact dampers are to distribute to maximum two master control sets with 4 one group (promptly expressing basket position 0, basket position 1, basket position 2, basket position 3 among the figure is first group, and basket position 4, basket position 5, basket position 6 and basket position 7 are second group).
Hypothesis has four bus assembly devices in the first embodiment of the invention: when first master control set 200, second master control set 201, the 3rd master control set 202 and the 4th master control set 203 are connected to bus 2, the above-mentioned method according to the present invention, bus controller 22 enters first distribution state.
When being in first distribution state, first master control set 200 is assigned to basket position (0,1), and second master control set 201 is assigned to basket position (2,3), and the 3rd master control set 202 is assigned to basket position (4,5), and the 4th master control set 203 is assigned to basket position (6,7).Therefore what 221 pairs first multiplexers 222 of data buffering control logic circuit and second multiplexer 223 were sent respectively first selects the signal and the second selection signal all to maintain low voltage level (representing with logical zero).
And 221 pairs the 3rd multiplexers 224 of data buffering control logic circuit send the 3rd selection signal, are in order to select which master control set to have the right to use of bus.In the present embodiment, suppose to represent that when the 3rd selection signal is 00 first master control set 200 has the right to use of bus, when the 3rd selection signal is the right to use that 01 expression second master control set 201 has bus; When the 3rd selection signal is the right to use that 10 expression the 3rd master control sets 202 have bus; When the 3rd selection signal is the right to use that 11 expression the 4th master control sets 203 have bus.
Thus, first master control set 200, second master control set 201, the 3rd master control set 202 and the 4th master control set 203 arrive mean allocation in the impact damper of basket position (0,1), basket position (2,3), basket position (4,5) and basket position (6,7).
In embodiments of the present invention,, will only have two impact dampers, but if when being connected with two master control sets or a master control set, this example will enter second distribution state by idle if when being connected with three master control sets.
Hypothesis has only two master control sets in the second embodiment of the invention: when first master control set 200 and second master control set 201 are connected to bus 2, the above-mentioned method according to the present invention, data buffering control logic circuit 221 makes bus controller 22 enter second distribution state.
When being in second distribution state, first master control set 200 is assigned to basket position (0,1) and basket position (4,5), and second master control set 201 is assigned to basket position (2,3) and basket position (6,7).Therefore data buffering control logic circuit 221 sends first respectively and selects signal and second selection signal to the first multiplexer 222 and second multiplexer 223.When supposing the first selection signal, just the data in basket position (0,1) are delivered to first master control set 200 for " 0 "; When the first selection signal is " 1 ", the data in basket position (4,5) are delivered to first master control set 200.When the second selection signal is " 0 ", the data in basket position (2,3) are delivered to second master control set 201; When the second selection signal is " 1 ", then the data in basket position (6,7) are delivered to second master control set 201.
In addition in the present embodiment, suppose to represent that when the 3rd selection signal is 00 first master control set 200 has the right to use of bus, when the 3rd selection signal is the right to use that 01 expression second master control set 201 has bus.
Thus, first master control set 200 and second master control set 201 arrive the basket position with mean allocation, that is first master control set 200 can use basket position (0,1) and the impact damper of basket position (4,5), and second master control set 201 can use basket position (2,3), the impact damper of basket position (6,7).
The number of this impact damper is the integral multiple that can be connected to this master control set maximum number of this bus in the present invention.
Certainly, above-mentioned example only is for clearly demonstrating the application's technological means, therefore do not limit the number of its master control set and cushion space unit, but the quantity of described cushion space unit is generally the integral multiple of the maximum quantity of attachable bus assembly device on this bus.And also not necessarily to be divided into two kinds of distribution state, three or more also is feasible, only need to increase the multiplexer number and select the variation of signal to get final product, so this not with give unnecessary details.
In sum as can be known, the application can effectively increase total line use ratio, and then reaches development the application's fundamental purpose.Therefore all other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the application's the claim.
Claims (8)
1. the distribution method in a data buffering space is connected to the operable cushion space of master control set on the peripheral unit connecting interface bus in order to distribution, and this method includes:
Detection is connected to the number of the master control set on this peripheral unit connecting interface bus;
If one first distribution state of the number of described master control set, then using greater than a default value disposes this data buffering space and gives described master control set; If the number of described master control set is not more than this default value, then use one second distribution state to dispose this data buffering space and give described master control set, when wherein using first distribution state, the operable data buffering of described master control set space is the operable data buffering of described master control set space when using second distribution state.
2. the distribution method in data buffering according to claim 1 space wherein can be when computer system power-on detects the number of the master control set that be connected to this peripheral unit connecting interface bus by operating system.
3. the distribution method in data buffering according to claim 1 space, wherein this method can be used for a bus controller.
4. a bus control device is given all master control sets that are connected on the peripheral unit connecting interface bus in order to dynamic assignment data buffering space, and this bus control device includes:
One data buffer unit comprises a plurality of impact dampers, in order to the data buffering space to be provided;
One data buffering control logic circuit is connected to this data buffer unit, and the master control set number that is connected to this peripheral unit connecting interface bus in order to basis determines that this bus control device is one first distribution state or one second distribution state,
Wherein when the master control set that is connected to this peripheral unit connecting interface bus outnumbers a default value, then use this first distribution state distribute data cushion space; Wherein when the master control set number that is connected to this peripheral unit connecting interface bus is no more than this default value, then use this second distribution state distribute data cushion space, and described master control set in number of buffers assigned under this first distribution state less than this second distribution state under assigned number of buffers.
5. bus control device according to claim 4, wherein this data buffering control logic circuit is given described master control set according to the number that is connected to the master control set on this peripheral unit connecting interface bus with described a plurality of buffer allocation.
6. bus control device according to claim 4, wherein this bus control device also includes a plurality of multiplexers, it is connected to this data buffer unit, this data buffering control logic circuit sends the selection signal to described a plurality of multiplexers respectively, in order to selecting the operable impact damper of described master control set, and distribute this data buffering space to give the master control set that is connected to this peripheral unit connecting interface bus.
7. bus control device according to claim 4, the number of wherein said impact damper are the integral multiple that can be connected to the master control set maximum number of this bus.
8. bus control device according to claim 4 wherein can be when computer system power-on detects the number of the master control set that be connected to this bus by operating system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101137587A CN100392621C (en) | 2005-10-14 | 2005-10-14 | Bus controller and data buffer space allocation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101137587A CN100392621C (en) | 2005-10-14 | 2005-10-14 | Bus controller and data buffer space allocation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1744060A CN1744060A (en) | 2006-03-08 |
| CN100392621C true CN100392621C (en) | 2008-06-04 |
Family
ID=36139443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101137587A Active CN100392621C (en) | 2005-10-14 | 2005-10-14 | Bus controller and data buffer space allocation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100392621C (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5675793A (en) * | 1992-09-30 | 1997-10-07 | Microsoft Corporation | Dynamic allocation of a common buffer for use by a set of software routines |
| EP1246072A1 (en) * | 2001-03-27 | 2002-10-02 | Intel Corporation | Adaptive read pre-fetch |
| US20030037198A1 (en) * | 2001-08-20 | 2003-02-20 | Hunsaker Mikal C. | Dynamic delayed transaction buffer configuration based on bus frequency |
| US20030196020A1 (en) * | 2002-04-15 | 2003-10-16 | International Business Machines Corporation | Data forwarding by host/PCI-X bridges |
| US20040093438A1 (en) * | 2002-11-07 | 2004-05-13 | Odom Brian Keith | DMA device configured to configure DMA resources as multiple virtual DMA channels for use by I/O resources |
| US20040225822A1 (en) * | 2003-05-08 | 2004-11-11 | Fujitsu Limited | Bus connection circuit and bus connection system |
-
2005
- 2005-10-14 CN CNB2005101137587A patent/CN100392621C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5675793A (en) * | 1992-09-30 | 1997-10-07 | Microsoft Corporation | Dynamic allocation of a common buffer for use by a set of software routines |
| EP1246072A1 (en) * | 2001-03-27 | 2002-10-02 | Intel Corporation | Adaptive read pre-fetch |
| US20030037198A1 (en) * | 2001-08-20 | 2003-02-20 | Hunsaker Mikal C. | Dynamic delayed transaction buffer configuration based on bus frequency |
| US20030196020A1 (en) * | 2002-04-15 | 2003-10-16 | International Business Machines Corporation | Data forwarding by host/PCI-X bridges |
| US20040093438A1 (en) * | 2002-11-07 | 2004-05-13 | Odom Brian Keith | DMA device configured to configure DMA resources as multiple virtual DMA channels for use by I/O resources |
| US20040225822A1 (en) * | 2003-05-08 | 2004-11-11 | Fujitsu Limited | Bus connection circuit and bus connection system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1744060A (en) | 2006-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6202107B1 (en) | Host controller interface descriptor fetching unit | |
| US5644787A (en) | Apparatus for controlling data transfer between external interfaces through buffer memory using table data having transfer start address transfer count and unit selection parameter | |
| US7761642B2 (en) | Serial advanced technology attachment (SATA) and serial attached small computer system interface (SCSI) (SAS) bridging | |
| US5768622A (en) | System for preemptive bus master termination by determining termination data for each target device and periodically terminating burst transfer to device according to termination data | |
| US9128633B2 (en) | Semiconductor memory device and method of operating the semiconductor memory device | |
| CN104965678A (en) | Solid-state storage control method and apparatus and solid-state storage device | |
| CN102918515A (en) | Storing data in any of a plurality of buffers in a memory controller | |
| US6782463B2 (en) | Shared memory array | |
| CN104765701A (en) | Data access method and device | |
| CN115599733A (en) | Circuit, method and device for expanding multi-path serial port and terminal equipment | |
| CN113056729A (en) | Programming and control of computational cells in an integrated circuit | |
| US8209453B2 (en) | Arbiter, a system and a method for generating a pseudo-grant signal | |
| CN100392621C (en) | Bus controller and data buffer space allocation method | |
| US20030037198A1 (en) | Dynamic delayed transaction buffer configuration based on bus frequency | |
| US20100257289A1 (en) | Dma controller, information processing device and dma management method | |
| US7916146B1 (en) | Halt context switching method and system | |
| US20040153589A1 (en) | Device and method for controlling data transfer | |
| CN115878517A (en) | Memory device, operation method of memory device, and electronic device | |
| US7472212B2 (en) | Multi CPU system | |
| CN107085557A (en) | Direct memory access system and associated method | |
| US7050059B2 (en) | Method for a graphics chip to access data stored in a system memory of a computer device | |
| US6240474B1 (en) | Pipelined read transfers | |
| US20030056072A1 (en) | System and method for providing data to multi-function memory | |
| US8209449B2 (en) | Method for enabling several virtual processing units to directly and concurrently access a peripheral unit | |
| JP4737702B2 (en) | Disk array controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |