CN100372100C - Mfg. method capable of using automatic aligncing matellic silicate mask type read-only memory - Google Patents
Mfg. method capable of using automatic aligncing matellic silicate mask type read-only memory Download PDFInfo
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- CN100372100C CN100372100C CNB2004100892429A CN200410089242A CN100372100C CN 100372100 C CN100372100 C CN 100372100C CN B2004100892429 A CNB2004100892429 A CN B2004100892429A CN 200410089242 A CN200410089242 A CN 200410089242A CN 100372100 C CN100372100 C CN 100372100C
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- metal silicide
- semiconductor substrate
- memory cell
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- 238000000034 method Methods 0.000 title claims description 29
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 40
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 40
- 150000004767 nitrides Chemical class 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000010276 construction Methods 0.000 claims description 23
- 239000002019 doping agent Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 230000000712 assembly Effects 0.000 abstract 1
- 238000000429 assembly Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000000059 patterning Methods 0.000 description 9
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The present invention provides a manufacturing method of a mask type read-only memory by using a self-aligned metal silicide. With the requirement of gradual increase of the operating rate of logical regions, a residual nitride layer is used for protecting an embedded type doped region of a memory cell region so as to avoid the short circuit of all embedded type bit lines caused by a metal silicide region when the self-aligned metal silicide is formed, the short circuit can influence operation and electrical properties between transistors, current leakage and breakdown are produced, and thus, assemblies cannot normally operate.
Description
Technical field
The present invention relates to a kind of mask ROM, particularly close the manufacture method of using automatic aligning metal silicide mask ROM a kind of.
Background technology
Mask ROM (Mask Read Only Memory, MROM) be a kind of nonvolatile memory IC, be a kind of mask (Mask) planning memory document content (Program) of in LSI chip manufacturing engineering, utilizing, then give the memory storage that permanent storage is got off.
It is by not needing write activity, whole circuit constitutes comparatively simple, and basic unit of storage is also very simple, only constituted by a MOS transistor npn npn (MOS Transistor), with internal memory (the Random AccessMemory that can rewrite memory information at any time, RAM) compare down, it only is its 1/4th size, so with regard to the chip of identical size, the MROM memory capacity is about about four times of RAM, so very economical, thereby be widely used in electronic products such as various information, communication, consumer electronics.
When the production of internal memory enters into deep-sub-micrometer technology, the integration of integrated circuit is more and more high, the size of assembly is more and more little, in order to reduce component string connecting resistance value, to reduce Metal Contact window number, and the convenience of the follow-up connection lead layout of increase (Layout), the use of aiming at the metal silicide technology automatically is widely used in the semiconductor technology gradually.But, with regard to mask ROM, traditional automatic aligning metal silicide technology can't be useful in the manufacturing mask ROM, this is because the automatic aligning metal silicide region in silicon substrate can cause all flush types (BN+) bitline short circuits, produce problems such as leakage current, and have influence between MOS transistor operation with electrically, make the assembly can't normal operation.
So, the present invention is directed to above-mentioned problem and propose a kind of manufacture method of using automatic aligning metal silicide mask ROM, be combined in the manufacturing process of a ROM mask programmable read-only memory reading memory with aiming at metal silicide automatically, with the arithmetic speed of effective lifting logic circuit area, and effectively avoid aiming at automatically metal silicide to the memory cell areas embedded type bit line the injury that may cause.
Summary of the invention
Main purpose of the present invention, a kind of manufacture method of using automatic aligning metal silicide mask ROM is being provided, it can effectively be combined in the technology of mask ROM aiming at metal silicide automatically, and exempt to form when aiming at metal silicide automatically, may be to the injury that embedded type bit line produced of memory cell areas.
Another object of the present invention is providing a kind of manufacture method of using automatic aligning metal silicide mask ROM, and it can effectively improve the logic transistor usefulness of mask ROM.
For reaching above-mentioned purpose, the invention provides a kind of manufacture method of using automatic aligning metal silicide mask ROM, it includes the following step: a Semiconductor substrate that has formed a plurality of isolation structures on it is provided, and wherein a plurality of isolation structures are defined as logic region and memory cell region with Semiconductor substrate; With a photomask is mask, forms embedded type bit line in memory cell region; Partly leading a plurality of polysilicon gate construction respectively of formation on the bottom substrate in logic region and memory cell region; Described polysilicon gate construction with logic region is a mask, and this logic region is carried out the shallow ion doping process; On Semiconductor substrate, form the mononitride layer, then nitride layer is carried out a flatening process; Nitride layer is carried out etching, and to form a sidewall spacers thing and a remaining nitride thing layer respectively in the polysilicon gate construction two side, remaining nitride thing layer position is on the Semiconductor substrate between two polysilicon gate constructions; Remove the remaining nitride thing layer of logic region; Be mask with the polysilicon gate construction of logic region and polysilicon gate construction, sidewall spacers thing and the remaining nitride thing layer of sidewall spacers thing and memory cell region respectively, Semiconductor substrate is carried out the heavy ion doping process; And double conductive substrate carried out an automatic metal silicide technology of aiming at.
The manufacture method of using automatic aligning metal silicide mask ROM of the present invention; it utilizes the protection of remaining nitride thing layer and covers the active region of position in memory cell; make follow-up when aiming at metal silicide automatically; can avoid aiming at automatically the influence of metal silicide, and reach the running speed that metal silicide promotes logic transistor significantly of aiming at automatically of utilizing embedded type bit line.
Description of drawings
Further specify architectural feature of the present invention and beneficial effect thereof below in conjunction with preferred embodiment and accompanying drawing.
Fig. 1 to Fig. 8 is each step structure cutaway view of the present invention.
Label declaration
10 Semiconductor substrate
12 isolation structures
14 logic regions
16 memory cell region
18 dopant wells
20 dopant wells
22 imbed bit line
24,25 polysilicon gate constructions
26 second patterning light group layers
28 shallow doped regions
30,31 side wall spacer
32,33 remaining nitride thing layers
34 heavy ion doped regions
36 aim at metal silicide automatically
Embodiment
Can use the manufacture method of automatic aligning metal silicide mask ROM, at first, as Fig. 1, one Semiconductor substrate 10 that has defined logic region 14 and memory cell region 16 on it by a plurality of isolation structures 12 is provided, and the dopant well 18 of this memory cell region 16 is a P type dopant well, and the dopant well 20 in logical operation zone can be P type dopant well or N type dopant well.
Then, as Fig. 2, be that mask is with suitable N with photomask (Mask)
+Ion is implanted in the memory cell region 16 of Semiconductor substrate 10, forms doping region in embedding type (buried diffusion layer), with as imbedding bit line 22, finishes the step of planning memory document.
On Semiconductor substrate 10, form a plurality of polysilicon gate constructions 24,25, its step comprises and forms a gate oxide level (not showing in the drawings) in regular turn, one polysilicon layer (not showing in the drawings), on polysilicon layer, form one first patterning light group layer (not showing in the drawings), with the first patterning light group layer is mask, polysilicon layer and gate oxide level are carried out etching, to form each difference position of plural number at the polysilicon gate construction of logic region and the polysilicon gate construction 24 of memory cell region, 25, remove the first patterning light group layer then, form structure as shown in Figure 3.
See also shown in Figure 4, form one second patterning light group layer 26 in memory cell region 16, then the polysilicon gate construction 25 with logic region 14 is a mask, logic cells area 14 is carried out light ion source/drain electrode doping process, to form shallow doped region 28 (LDD), remove the second patterning light group layer 26 subsequently.
Then, as shown in Figure 5, utilize chemical vapour deposition technique on Semiconductor substrate 10, to deposit the mononitride layer, nitride layer is carried out a cmp, in the hope of comprehensive smooth, utilize the characteristic of dry type anisotropic etching then, with the nitride thickness that is deposited is that benchmark carries out etching, with at polysilicon gate construction 24,25 two sides are the height place formation side wall spacer 30 of half approximately, 31, but be noted that at this this moment is at two polysilicon gate constructions 24, still be coated with a remaining nitride thing layer 32 on 25 Semiconductor substrate 10 surfaces, 33, structure as shown in Figure 5.
On Semiconductor substrate, form one the 3rd patterning light group layer (not showing in the drawings), with the 3rd patterning light group layer is mask, contraposition is carried out etching at the remaining nitride thing layer 33 of logic region 14, to remove this remaining nitride thing layer 33, form configuration state as shown in Figure 6, remove the 3rd patterning light group layer then.
Then; Semiconductor substrate 10 is carried out a heavy ion source/drain electrode doping process; heavy ion source/drain electrode doping process of this moment; for logic region 14; be to be mask with side wall spacer 31 with polysilicon gate construction 25; and memory cell region 16 is with polysilicon gate construction 24; side wall spacer 30 is a mask with remaining nitride thing layer 32; to form heavy ion doped region 34; as shown in Figure 7; then; deposition one material is the metal level of titanium or cobalt etc. on Semiconductor substrate 10; again Semiconductor substrate 10 is annealed; make metal level and the polysilicon gate construction 24 that is contacted; 25 silicon atom forms automatic aligning metal silicide 36; form structure as shown in Figure 8; this moment is because there are 32 layers of protection of remaining nitride thing in the embedded type bit line zone 22 of memory cell; so will can not generate and aim at metal silicide automatically with the metal level reaction; utilize the mode of wet type optionally the unreacted metal layer to be removed subsequently; promptly obtain at polysilicon gate 24; 25 surfaces form tool and aim at the mask ROM of metal silicide 36 structures automatically, as shown in Figure 8.
In sum; the manufacture method of using automatic aligning metal silicide mask ROM that the present invention provides; it utilizes a remaining nitride layer effectively to protect the active region of memory cell region; to be used to increase the logic transistor operational effectiveness; avoid simultaneously aiming at automatically metal silicide the problems such as bitline short circuits of imbedding that may cause; so that increase and do not influence under the operation and electrical prerequisite of memory cell transistor in the assembly integration; make automatic aligning metal silicide technology applicable in the mask ROM technology, and common short circuit problem can not take place.
Above-described embodiment is only in order to illustrate technological thought of the present invention and characteristics; its purpose makes those of ordinary skill in the art can understand content of the present invention and is implementing according to this; the scope of this patent also not only is confined to above-mentioned specific embodiment; be all equal variation or modifications of doing according to disclosed spirit, still be encompassed in protection scope of the present invention.
Claims (7)
1. the manufacture method that can use automatic aligning metal silicide mask ROM, it comprises the following steps:
Semi-conductive substrate is provided, and is to have formed a plurality of isolation structures on this Semiconductor substrate, to define logic region and memory cell region;
With a mask is mask, and this memory cell region is carried out ion doping technology, imbeds bit line to form one;
On this Semiconductor substrate, form a plurality of positions respectively at the polysilicon gate construction of this logic region and this memory cell region;
This polysilicon gate construction with this logic region is a mask, and this logic region is carried out the shallow ion doping process;
On Semiconductor substrate, form the mononitride layer, then this nitride layer is carried out a flatening process;
This nitride layer is carried out etching, and to form a sidewall spacers thing and a remaining nitride thing layer respectively in the polysilicon gate construction two side, this remaining nitride thing layer is to cover on the semiconductor substrate surface;
Remove the remaining nitride thing layer of this logic region, to expose the semiconductor substrate surface of position between the logic region polysilicon gate construction;
Is mask with this polysilicon gate construction of logic region and this sidewall spacers thing with this polysilicon gate construction, this sidewall spacers thing and this remaining nitride thing layer with memory cell region, and this Semiconductor substrate is carried out the heavy ion doping process; And
This Semiconductor substrate is carried out one automatically aim at metal silicide technology, above these polysilicon gate constructions of logic region and memory cell region, forming the automatic metal silicide of aiming at,
Wherein, aiming at metal silicide technology automatically comprises the following steps:
Deposition one metal level on this Semiconductor substrate;
This Semiconductor substrate is carried out an annealing process, aim at metal silicide automatically so that form one with this metal level reaction with the silicon atom at this metal level place of connecing; And
Remove unreacted this metal level.
2. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1, it is characterized in that: the dopant well of described memory cell region is a P type dopant well, and the dopant well in logical operation zone is P type dopant well or N type dopant well.
3. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1 is characterized in that: the generation type of described nitride layer is to deposit by chemical vapour deposition technique to form.
4. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1 is characterized in that: when this nitride layer was carried out etching, the etching mode that is adopted was a dry etching.
5. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1 is characterized in that: the material of described metal level is titanium or cobalt.
6. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1, it is characterized in that: the described technology of imbedding bit line is, this dopant ion is implanted the substrate of the memory cell region of exposing, and form this embedded type bit line, and this dopant ion is the N+ admixture.
7. the manufacture method of using automatic aligning metal silicide mask ROM according to claim 1 is characterized in that: the step of described removal unreacted metal layer is to utilize the mode of wet etching optionally to remove.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100892429A CN100372100C (en) | 2004-12-08 | 2004-12-08 | Mfg. method capable of using automatic aligncing matellic silicate mask type read-only memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100892429A CN100372100C (en) | 2004-12-08 | 2004-12-08 | Mfg. method capable of using automatic aligncing matellic silicate mask type read-only memory |
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| CN1787205A CN1787205A (en) | 2006-06-14 |
| CN100372100C true CN100372100C (en) | 2008-02-27 |
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| CNB2004100892429A Expired - Fee Related CN100372100C (en) | 2004-12-08 | 2004-12-08 | Mfg. method capable of using automatic aligncing matellic silicate mask type read-only memory |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465326B (en) * | 2008-12-30 | 2012-08-29 | 上海宏力半导体制造有限公司 | Method for manufacturing mask ROM |
| CN101459138B (en) * | 2008-12-30 | 2012-08-29 | 上海宏力半导体制造有限公司 | Manufacturing method for mask read only memory device |
| CN104701320A (en) * | 2013-12-10 | 2015-06-10 | 上海华虹宏力半导体制造有限公司 | Structure of mask read-only memory with low gate resistance and manufacturing method thereof |
| CN109003978A (en) * | 2017-06-07 | 2018-12-14 | 北京兆易创新科技股份有限公司 | The preparation method and memory of memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413861B1 (en) * | 2001-04-18 | 2002-07-02 | Macronix International Co. Ltd. | Method of fabricating a salicide of an embedded memory |
| CN1420542A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. semiconductor devcie used in system chip |
| CN1423319A (en) * | 2001-09-05 | 2003-06-11 | 东部电子株式会社 | Method for making silicide film of plane unit storage element |
| CN1426099A (en) * | 2001-12-11 | 2003-06-25 | 旺宏电子股份有限公司 | Method for forming embedded non-volatile memory |
| CN1472798A (en) * | 2002-08-02 | 2004-02-04 | ���Ӱ뵼������˾ | Producing method for shielded read-only memory with self-aligning metal silicide |
| CN1472796A (en) * | 2002-08-02 | 2004-02-04 | ���Ӱ뵼������˾ | Method for forming metal silicide in shielded read-only memory |
-
2004
- 2004-12-08 CN CNB2004100892429A patent/CN100372100C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413861B1 (en) * | 2001-04-18 | 2002-07-02 | Macronix International Co. Ltd. | Method of fabricating a salicide of an embedded memory |
| CN1423319A (en) * | 2001-09-05 | 2003-06-11 | 东部电子株式会社 | Method for making silicide film of plane unit storage element |
| CN1420542A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. semiconductor devcie used in system chip |
| CN1426099A (en) * | 2001-12-11 | 2003-06-25 | 旺宏电子股份有限公司 | Method for forming embedded non-volatile memory |
| CN1472798A (en) * | 2002-08-02 | 2004-02-04 | ���Ӱ뵼������˾ | Producing method for shielded read-only memory with self-aligning metal silicide |
| CN1472796A (en) * | 2002-08-02 | 2004-02-04 | ���Ӱ뵼������˾ | Method for forming metal silicide in shielded read-only memory |
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| CN1787205A (en) | 2006-06-14 |
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