CN100368593C - Annealing technique for eliminating titanium nitride film stress and decreasing film resistance - Google Patents
Annealing technique for eliminating titanium nitride film stress and decreasing film resistance Download PDFInfo
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- CN100368593C CN100368593C CNB200410066529XA CN200410066529A CN100368593C CN 100368593 C CN100368593 C CN 100368593C CN B200410066529X A CNB200410066529X A CN B200410066529XA CN 200410066529 A CN200410066529 A CN 200410066529A CN 100368593 C CN100368593 C CN 100368593C
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Abstract
The present invention discloses an annealing technology method for eliminating MOCVD TiN film stress and decreasing film resistance, which anneals a silicon wafer of an MOCVD TiN film which is deposited already. By that the silicon wafer is annealed in specified parameter mixed gas atmosphere of nitrogen gas and hydrogen gas, the present invention can eliminate C, O, etc. in a blocking layer in a through hole under a low temperature, and reduce the thickness of the blocking layer on one side wall, which decreases the resistance of the through hole and reduces the stress of the blocking layer under the condition that the thermal induction of a metal strip is ineffective. The present invention can be used in the manufacture of a chip of an integrated circuit.
Description
Technical field
The present invention relates to the method for annealing in the integrated circuit (IC) chip manufacturing, particularly relate to the method for annealing of a kind of TiN of elimination membrane stress, reduction membrane resistance.
Background technology
In the aluminum metal interconnection technique, preparation TiN blocking layer is the prerequisite of preparation W through hole and Al film.The TiN layer can not only prevent WP
6And SiO
2Deng the reaction of medium layer, can also strengthen the bonding strength of tungsten plug, Al metallic membrane and medium layer, can the quality of its quality normally be filled with direct influence to tungsten plug and Al film.
At present, the preparation on TiN blocking layer has following several:,
Physical vapour deposition (PVD Physical Vapour Deposition) titanium and titanium nitride duplicature barrier layer deposition method, chemical vapor deposition (CVD Chemical Vapour Deposition) titanium and titanium nitride duplicature barrier layer deposition method, atomic layer deposition (ALD Atomic layerDeposition) titanium nitride barrier layer deposition process, and organometallics chemical vapor deposition (MOCVD Metal Organic Chemical Vapour Deposition) titanium and titanium nitride duplicature barrier layer deposition method.
MOCVD TiN barrier layer deposition method realizes the TiN deposit by following process:
At first realize the TiN deposit by following reaction formula;
Ti[N (CH
3)
2]
4=TiN+HN (CH
3)
2+ other hydrocarbons (hydrocarbon polymer);
Temperature of reaction＜400 ℃.
The hybrid plasma in-situ treatment of usefulness hydrogen and nitrogen is removed the impurity such as C, O in the film after the TiN deposit is intact.
This method can make the comprehensive growth in deep hole of TiN film, the film that grows in the bottom in hole, the blocking layer that sidewall all forms good spreadability, can effectively improve metal interconnected productive rate, be particularly suitable for growing film in the hole of complex geometry, and desired reaction temperature be low.This technology has obtained very big application in recent years.
The shortcoming of this method is to contain impurity such as higher C, O in the film, causes through hole resistance to exceed 10%～15% when free from foreign meter, and the film quality is more loose, membranous less stable.When film is exposed in the air, because O
2, CO
2The top layer that can diffuse into film Deng gas rapidly forms compound, cause sheet resistance in time passing and increase.The annealing process temperature of existing removal impurity is all higher, generally is about 690 ℃, causes the metal strip thermal induction to lose efficacy easily.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of MOCVDTiN of elimination membrane stress, reduces the method for annealing of membrane resistance, it can be in low-temperature condition goes down membrane removal impurity such as C, O, eliminate stress, the reduction sheet resistance of TiN film, avoid causing the metal strip thermal induction to lose efficacy.
For solving the problems of the technologies described above, elimination MOCVD TiN membrane stress of the present invention, reduce the method for annealing of membrane resistance, the silicon chip to the intact MOCVDTiN film of deposit carries out anneal, and the pressure-controlling of nitrogen and hydrogen gas mixture is 10Tor～25Tor in the annealing furnace; The volume ratio of nitrogen and hydrogen is controlled to be 1: 0.5～and 1: 5; Annealing time is 30S～90S: heat-up rate is 70 ℃/s; Annealing temperature is 400 ℃～500 ℃.
Present method is not made any change to original hardware device, and annealing temperature is 400 ℃～500 ℃, and the pressure-controlling of nitrogen and hydrogen gas mixture exists: in 10Tot～25Tor.Because the pressure of reaction cavity is higher, nitrogen and hydrogen gas mixture are very capable to the hole internal diffusion, nitrogen in the hole and hydrogen gas mixture can keep higher concentration, thereby at low temperatures, also can remove C, O impurity in the TiN film, do not damage the TiN film, and can reduce metal fever and induce the damage that causes.Annealing process of the present invention need not produce plasma gas, can alleviate because the device damage that causes of plasma treatment, reduces the hydrogen in the MOCVD reaction chamber and the mixing plasma gas treatment time of nitrogen.
Embodiment
At first adopt photoetching, etching technics to prepare required metal interconnected through hole, then carry out the deposit of MOCVDTiN film, in MOCVD, finish TiN preparation after, silicon chip enters annealing furnace and carries out aftertreatment.Feed nitrogen and hydrogen treat gas in annealing furnace, the pressure-controlling of annealing furnace nitrogen and hydrogen gas mixture is 10Tor～25Tot; The volume ratio of nitrogen and hydrogen is controlled to be 1: 0.5～and 1: 5; Annealing time is 30S～90S (annealing time is 60S in a specific embodiment); Heat-up rate is 70 ℃/S; Annealing temperature is 400 ℃～500 ℃ (annealing temperature is 450 ℃ in a specific embodiment).Keep for some time that TiN is fully handled.After disposing, annealing furnace cools to normal value, last exhaust.
Handle through after annealing, film produces recrystallization and thermal backflow, become comparatively fine and close, planeness and electrical property improve: utilize the impurity such as C, O in nitrogen and the hydrogen gas mixture removal TiN film, C in the sidewall film, O foreign matter content by 20% be reduced to 10%, C, O foreign matter content in the bottom film be reduced to 3% by 5%, thereby eliminate the TiN membrane stress, reduce sheet resistance, make membranous more stable.It is about 10% that the TiN thickness can reduce, and resistance can reduce about 20%.
Claims (2)
1. method for annealing of eliminating MOCVD TiN membrane stress, reducing membrane resistance carries out anneal to the silicon chip of the intact MOCVDTiN film of deposit, and it is characterized in that: the regulation range of the pressure of nitrogen and hydrogen gas mixture is 10Tor～25Tor in the annealing furnace; The volume ratio of nitrogen and hydrogen is controlled to be 1: 0.5～and 1: 5; Annealing time is 30S～90S; Heat-up rate is 70 ℃/S; Annealing temperature is 400 ℃～500 ℃.
2. the method for annealing of elimination MOCVD TiN membrane stress as claimed in claim 1, reduction membrane resistance, it is characterized in that: annealing time is 60S, annealing temperature is 450 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410066529XA CN100368593C (en) | 2004-09-21 | 2004-09-21 | Annealing technique for eliminating titanium nitride film stress and decreasing film resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410066529XA CN100368593C (en) | 2004-09-21 | 2004-09-21 | Annealing technique for eliminating titanium nitride film stress and decreasing film resistance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1752282A CN1752282A (en) | 2006-03-29 |
| CN100368593C true CN100368593C (en) | 2008-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410066529XA Expired - Fee Related CN100368593C (en) | 2004-09-21 | 2004-09-21 | Annealing technique for eliminating titanium nitride film stress and decreasing film resistance |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446841B (en) * | 2011-11-07 | 2016-08-03 | 上海华力微电子有限公司 | A kind of preparation method of low stress metal hard mask layer |
| CN102709232A (en) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Preparation method for metal hard mask layer applied to copper interconnection |
| CN104347487A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN103426819A (en) * | 2013-08-27 | 2013-12-04 | 上海华力微电子有限公司 | Method for preparing interconnection structure of metal hard mask layer and copper |
| CN105810588B (en) * | 2016-03-22 | 2018-11-30 | 中国科学院微电子研究所 | The preparation method of grid technique MOS device after a kind of |
| WO2020239718A1 (en) * | 2019-05-27 | 2020-12-03 | Ab Sandvik Coromant | A coated cutting tool |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207557B1 (en) * | 1998-07-22 | 2001-03-27 | Samsung Electronics Co., Inc. | Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same |
| CN1405845A (en) * | 2001-08-21 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing titanium oxide layer |
-
2004
- 2004-09-21 CN CNB200410066529XA patent/CN100368593C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207557B1 (en) * | 1998-07-22 | 2001-03-27 | Samsung Electronics Co., Inc. | Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same |
| CN1405845A (en) * | 2001-08-21 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing titanium oxide layer |
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| CN1752282A (en) | 2006-03-29 |
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Effective date of registration: 20171218 Address after: Zuchongzhi road 201203 Shanghai Pudong New Area Zhangjiang High Tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Granted publication date: 20080213 Termination date: 20180921 |