CN100364069C - Packaging annealing method based on gallium nitride material - Google Patents
Packaging annealing method based on gallium nitride material Download PDFInfo
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- CN100364069C CN100364069C CNB2004101018719A CN200410101871A CN100364069C CN 100364069 C CN100364069 C CN 100364069C CN B2004101018719 A CNB2004101018719 A CN B2004101018719A CN 200410101871 A CN200410101871 A CN 200410101871A CN 100364069 C CN100364069 C CN 100364069C
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Abstract
The present invention particularly relates to a packaging annealing method which is applied to materials based on gallium nitride. The present invention relates to the technical field of the technology of a semiconductor device. The present invention comprises the following steps: step 1, forming an electric beam marker and a source leaking metal region by optical etching to depositing ohmic contact metal; step 2, depositing a SiN or SiO medium film of which the thickness is 3000 A on the metal; step 3, annealing, and temperature in a range of 700 to 730 DEG C; step 4, removing the SiN or SiO medium film by an etch medium; step 5, injection and separation; step 6, etching a grid plate by electric beam light; step 7, evaporating grid metal; step 8, wiring.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly a kind of annealing encapsulated method that is applied to based on gallium nitride material.
Background technology
In the middle of semiconductor device and integrated circuit production technology, need often carry out annealing process.Annealing process mainly is to form to electrically contact the interface between semiconductor and metal, i.e. ohmic contact interface, and this technical process also is known as process annealing or sintering.In gallium nitride HFET device making technics, annealing process usually is used for realizing the ohmic contact of the source and drain areas of device.
For field-effect transistor, the grid length of device plays crucial effect to Devices Characteristics (especially high frequency characteristics).And for X-band GaN HFET device, the long requirement of grid reaches pattern of sub-micron level.At present, electron beam lithography (being also referred to as the e-beam direct-writing exposure technology) technology has the high and alignment precision advantages of higher of resolution, is the method for a kind of maturation and stable formation sub-micron lines.The e-beam direct-writing exposure technology does not realize the concrete reticle that common photoetching is required, and it is directly to read layout data from computer, according to the domain that designs on computers, as doing the picture required figure that draws with pen on substrate.This " pen " is exactly the electron beam that electron beam adhesive is reacted.E-beam direct-writing exposure can be made the fine lines of 0.1 micron even tens nanometers, and because has high overlay alignment precision by computer control.
Yet the basis that electron beam lithography technology has above-mentioned advantage is that high-quality electron beam overlay mark will be arranged, and makes the other parts of electron beam lithography figure and device realize accurate alignment.The electron beam overlay mark is produced on the backing material prior to electron beam lithography, and its effect is similar to the ordinary optical photoetching, be make the electron-beam direct writing figure with substrate on figure carry out accurate localization.Electron-beam lithography system is that the surface of good pattern will be arranged for the basic demand of overlay mark, because electron-beam lithography system is to rely on the electronic signal of mark metal surface reflection to recognize mark position.If the quality of electron beam overlay mark can not reach standard, cause the big hand useful signal of noise signal in the signal of mark metallic reflection, electron-beam lithography system can not accurately be recognized mark position.Electron beam lithography technology can not be carried out smoothly this moment, even all that has been achieved is spoiled to make ready-made work.Therefore the making of electron beam lithography mark is the basis in the X-band GaN HFET device technology.
Forming in the GaN HFET device technology of grid line bar with direct electronic beam writing technology of routine, for the accurate alignment of acquisition source leakage metal and grid, common processing step is as follows:
1. e-beam direct write lithography or ordinary optical photoetching, form the electron beam overlay mark, and evaporation mark metal, metal component is generally Ti/Au=200/1000 , and (to leak metal different with the source, can not form ohmic contact, but the high temperature that can stand to anneal and keep the pattern good);
2. (is benchmark with the electron beam overlay mark) e-beam direct write lithography source leakage graphic, and evaporating drain and source metals;
3. annealing makes the source leak metal and backing material forms good Ohmic contact;
4. active area isolation;
5. (is benchmark with the electron beam overlay mark) electron-beam direct writing is made the grid line bar, leaks metal with the source and realizes accurate alignment;
6. evaporate the grid metal.
As can be seen, electron beam exposure is that benchmark carries out accurate alignment with the alignment mark from above processing step.Though electron beam exposure has the high and high advantage of alignment precision of resolution, because it adopts direct writing technology, the time for exposure is longer relatively.In the 2nd step in above technology,, utilize direct electronic beam writing technology to carry out photoetching and will spend a large amount of time because source leakage graphic area is bigger.
But, make, utilize the source to leak metal simultaneously if all adopt ordinary optical to expose the step of the 1st, 2 in the above technology, only carry out the once electron beam alignment as electron beam mark metal, to save a large amount of process times, and can not sacrifice the advantage of e-beam direct-writing exposure.
Yet for GaN HFET device technology, metal ohmic contact is leaked in the source of the Al/Ti/Au of its use system, anneal under 700 ℃ to 800 ℃ even 900 ℃ of conditions, could form desirable ohmic contact.Under this temperature, the metallic surface pattern is leaked with general variation in the source, electron beam exposure system is normally recognized, thereby can't be carried out the photoetching of grid line bar again.
Summary of the invention
The invention relates to a kind of being applied in the gallium nitride semi-conducting material device making technics such as (GaN-Gallium Nitride); the method of solution electron beam exposure overlay mark protection when high annealing is the new process that forms in finishing country " 973 " problem " research of X-band GaN HFET (Hetero junction FieldEffect Transistor HFET) device " process.
To reduce the process time and form excellent marker metal surface this a pair of contradiction of pattern in order to solve, we have proposed a kind of effective method: be applied to the annealing encapsulated method based on mark metal coating in the electron beam exposure of broad stopband material devices such as gallium nitride.
The present invention is the annealing encapsulated method that is applied to based on gallium nitride material; mainly be electrically connected (source leakage ohmic contact) drain-source metal partly in the device simultaneously with the metal of marking with forming; having made mark metal and source at the same time leaks after the metal; deposition medium on the drain-source metal; carry out annealing process again, to reach the purpose of protection mark metal.This method is used for the making of HFET device, and specifically comprises the steps:
The key step of this method comprises:
1. ordinary optical method photoetching electron beam overlay mark and source leakage graphic; Evaporating drain and source metals, metal component are Al/Ti/Al/Ti/Au=200/300/900/400/800 (metal component when not taking the annealing encapsulated method is Al/Ti/Al/Ti/Au=200/300/900/400/2000A);
Optical lithography forms the electron beam mark and metal area is leaked in the source, deposition metal ohmic contact (Al/Ti/Au is a metal);
2. deposit SiN or Si0 deielectric-coating, thickness is 3000 ;
3. annealing, temperature is 700-730 ℃, makes the source leak metal and backing material formation good Ohmic contact;
4. be etched away SiN or SiO deielectric-coating;
5. active area isolation;
6. (leaking metal with electron beam overlay mark and source is benchmark) electron-beam direct writing is made the grid line bar, leaks metal with the source and realizes accurate alignment; Electron beam lithography grid version;
7. evaporate the grid metal;
8. wiring.
The annealing encapsulated method that this is applied to based on gallium nitride material is the method that is applied in the gallium nitride semiconductor material HFET device making technics.
Replace the mark metal with forming the metal that mainly is electrically connected (source leakage ohmic contact) part in the device, used metal is an Al/Ti/Au system.
To make mark metal and source simultaneously and leak metal.
Made mark metal and source at the same time and leaked after the metal, deposition SiN or SiO deielectric-coating on metal, thickness is 3000 , carries out annealing process then.
Carry out annealing process after deposition SiN or the SiO deielectric-coating on metal, temperature is 700-730 ℃.
By adopting the method for leaking deielectric-coating such as deposition SiN or SiO on the metal in the source, and choose suitable metal component, even after annealed, the source is leaked the metallic surface pattern and is still kept good, can be used as the electron beam overlay mark, recognized by electron-beam lithography system smoothly, and make annealing temperature reduce about 100 ℃ (temperature when same metal component is not taked encapsulating method annealing is 780-830 ℃).The method has been given full play to the advantage of electron beam lithography, and has reduced the process time, has improved operating efficiency.
The purpose of this method is; utilize the e-beam direct write lithography technology to reach in the middle of the GaN HFET device technology of accurate alignment at needs; a kind of method by deposition medium before annealing is provided; when substrate carries out annealing process, the method for the necessary overlay mark metal of protection e-beam direct-writing exposure.By this method, can make the source leak metal after annealing process, can obtain the good metal pattern, make it to substitute the overlay mark of e-beam direct-writing exposure, save the process time, shorten the effect of process cycle thereby reach.
Description of drawings
Being the effect that further specifies content of the present invention and can reach, is example and in conjunction with the implementation procedure (technological process) of caption annealing encapsulated method with GaN HFET technological process below, and the characteristics of annealing encapsulated method and advantage, wherein:
Fig. 1 is a GaN HFET process chart;
Fig. 2 is the pattern after the mark metal annealing;
Fig. 3 leaks metal for the source does not have the pattern after the annealing under the deposition medium situation;
Fig. 4 is for depositing the pattern after SiN or SiO deielectric-coating carry out annealing encapsulated on the source leakage metal;
Embodiment
Fig. 1 (a) is common processing step; (b) be annealing encapsulated method step of the present invention.
As can be seen, the common process flow process has more a step electron beam lithography source at least and leaks metal area from flow chart, and exposure area is far longer than the grid version, and the time of the electron beam exposure of this edition will be 2～3 times of grid version.
Represented among Fig. 2 is pattern after mark metal (Ti/Au=200/1000 ) annealing.
As can see from Figure 2, even the mark metal can also keep good pattern after annealing.This mark can be recognized smoothly by electron-beam lithography system.
Fig. 3 is that the source is leaked metal and do not carried out pattern after the annealing that medium seals.As can see from Figure 3, the source is leaked metal and is not being carried out under the situation that SiN or SiO deielectric-coating seal, and after the annealed technology, it is very coarse that the surface has become.Though at this moment can form good Ohmic contact, but can not be recognized by electron beam exposure system, can't be used for when marking metal.
Pattern among the figure behind expression source leakage metal (the serving as a mark simultaneously) annealing encapsulated.
Be that the pattern that carries out behind deposition SiN on the metal or the SiO deielectric-coating behind the annealing encapsulated is leaked in the source shown in Fig. 4, at this moment source leakage metal can form good Ohmic contact with Semiconductor substrate (as GaN), and pattern can be comparable with the mark metal of Fig. 2, can be used as the mark metal, and can be recognized smoothly by electron beam exposure system.
By the method for the protection mark metal after the application enhancements, can reduce the electron beam exposure step of a step-length time, make total electron beam exposure time decreased 60-70%.So significant effect has very important significance to whole process flow, and a kind of method of worth reference is provided for the industrialization of electron beam lithography.
Claims (2)
1. annealing encapsulated method that is applied to based on gallium nitride material, it is characterized in that, leak metal simultaneously with the metal of marking with the source that forms main electric connecting member in the device, having made mark metal and source at the same time leaks after the metal, leak deposition medium on the metal in the source, carry out annealing process again, this method is used for the making of HFET device, and specifically comprises the steps:
Step 1: optical lithography forms the electron beam mark and metal area is leaked in the source, the deposition metal ohmic contact;
Step 2: leak deposition SiN or SiO deielectric-coating on the metal in the source, thickness is 3000 ;
Step 3: annealing, temperature is 700-730 ℃;
Step 4: the etching medium removes SiN or SiO deielectric-coating;
Step 5: inject and isolate;
Step 6: electron beam lithography grid version;
Step 7: evaporation grid metal;
Step 8: wiring.
2. the annealing encapsulated method that is applied to based on gallium nitride material according to claim 1 is characterized in that, leaks metal simultaneously with the metal of marking with the source that forms main electric connecting member in the device, and used metal is an Al/Ti/Au system.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004101018719A CN100364069C (en) | 2004-12-30 | 2004-12-30 | Packaging annealing method based on gallium nitride material |
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| CNB2004101018719A CN100364069C (en) | 2004-12-30 | 2004-12-30 | Packaging annealing method based on gallium nitride material |
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| CN100364069C true CN100364069C (en) | 2008-01-23 |
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| CNB2004101018719A Expired - Fee Related CN100364069C (en) | 2004-12-30 | 2004-12-30 | Packaging annealing method based on gallium nitride material |
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| CN100495216C (en) * | 2006-09-22 | 2009-06-03 | 中国科学院微电子研究所 | Electron beam alignment mark manufacture method and its uses |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102285A (en) * | 1999-09-28 | 2001-04-13 | Toshiba Corp | Aligning mark |
| US6387574B1 (en) * | 1998-12-07 | 2002-05-14 | Hoya Corporation | Substrate for transfer mask and method for manufacturing transfer mask by use of substrate |
| CN1392592A (en) * | 2001-06-14 | 2003-01-22 | 中国科学院微电子中心 | Method for forming T-shaped gate with multilayer film and through once electronic beam exposure and multiple developing |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6387574B1 (en) * | 1998-12-07 | 2002-05-14 | Hoya Corporation | Substrate for transfer mask and method for manufacturing transfer mask by use of substrate |
| JP2001102285A (en) * | 1999-09-28 | 2001-04-13 | Toshiba Corp | Aligning mark |
| CN1392592A (en) * | 2001-06-14 | 2003-01-22 | 中国科学院微电子中心 | Method for forming T-shaped gate with multilayer film and through once electronic beam exposure and multiple developing |
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