CN100362592C - Semiconductor memory element and its control method - Google Patents

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode.

Description

The cell phone of semiconductor storage unit and method of operating thereof and this storer of use

The application is to be the dividing an application of Chinese patent application 01124583.2 in August 9 calendar year 2001 the applying date.

Technical field

The present invention relates to have the semiconductor storage unit of low power consumption mode.

Background technology

In recent years, mobile phone has not only had the acoustic communication function, and has the function that transmits string data or pictorial data.And, along with the variation of Internet service, wishing that mobile phone becomes a kind of information terminal (for example, portable personal computer) in the future.Therefore, increased considerably the data message amount that will be moved the phone processing.Conventionally, mobile phone has used the working storage SRAMs with about 4 megabit memory capacity.Working storage is to be used to keep essential memory of data in mobile phone operating period.Obviously, in the future, the memory capacity of working storage will be not enough.

On the other hand, improving the transfer rate of mobile phone.It is more little that mobile phone becomes, and the battery of assembling becomes more little.Therefore, the working storage that is used in the mobile phone need have at a high speed low power consumption and high capacity.In the serious price competition of mobile phone, it is necessary making the cost of parts become low as much as possible.Therefore, working storage has to have low price.

Be used in conventional SRAMs in the working storage on cost every to be higher than DRAMs.The production quantity of SRAMs makes to be difficult to reduce its price less than the quantity of DRAMs.And, never develop the have large storage capacity SRAMs of (for example, 64 megabits).

In this case, considered in the working storage of mobile phone, to replace SRAMs with flash (flash) storer and DRAMs.

In stand-by state, flash memory has low power consumption to a few μ W, but needs a few μ s to tens μ s to be used for write data.Therefore, when flash memory is used as the working storage of mobile phone, be difficult at full speed transmit/receive data.Flash memory is carried out write operation in the unit of sector, make it be not suitable for rewriteeing by turn pictorial data such as the active images data.

Otherwise DRAMs can carry out read operation and write operation in tens ns, and can easily handle the data of active images.Power consumption is higher than the power consumption of flash memory in stand-by state.In existing DRAMs, be used for keeping the self refresh mode of write data, the power consumption in the stand-by state is approximately 1mW, in not needing to keep the stand-by state of write data, is approximately 300 μ W.

If the power consumption in the stand-by state can reduce to the power consumption of flash memory, DRAMs can be used as the working storage of mobile phone, but never proposes described circuit engineering.

By stopping the power supply of DRAMs, the power consumption of DRAMs can be kept to zero.Yet because the End of Address of DRAMs, data terminal etc. connect the terminal of other electronic unit by the wiring diagram on the circuit board, for the termination of DRAMs power supply, need change system's (change in pattern of circuit board, rearrangement etc.) of mobile phone significantly.

And, stop power supply with the operation that stops the interior circuit in the stand-by state after, the technology that realization is withdrawed from from stand-by state during fault in not having to occur also is not proposed.

In the interior voltage in the generation of device the inside will be used in the circuit, when discharging from stand-by state (low power consumption mode), it must fast return arrive predetermined voltage.Yet this technology never was proposed.

Summary of the invention

The objective of the invention is to make device to enter the low power consumption mode and device is withdrawed from from the low power consumption mode reliably.

Another object of the present invention is to provide a kind of semiconductor storage unit and control method thereof, compare with conventional device, this device can reduce the current drain in the stand-by state significantly.

An also purpose of the present invention is to provide a kind of semiconductor storage unit and control method thereof, compares the current drain during this device can reduce between standby period significantly with conventional device.

Another object of the present invention is to make device easily enter into the low power consumption mode by the control signal of outside.

The wire current (or leak path) of circuit in another object of the present invention is in the low power consumption mode, stop.

An also purpose of the present invention is to make device easily enter into the low power consumption mode by using existing control signal.

Another object of the present invention is to make device easily enter into the low power consumption mode by the order input.

Another object of the present invention is to make device easily enter into the low power consumption mode by dedicated control signal.

Another object of the present invention is to fast return from the low consumpting power mode.

The control method of semiconductor storage unit aspect and this semiconductor storage unit of control according to the present invention, the self refresh control circuit is with the automatic updated stored of predetermined circulation unit.Interior voltage generator once receive outside supply voltage produce to be applied to be scheduled in the interior voltage of circuit.When receiving outside control signal, semiconductor storage unit stops the supply capacity that activates voltage generator in self refresh control circuit and the reduction, thereby enters into the low power consumption mode.When not needing the data of reserved storage location in the low power consumption mode, the operation of self refresh control circuit is unnecessary.Do not upgrade owing to carry out, interior voltage generator can be operated with the voltage that is enough to compensate by the electric power of interior circuitry consumes (leakage current).As a result, can reduce power consumption in the low power consumption mode.

Even voltage offers interior circuit in the low power consumption mode.Therefore, circuit can be operated immediately in after discharging from the low power consumption mode.

According to the present invention semiconductor storage unit on the other hand, interior voltage generator comprise be used to produce in a plurality of unit of voltage.In the low power consumption mode, a part of unit can be ended, the feasible power consumption that can further reduce in the low power consumption mode.

Semiconductor storage unit is answered the requirement of external control signal on the other hand according to the present invention, enters the generation that circuit stops the operation of stepup transformer and will be applied to the booster voltage of word line.In the low power consumption mode, stop to stablize the stepup transformer of consumption of electric power, make to reduce power consumption significantly.

Semiconductor storage unit is answered the requirement of external control signal on the other hand according to the present invention, enters the operation that circuit stops substrate voltage generator, to stop to be applied to the generation of suprabasil basic voltage.In the low power consumption mode, stop to stablize the substrate voltage generator of consumption of electric power, make to reduce power consumption significantly.

According to semiconductor storage unit of the present invention on the other hand, answer the requirement of external control signal, enter the operation that circuit stops interior power supply voltage generator, to stop to be applied to the generation of the interior supply voltage on the storage core.In the low power consumption mode, stop to stablize the interior power supply voltage generator of consumption of electric power, make to reduce power consumption significantly.

Semiconductor storage unit is answered the requirement of external control signal on the other hand according to the present invention, enters the operation that circuit stops the pre-charge voltage generator, to stop to be applied to the generation of the pre-charge voltage on the bit line.In the low power consumption mode, stop to stablize the pre-charge voltage generator of consumption of electric power, make to reduce power consumption significantly.

Semiconductor storage unit when from outside supply reset signal, stops and activates predetermined interior circuit on the other hand according to the present invention.Requirement that should reset signal enters circuit and makes device enter into the low power consumption mode.In reseting procedure, do not need to operate this device.Therefore, it can enter into the low power consumption mode by using existing signal.The type of exterior terminal and quantity are identical with conventional terminal, make that adding the low power consumption mode does not reduce availability.

Semiconductor storage unit enters circuit and receives a plurality of external control signals on the other hand according to the present invention.When the state that enters the circuit acknowledgement control signal was the order of low power consumption mode, it made device enter into the low power consumption mode.Therefore, can enter into the low power consumption mode by the order entering apparatus.

Semiconductor storage unit enters circuit and receives external reset signal and chip initiating signal on the other hand according to the present invention.When entering circuit and confirm that the state of these control signals is the low power consumption order, it makes device enter into the low power consumption mode.Therefore, can enter into the low power consumption mode by the order entering apparatus.

Semiconductor storage unit activate reset signal when stoping in the scheduled period, and in this state, when activating the chip initiating signal in the scheduled period, device enters into low power consumption mode kind on the other hand according to the present invention.Even because power supply noise etc. when glitch occurs in reset signal or the chip initiating signal, can stop device to enter into the low power consumption mode mistakenly.

Semiconductor storage unit enters circuit and receives a plurality of external control signals on the other hand in the low power consumption mode according to the present invention.When the level of control signal is indicated withdrawing from of low power consumption mode, enter circuit and from the low power consumption mode, withdraw from this device.Therefore, can from the low power consumption mode, withdraw from by the order entering apparatus.

Receive the predetermined level of low power consumption mode signal or conversion during the edge when entering circuit, it makes device enter into the low power consumption mode.Therefore, can enter reliably in the low power consumption mode by the application specific signal device.

The control that reaches this semiconductor storage unit on the other hand of semiconductor storage unit according to the present invention when the state of the control signal that receives is indicated withdrawing from of low power consumption mode, is withdrawed from the low power consumption mode in the low power consumption mode.This just allows easily to withdraw from from the low power consumption mode by the external control signal device.For example, enter circuit by control and carry out withdrawing from from the low power consumption mode.

The control that reaches this semiconductor storage unit on the other hand of semiconductor storage unit according to the present invention, after withdrawing from the low power consumption mode, interior voltage be lower than predetermined voltage during, activate be used for initial in the reset signal of circuit.For example, interior voltage be lower than by reduce reference voltage that supply voltage produces during, activate reset signal.Therefore, when the low power consumption mode was converted to normal mode of operation, interior circuit can reset reliably, the appearance of fault in stoping.

According to the present invention semiconductor storage unit on the other hand, after withdrawing from the low power consumption mode, the booster voltage that produces in inside be lower than predetermined voltage during, activate be used for initial in the reset signal of circuit.For example, booster voltage be lower than supply voltage during, activate reset signal.In addition, booster voltage be lower than by reduce reference voltage that supply voltage produces during, can activate reset signal.

According to the present invention semiconductor storage unit on the other hand, after withdrawing from the low power consumption mode, at least one that produces in inside voltage and booster voltage be lower than predetermined voltage separately during, activate be used for initial in the reset signal of circuit.Therefore, when the low power consumption mode was converted to normal mode of operation, interior circuit can reset reliably, and fault just occurs in stoping.

According to the present invention semiconductor storage unit on the other hand, when the low power consumption mode withdraws from, when timer is just measured predetermined time duration, activate be used for initial in the reset signal of circuit.This just allows when the low power consumption mode is converted to normal mode of operation, and interior circuit resets reliably, the appearance of fault in causing stoping.

According to the present invention semiconductor storage unit on the other hand, timer comprises the CR time constant circuit.On the basis in propagation delay time of the signal that propagates into the CR time constant circuit, the timer measuring duration, make and to be provided with between the active period of reset signal by ball bearing made using.

According to the present invention semiconductor storage unit on the other hand, when the low power consumption mode withdraws from, when with the rolling counters forward predetermined quantity of normal running operation, activate be used for initial in the reset signal of circuit.This just allows when the low power consumption mode is converted to normal mode of operation, and interior circuit resets reliably, the appearance of fault in causing stoping.For example, be used to indicate the refresh counter of the scheduler of storage unit etc. to be used as counter.

According to the present invention semiconductor storage unit on the other hand with the control method of this semiconductor storage unit, the stabilising condenser storage that connects power lead will be supplied to a part of electric charge of power lead.When receiving external control signal, semiconductor storage unit keeps being connected between power lead and stabilising condenser, but deenergization line and interior circuit, thereby enter into the low power consumption mode.Therefore, the power consumption of circuit can reduce to zero in the low power consumption mode.After discharging from the low power consumption mode, when power lead was connected with interior circuit, the voltage corresponding with electric charge in being stored in stabilising condenser was applied on the interior circuit by power lead.As a result, but discharging back semiconductor storage unit immediate operation from the low power consumption mode.

According to the present invention semiconductor storage unit on the other hand, interior voltage generator is voltage in receiving outside supply voltage generation.Interior voltage is applied on the interior circuit by power lead.Therefore, after discharging, in the voltage corresponding with electric charge in being stored in stabilising condenser can be fed on the circuit from the low power consumption mode.

According to the present invention semiconductor storage unit on the other hand with the control method of this semiconductor storage unit, interior voltage generator once receive outer power voltage produce to be applied to predetermined in the interior voltage of circuit.Interior voltage detector is surveyed the level of interior voltage and is controlled interior voltage generator according to its result of detection.The semiconductor storage unit that receives external control signal weakens the response of interior voltage detector, thereby enters into the low power consumption mode.The frequency of operation of the interior voltage generator of operation under the voltage detector control in the response of voltage detector causes being reduced in weakening.As a result, can reduce power consumption in the low power consumption mode.

The another way of semiconductor storage unit according to the present invention, interior voltage generator comprise a plurality of unit that are used to survey interior voltage level.In the low power consumption mode, their operation is ended in a part of unit, the feasible power consumption that can further reduce in this power consumption mode.

According to the present invention semiconductor storage unit on the other hand with the control method of this semiconductor storage unit, interior voltage generator once receive outer power voltage produce to be supplied to predetermined in interior voltage on the circuit.Interior voltage detector is surveyed the level of interior voltage and is controlled interior voltage generator according to its result of detection.The semiconductor storage unit of reception external control signal reduces the interior voltage detection level in the interior voltage detector and reduces the absolute value of the interior voltage of interior voltage generator generation, thereby enters into the low power consumption mode.Therefore, the driving force of voltage generator has reduced power consumption in can reducing.

According to the present invention semiconductor storage unit on the other hand, reference voltage generator produces reference voltage.By relatively interior voltage and reference voltage, the level of voltage in interior voltage detector is surveyed.The semiconductor storage unit that receives external control signal reduces the level of the reference voltage of reference voltage generator generation, thus the absolute value of the interior voltage detection level in the voltage detector in reducing.The absolute value of the interior voltage level in this has just caused reducing in the circuit and transistorized cut-off current etc., thus power consumption reduced.

According to the present invention semiconductor storage unit on the other hand with the control method of this semiconductor storage unit, the self refresh control circuit is with the automatic updated stored of predetermined circulation unit.When semiconductor storage unit received external control signal, it stops activated the self refresh control circuit and enters into the low power consumption mode.Do not upgrade owing in the low power consumption mode, carry out, can reduce the current sinking amount that is used to upgrade.

According to the present invention semiconductor storage unit on the other hand, the self refresh control circuit comprises the timer that is used for determine upgrading circulating continuancing time.Abort timer in the low power consumption mode makes to reduce power consumption.

The semiconductor storage unit control method receives outside a plurality of control signals on the other hand according to the present invention.When the state of device acknowledgement control signal was the low power consumption order, it entered into the low power consumption mode.Therefore, can enter into the low power consumption mode by the order entering apparatus.

According to the present invention the semiconductor storage unit control method on the other hand, when energized, the chip initiating signal keep to stop activates and to reach predetermined voltage up to supply voltage.This just stops mistake to enter the low power consumption mode possibility that becomes when energized.

Description of drawings

Work as connection with figures, by following detailed, essence of the present invention, principle and application will become clear, and similarly parts are pointed out with identical reference symbol in the accompanying drawings, wherein:

Fig. 1 is the state transition diagram of semiconductor storage unit of the present invention;

Fig. 2 is the block diagram that the first embodiment cardinal rule is shown;

Fig. 3 is the block diagram that first embodiment is shown;

Fig. 4 illustrates the stepup transformer of Fig. 3 and the circuit diagram of pre-charge voltage generator detail drawing;

Fig. 5 illustrates the interior power supply voltage generator of Fig. 3 and the circuit diagram of substrate voltage generator detail drawing;

Fig. 6 is the circuit diagram that the storage core essential part detail drawing of Fig. 3 is shown;

Fig. 7 illustrates first embodiment at power connection and the time diagram operated when entering and withdrawing from the low power consumption mode;

Fig. 8 is the block diagram that semiconductor storage unit that first embodiment is shown is used in the embodiment in the mobile phone;

Fig. 9 is the key diagram that the state of mobile phone that uses Fig. 8 is shown;

Figure 10 is the process flow diagram that the state of mobile phone of control chart 8 is shown;

Figure 11 is the block diagram that second embodiment is shown;

Figure 12 is the circuit diagram that low power supply that Figure 11 is shown enters the circuit detail drawing;

Figure 13 is the time diagram that low-power that Figure 12 is shown enters circuit operation;

Figure 14 is the block diagram that the 3rd embodiment is shown;

Figure 15 is the circuit diagram that the VII starter in the 4th embodiment is shown;

Figure 16 is the circuit diagram that the VII starter in the 4th embodiment is shown;

Figure 17 is the time diagram that the operation when entering and withdrawing from the low power consumption mode in the 4th embodiment is shown;

Figure 18 is the circuit diagram that the level detecting circuit in the 5th embodiment is shown;

Figure 19 is the time diagram that the operation when entering and withdrawing from the low power consumption mode in the 5th embodiment is shown;

Figure 20 is the circuit diagram that the initiating signal generator in the 6th embodiment is shown; And

Figure 21 is the time diagram that the operation when entering and withdrawing from the low power consumption mode in the 6th embodiment is shown;

Figure 22 is the block diagram that the 7th embodiment is shown;

Figure 23 is the circuit diagram that the reference signal generator detail drawing of Figure 22 is shown;

Figure 24 is the circuit diagram that the interior power supply voltage generator detail drawing of Figure 22 is shown;

Figure 25 illustrates stepup transformer, VPP detector, the block diagram of substrate voltage generator and VBB detector;

Figure 26 is the circuit diagram that the stepup transformer unit detail drawing of Figure 25 is shown;

Figure 27 is the circuit diagram that the stepup transformer unit detail drawing of Figure 25 is shown;

Figure 28 is the circuit diagram that the VPP detector detail drawing of Figure 22 is shown;

Figure 29 is the circuit diagram that the substrate voltage generator unit detail drawing of Figure 25 is shown;

Figure 30 is the circuit diagram that the substrate voltage generator unit detail drawing of Figure 25 is shown;

Figure 31 is the circuit diagram that the VBB detector detail drawing of Figure 22 is shown;

Figure 32 is the circuit diagram that the pre-charge voltage generator detail drawing of Figure 22 is shown;

Figure 33 is the circuit diagram that the oscillator detail drawing of Figure 22 is shown;

Figure 34 is the circuit diagram that the generator detail drawing of Figure 23 is shown; And

Figure 35 is the time diagram that oscillator in the 7th embodiment and frequency divider operation are shown.

Embodiment

With reference to the accompanying drawings embodiment of the present invention will be described.

Fig. 1 shows the state transition diagram of semiconductor storage unit of the present invention.

At first, semiconductor storage unit enters idle mode when energized.When receiving read command or write order in idle mode, this mode is converted to mode of operation, to carry out read operation or write operation.After carrying out read operation or write operation, idle mode is restored automatically.When being received from update command in idle mode, device enters the self refresh mode to carry out self refresh.In this self refresh mode, produce scheduler automatically and carry out the renewal operation with order in storage unit.

By the predetermined state of detectable signal in idle mode, semiconductor storage unit enters into the low power consumption mode.In the first following embodiment, the requirement of answering chip initiating signal CE2, device enters into the low power consumption mode.Particularly, by chip initiating signal CE2, stop predetermined interior circuit of activation and device to enter into the low power consumption mode.In the second following embodiment, should be by the requirement of the order of chip initiating signal/CE1 and CE2 input, device enters into the low power consumption mode.In the 3rd following embodiment, answer the requirement of special-purpose low power consumption mode signal/LP, device enters into the low power consumption mode.

In the low power consumption mode, the predetermined state of semiconductor storage unit detectable signal also withdraws from this mode.

Fig. 2 shows the cardinal rule of semiconductor storage unit of the present invention.

Semiconductor storage unit comprises and enters circuit 1, interior voltage generator 2, external power potential circuit 3 and interior circuit 4.

After energized, voltage in interior voltage generator 2 produces, and should supply with interior circuit 4 by interior voltage.Entering circuit 1 receives control signal and stop voltage generator 2 in the activation when it surveys the predetermined state of control signal.In stop activating, during voltage generator 2, stop the generation of interior voltage.At the same time, enter circuit 1 and activate external power potential circuit 3.Circuit 4 external power potential circuit 3 is supplied with supply voltage as interior voltage in.And semiconductor storage unit enters into the low power consumption mode.

Fig. 3 illustrates semiconductor storage unit first embodiment of the present invention and control method thereof.The semiconductor storage unit of this embodiment is formed on the p-type silicon substrate as DRAM by using the CMOS treatment technology.

DRAM is equipped with VII starter 10, VDD starter 12, and low-power enters circuit 14, command decoder 16, interior voltage generator 18 and main circuit unit 20.Interior voltage generator 18 has low pass filter 22, reference voltage generator 24, VDD charging circuit 26, stepup transformer 28, precharge generator 30, interior power supply voltage generator 32, substrate voltage generator 34 and VSS charging circuit 36.Main circuit unit 20 has storage core 38 and peripheral circuit 40.Here, what low-power entered that circuit 14 is equivalent to Fig. 2 enters circuit 1, and VDD charging circuit 26 and VSS charging circuit 36 are equivalent to external voltage charging (supply) circuit 3 of Fig. 2.

With outer power voltage VDD (for example 2.5V), ground voltage VSS, as the chip initiating signal/CE1 and the CE2 of control signal, a plurality of address signal AD, a plurality of data input/output signal DQ and another control signal CN supply with DRAM.DRAM does not adopt address multiplexer channel method.Therefore, supply primary address signal AD when each read operation and each write operation.The nearly all circuit except storage core 38 partial circuits with supply voltage VDD and ground voltage VSS supply.Here, the signal with letter "/" beginning is the signal of negative logic.In following, by omitting its signal name, " address signal AD " can be abbreviated as " AD signal ".

When carrying out read operation and write operation with activation DRAM ,/CE1 signal becomes low level.When in low level, the CE2 signal as reset signal with in main circuit unit 20, stop to activate predetermined in circuit.

Supply voltage VII and ground voltage VSS and initiating signal STTVII outputed to main circuit unit 20 in VII starter 10 receives.Behind power connection, reach predetermined voltage up to interior supply voltage VII, VII starter 10 main circuit unit 20 that resets, and it prevents the fault of main circuit unit 20.VDD starter 12 receives supply voltage VDD and ground voltage VSS and output initiating signal STTCRX.Reach predetermined voltage up to supply voltage behind power connection, VDD starter 12 stops the activation low-power to enter circuit 14, and it prevents the fault of circuit 14.

Low-power enters circuit 14 and receives initiating signal STTCRX and CE2 signal and activate low-power signal ULP.

Should/requirement of CE1 signal and another control signal CN, command decoder 16 decoding orders also will output to peripheral circuit 40 as this decoding order of interior command signal.

Low pass filter 22 has and leaches the function that is included in the noise among the supply voltage VDD.The supply voltage VDD that so disposes noise supplies with reference voltage generator 24 etc.In the low power consumption mode, the switch in low pass filter 22 is closed and supply voltage VDD is not supplied with reference signal generator 24, feasible not current sinking.

Reference voltage generator 24 receives supply voltage VDD and produces reference voltage VPREF (for example 1.5v), VPRREFL (for example 0.8V), VPRREFH (for example 1.2V) and VRFV (for example 2.0V).

In the low power consumption mode, VDD charging circuit 26 becomes booster voltage VPP and interior supply voltage VII into supply voltage VDD.

Stepup transformer 28 receives reference voltage VPREF and produces booster voltage VPP (for example 3.7V) and this booster voltage VPP is supplied with storage core 38.

Pre-charge voltage generator 30 receives reference voltage VPRREFL and reference voltage VPRREFH and produces the pre-charge voltage VPR (for example 1.0V) that will be supplied to storage core 38.

Interior power supply voltage generator 32 receives reference voltage VRFV and produces the interior supply voltage VII (for example 2.0V) that will be supplied to storage core 38 and peripheral circuit 40.

Substrate voltage generator 34 receive reference voltage VRFV and produce to be fed to substrate and storage unit p-trap basic voltage VBB (for example-1.0V).

In the low power consumption mode, VSS charging circuit 36 becomes pre-charge voltage VPR and basic voltage VBB into ground voltage VSS.

Fig. 4 shows the detail drawing of stepup transformer 28 and precharge generator 30.

Stepup transformer 28 is by the resistor R 1 and the R2 that are connected in series, differential amplifier 28a, and the on-off circuit 28d that exciting circuit 28b, nMOS28c and being used to control the nMOS28c grid forms.Booster voltage VPP is fed to an end of resistor R 1, ground voltage VSS is fed to an end of resistor R 2 by nMOS28c.Produce distribution voltage V1 from the connected node of resistor R 1 and R2.In the low power consumption mode, nMOS28c receives the supply voltage VDD from on-off circuit 28d.Differential amplifier 28a for example forms as the current mirroring circuit MOS differential amplifier of power supply by using.When voltage V1 was lower than reference voltage VPREF, differential amplifier 28a exported high level.Exciting circuit 28b receives from the high level of differential amplifier 28a and begins the excitation operation.By this excitation operation, boosted voltage VPP, and boosted voltage V1.When voltage V1 was consistent with reference voltage VPREF (for example 1.5V), the output of differential amplifier 28a arrived low level, made to stop the excitation operation.By repeating these operations, booster voltage VPP remains on constant voltage.

Pre-charge voltage generator 30 is formed by export interconnective two differential amplifier 30a and 30b at them.Reference potential VPRREFL and pre-charge voltage VPR are supplied with differential amplifier 30a.Reference potential VPRREFL and pre-charge voltage VPR are supplied with differential amplifier 30b.And differential amplifier 30a and 30b produce pre-charge voltage VPR with the intermediate value between reference voltage VPRREFL and VPRREFH.

The detail drawing of power supply voltage generator 32 and substrate voltage generator 34 in Fig. 5 shows.Interior power supply voltage generator 32 is by negative feedback type differential amplifier 32a, compensating circuit 32b, and by the regulator 32c that nMOS makes, the on-off circuit 32e that nMOS32d and being used to controls the nMOS door forms.Differential amplifier 32a receives the voltage V2 of reference voltage VRFV and compensating circuit 32b generation, and predetermined voltage is supplied with node VG.In compensating circuit 32b, nMOS in diode connects and resistor R 3 and R4 are arranged in series between node VG and the ground wire VSS.Voltage V2 is created on the connected node between resistor R 3 and the R4.The door connected node VG of regulator 32c, supply voltage in producing on reception supply voltage VDD and the source in its leakage at it.

The source of nMOS32d is connected to ground and its leakage connected node VG.In the low power consumption mode, on-off circuit 32e supplies with supply voltage VDD the grid of nMOS32d.In the low power consumption mode, nMOS32d receives the supply voltage VDD from on-off circuit 32e, and at ground level stationary nodes VG.

In this in power supply voltage generator 32, when the starting voltage of regulator 32c reduced owing to the rising of temperature in the environment around, for example, the starting voltage of the nMOS of compensating circuit 32b also reduced, and makes voltage V2 raise.Answer the requirement of the rising of voltage V2, differential amplifier 32a reduces the voltage of node VG.And the source of nMOS32c to leakage current keeps constant, and supply voltage VII keeps constant in making.

Substrate voltage generator 34 is made up of oscillator 34a and exciting circuit 34b.Answer the requirement of control signal VBBEN high level, the operation of oscillator 34a starting oscillation is with outputting oscillation signal OSC.Exciting circuit 34b has the oscillator signal OSC of response oscillator 34a, is used for the capacitor of recharge and discharge, is connected the nMOS transistor of the diode connection of capacitor with an end.By the excitation operation, the electric charge of the p-type substrate that discharge is connected with anode, this excitation operation reduces basic voltage VBB.Make basic voltage VBB for negative, cause obtaining some effects, because the influence of the drift of the storage unit starting voltage that the substrate effect causes, make the performance that can improve storage unit such as reducing.

Fig. 6 shows the detail drawing of storage core 38 essential parts.

Storage core 38 has storage unit MC, nMOS switch 42a and 42b, pre-charge circuit 44 and sensor amplifier 46.

Storage unit MC transmits nMOS by data and capacitor is formed.The grid of nMOS connect word line WL0 (or WL1).

Bit line BL on nMOS switch 42a and the 42b control store unit MC side (or/BL) with sensor amplifier SA side on bit line BL (or/ being connected between BL).NMOS switch 42a and 42b receive control signal BT with their door.

Pre-charge circuit 44 is by three nMOS44a, and 44b and 44c form.The source of nMOS44a with leak be connected respectively bit line BL and/BL.NMOS44b and 44c with they source with leak be connected respectively bit line BL and/BL, pre-charge voltage BPR is fed to their another source or leakage.NMOS44a and 44b and 44c receive bit line control signal BRS with their grid.

Sensor amplifier 46 constitutes by the input and output that interconnect two CMOS transducers.The output of each CMOS transducer connects bit line/BL and BL respectively.The source of the source of pMOS and the nMOS of each cMOS transducer is connected power lead PSA and NSA respectively.At stand-by state with in the prevention of sensor amplifier activates, the voltage of these power leads PSA and NSA reaches the VPR level respectively, and supply voltage VII and ground voltage VSS in becoming respectively when bit line is exaggerated.

Fig. 7 shows about above-mentioned semiconductor storage unit, and power connection becomes (entering) low power consumption mode and the operation of release (withdrawing from) from the low power consumption mode.

At first, when power connection, supply voltage VDD raise gradually (Fig. 7 (a)).VDD starter 12 among Fig. 3 stops activation initiating signal STTCRX (to low level) to reach predetermined voltage (Fig. 7 (b)) up to supply voltage VDD.By this control, when power connection, can stop the fault that enters circuit 14 owing to low-power to activate the ULP signal.After supply voltage VDD reaches minimum operation voltage VDDmin, the outer controller (for example, CPU or memory controller) that is used to control DRAM will become the high level (Fig. 7 (c)) of schedule time T0 at the CE2 of high level signal.

After this, DRAM becomes stand-by state or carries out normal operations.When DRAM entered the low power consumption mode, outer controller became the CE2 signal into low level (Fig. 7 (d)).When STTCRX signal during at high level, the requirement of answering the CE2 signal to descend, low-power enters circuit 14 and activates ULP signals (to high level) (Fig. 7 (e)).

Answer the high level of ULP signal, low pass filter 22 stop supplies reference voltage generators 24 supply voltages of interior voltage generator 18, but supply is from the ground voltage VSS of VSS charging circuit 36.Voltage VSS responsively, reference voltage generator 24 be reference voltage VPREF, VPRREFL, and VPRREFH and VRFV become ground level.Close the nMOS28b of the stepup transformer 28 among Fig. 4 and the nMOS32d of the interior power supply voltage generator 32 among Fig. 5.As a result, stepup transformer 28, pre-charge voltage generator 30, interior power supply voltage generator 32 and substrate voltage generator 34 are prevented from activating, to stop their operation.Therefore, in the low power consumption mode, keep all custom circuits of operation to be stopped.Therefore, compare with routine, the power consumption in the low power consumption mode has reduced significantly.

When this activates a little circuit and is prevented from encouraging, stop to take place booster voltage VPP, pre-charge voltage VPR, interior supply voltage VII and basic voltage VBB.Yet by VSS charging circuit 36, booster voltage VPP and interior supply voltage VII become supply voltage VDD, and by VSS charging circuit 36, basic voltage VBB and pre-charge circuit VPR become ground voltage VSS.Therefore, stop the interior circuit of main circuit unit 20 to have leak path.

When discharging the low power consumption mode, outer controller becomes high level (Fig. 7 (f)) to the CE2 signal.Answer the requirement of CE2 signal high level, low-power enters circuit 14 and stops activation ULP signal (to low level) (Fig. 7 (g)).Answer the prevention of ULP signal to activate, low pass filter 22 is supplied with reference voltage generator 24 with supply voltage VDD.Answer the ULP signal to stop the requirement that activates, VDD charging circuit 26 and VSS charging circuit 36 stop supplies supply voltage VDD and ground voltage VSS.Then, activate stepup transformer 28 once more, precharge generator 30, interior power supply voltage generator 32 and substrate voltage generator 34 are to begin their operation.

Here, in the time T 1 behind the high level of CE2 signal, DRAM enters idle mode.Time T 1 is voltage VPP in each, and VPR, VII and VBB become and stablize the required time.

Fig. 8 shows a kind of example, and wherein the semiconductor storage unit of first embodiment is used in the mobile phone.

Mobile phone has the DRAM of this embodiment, is installed in CPU and flash memory on the circuit board.

CPU control is from the read/write operation of/data in DRAM and flash memory.When mobile phone cut out or be in waiting status, DRAM was used as working storage, and flash memory is used as backup of memory.

Fig. 9 shows the user mode of the mobile phone among Fig. 8.

In this embodiment, when mobile phone was in waiting status, by the control of CPU, DRAM was in the low power consumption mode.At this moment, the power consumption of DRAM is many as the consumed power of the flash memory in the stand-by state.

When mobile phone when waiting status enters service state, the CE2 signal among CPU rising Fig. 8 is to high level.After DRAM entered idle condition, the data that are retained in the flash memory were sent to DRAM (Fig. 9 (a)).In service state, DRAM is used as working storage.Here, service state not only comprises the state that exchanges acoustic communication but also comprises the state that transmits data.

When service state became waiting status, the data of those necessary DRAM that keep were stored in (Fig. 9 (b)) in the flash memory.After this, CPU reduces the CE2 signal to low level and make DRAM enter into the low power consumption mode.DRAM does not carry out and upgrades operation in the low power consumption mode, makes to lose unnecessary data.

When powered-down, necessary data is retained in the flash memory.Be applied to the working storage of mobile phone by the DRAM with first embodiment, the power consumption when mobile phone is in waiting status reduces significantly.

Here, not by CPU but by control DRAM and flash memories such as specific store controllers.As needs, not only when conversion waiting status and service state, and in service state, carry out data equally and transmit.And the storer that is used for Backup Data should not be confined to flash memory, can be SRAM.Data can be stored in the server such as mobile telephone base station.

Figure 10 is the process flow diagram that the mobile phone of control chart 8 is shown.

At first step S1, when energized, stop the low power consumption mode that enters.As shown in Figure 7, particularly, between the active period of the STTCRX of VDD start-up circuit 12 signal, stop the appearance of fault.

Next, at step S2, CPU becomes low level to the CE2 signal, so that DRAM enters in the low power consumption mode.At step S3, mobile phone is in waiting status.

Next, at step S4, whether CPU detects power supply and closes.When powered-down, termination routine.Program advances to step S5 when powered-down not.

At step S5, CPU repeats waiting status and becomes service state up to it.When it became service state, program advanced to step S6.

At step S6, CPU rising CE2 signal is to high level, so that DRAM is transformed into idle mode from the low power consumption mode.Then, begin each power circuit 28,30,32 and 34 among Fig. 3 once more.

Next, at step S7, the data that CPU will be retained in the flash memory (flash) are sent to DRAM (return data).

Next, at step S8, carry out service or data and transmit.

At step S9, CPU detects DRAM and whether becomes waiting status.When it did not become waiting status, program turned back to step S7.When it is in waiting status, program advances to step S10.

At step S10, CPU is sent to (preservation data) in the flash memory with the data of those necessary DRAM that keep.

Then, program turns back to step S2, and here mobile phone enters waiting status once more.DRAM enters into the low power consumption mode.

In semiconductor storage unit of the present invention and control method thereof, in the low power consumption mode, stop stepup transformer 28, pre-charge voltage generator 30, the operation of interior power supply voltage generator 32 and substrate voltage generator 34.Therefore, compare, can reduce the power consumption in the low power consumption mode significantly with routine.

In the low power consumption mode, at supply voltage VDD and ground voltage VSS booster voltage VPP and interior supply voltage VII, basic voltage VBB and pre-charge voltage VPR are set respectively.Therefore, can stop the interior circuit of main circuit unit 20 to have leak path, thereby reduce power consumption.

By being applied in existing CE2 signal in the routine, DRAM enters into the low power consumption mode, and therefore, what the kind of outer terminal and quantity can be with conventional terminals is identical.As a result, the user of DRAM does not need owing to increasing the low power consumption mode varying circuit significantly.

When energized, VDD starter 12 stops activation initiating signal STTCRX (to low level), and VDD reaches predetermined voltage up to supply voltage.As a result, when power connection, can stop low-power to enter circuit 14 and any fault occur, enter into the low power consumption mode to stop activation ULP signal and DRAM.

When energized, among the schedule time T0 after supply voltage VDD reaches minimum operation voltage VDDmin, the CE2 signal is elevated to high level.This just makes and may stop mistake to enter into the low power consumption mode when energized.

Therefore, by DRAM of the present invention being applied in the working storage of mobile phone, can reduce the power consumption of mobile phone in waiting status significantly.And, can stop the appearance of fault.

Figure 11 shows second embodiment and the control method thereof of semiconductor storage unit of the present invention.Point out with equal reference numbers with the identical circuit that first embodiment is described, and ignore their detailed description.

In this embodiment, general/CE1 signal and CE2 signal provision enter circuit 50 to low-power.General/CE1 signal, CE2 signal and another control signal CN are fed to command decoder 52.Remaining structure is identical with previous first embodiment.

Figure 12 shows the detail drawing that low-power enters circuit 50.

Low-power enters circuit 50 and has timing adjusting circuit 54a and 54b, level shifter 56, rest-set flip-flop 58 and combinational circuit 60.

By connecting two input rejection gate and two input nand gates of a plurality of series connection, form timing adjusting circuit 54a, an input connection delay circuit 54c of rejection gate, an input connection delay circuit 54c of Sheffer stroke gate.Each delay circuit 54c has the mos capacitance that is arranged between a plurality of phase inverters that are connected in series.Timing adjusting circuit 54a outputs to node ND1 with the negative edge of about 100ns delay chip initiating signal CE2Z and with it.CE2Z is from CE2 signal outside supply and that receive at the input buffer (not shown).

Timing adjusting circuit 54b is identical with timing adjusting circuit 54a.Timing adjusting circuit 54b is sent to the negative edge of the signal of node ND3 with about 100ns delay.

Level shifting circuit 56 has pMOS and the nMOS that two covers are connected in series.The grid of each nMOS receive and are in the homophase of rwo address strobe signals RASX and anti-phase signal.Be used to produce these interior supply voltage VII of phase inverters reception anti-phase and not inversion signal and ground voltage VSS of RASX signal.The RASX signal is to become low level control signal when activating word line.Each connects the leakage of adjacent pMOS the grid of pMOS, and the leakage (or output node) of nMOS that is used to receive the positive logic of RASX signal connects rest-set flip-flop 58.The source of each pMOS receives supply voltage VDD, and the source of each nMOS receives ground voltage VSS.

Rest-set flip-flop 58 is made up of two two input rejection gates.A kind of input corresponding with output node ND2 receives initiating signal STTCRX, the output signal of another input incoming level change-over circuit 56.

Combinational circuit 60 receiving node ND1, the low level of ND2 and chip initiating signal CE1X and it become low level to output node ND3.The CE1X signal is created within on the input buffer (not shown) of the signal/CE1 that receives outside supply, and also is negative logic signal.

About 100ns after the low level of receiving node ND3, timing adjusting circuit 54b activates ULP signal (to high level) by phase inverter.

Figure 13 shows the operation that low-power enters circuit 50.

At first, when energized, the STTCRX signal becomes low level, and feasible/CE1 voltage of signals is along with supply voltage VDD raises.Therefore, stoped the appearance of fault.

The schedule time after energized, the STTCRX signal becomes high level (Figure 13 (a)).After this, be used to control the outer controller rising CE2 signal of DRAM to high level (Figure 13 (b)).Identical in above-mentioned time and first embodiment.Response CE2Z signal high level, the node ND1 in Figure 12 becomes high level (Figure 13 (c)).

Carry out initial cycle the RASX signal is become low level (Figure 13 (d)).Response RASX signal low level, rest-set flip-flop 58 rising ND2 are to high level (Figure 13 (e)).After this, the operation of the interior voltage generator 18 among beginning Figure 11.

Next, provide and enter order entering the low power consumption mode.In this embodiment, the schedule time after the CE2 signal is become low level, become low level by handle/CE1 signal, DRAM enters into the low power consumption mode.

Among about 100ns after receiving the CE2Z signal, timing adjusting circuit 54a becomes low level (Figure 13 (f)) to node ND1.Among the 100ns or more time behind the negative edge of CE2Z signal, the CE1X signal becomes low level (Figure 13 (g)).Response CE1Z signal low level and node ND1 low level, the combinational circuit 60 among Figure 12 becomes node ND3 into low level (Figure 13 (h)).Among about 100ns after receiving node ND3 low level, timing adjusting circuit 54b rising ULP signal is to high level (Figure 13 (i)).DRAM enters into the low power consumption mode.

Therefore, by the order input, DRAM enters into the low power consumption mode.

At this moment, the phase inverter of the level shifting circuit among Figure 12 56 receives supply voltage VDD rather than interior supply voltage VII.As a result, owing to reliably close the grid of nMOS, stop level shifter 56 to have leak path.

When discharging the low power consumption mode, the CE1X signal at first becomes high level (Figure 13 (j)).Combinational circuit 60 receives the high level of CE1X signal, becomes low level (Figure 13 (i)) node ND3 is become high level (Figure 13 (k)) and ULP signal.200 μ s after CE1X signal rising edge, CE2Z signal become high level (Figure 13 (m)).Answer the requirement of CE2Z signal high level, the level of node ND1 becomes high level.During 200 μ s, voltage generator 18 in activating is to be stabilized in voltage VPP, VPR, VII and VBB in each of predetermined level.

Here, as first embodiment, the activation of voltage generator 18 and prevention activate in carrying out.Particularly, except entering and withdraw from the low power consumption mode carried out by order input, identical in the control of each circuit in this embodiment and first embodiment.

This embodiment can reach and the similar effect of previous first embodiment.And in this embodiment, by the order input of use/CE1 signal and CE2 signal, DRAM can enter into the low power consumption mode and can discharge from the low power consumption mode.

Figure 14 shows the 3rd embodiment of semiconductor storage unit of the present invention.Point out with identical reference number with the identical circuit that first and second embodiments are described, and omit their detailed description.

In this embodiment, low-power enters circuit 62 and receives low power consumption mode signal/LP.Low power consumption mode signal/LP is the special signal that DRAM enters the low power consumption mode.Low-power enters the negative edge of circuit 62 detection/LP signals, so that DRAM enters into the low power consumption mode.General/CE1 signal, CE2 signal and another control signal CN are fed to command decoder 52.Remaining structure is similar with previous first embodiment.

According to the present invention, the running time in the situation that the CE2 signal quilt/LP signal in energized and running time and Fig. 7 of entering when withdrawing from the low power consumption mode in the time diagram replaces is similar.

This embodiment can reach and the similar effect of previous first embodiment.And in this embodiment, by special-purpose low power consumption mode signal/LP, DRAM can enter into the low power consumption mode reliably and neutralize and discharge from this mode.

Figure 15 and 16 shows VII starter in semiconductor storage unit the 4th embodiment of the present invention and the 3rd embodiment of control method thereof.Describe identical circuit with first embodiment and point out, and omit their detailed description with equal reference numbers.

In this embodiment, form VII starter 70 to replace the VII starter 10 (first embodiment) among Fig. 3.Identical among configuration in addition and Fig. 3.In other words, by in the high level process of/CE1 signal, the CE2 signal being become low level, enter into the low power consumption mode to the DRAM of this similar embodiment among Fig. 7, and, from the low power consumption mode, discharge by the CE2 signal is become high level.

VII starter 70 comprises the release detection circuit 72 among Figure 15, the level detecting circuit 74 among Figure 16, power-on circuit 76.In Figure 15 and 16, except this circuit had the supply voltage of indication, logical circuit was supplied with supply voltage VDD.

Discharge detection circuit 72 and comprise detection circuit 72a, level shifting circuit 72b and trigger 72c.The low level of the pulse LPLS that low-power signal ULP among detection circuit 72a reception Fig. 3 and output and ULP signal negative edge are synchronous.Level shifter 72b converts the high level voltage (interior supply voltage VII) of rwo address strobe signals RASZ to external power voltage VDD, and exports the rwo address strobe signals RASX1 with inverted logic.Level shifter 72b is identical with level shifter 56 among Figure 12.Reception is from the low pulse of detection circuit 72a, and trigger 72c becomes release signal REL into high level, and the low level of incoming level carry circuit 72b (RASZ=high level), and it becomes release signal REL into low level.

In Figure 16, level detecting circuit 74 comprises differential amplifier 74a and the capable 74b of phase inverter, and differential amplifier 74a comprises current mirroring circuit, and the capable 74b of transducer comprises the odd number phase inverter and receives the output of differential amplifier 74a.In the high level process of release signal REL, activate differential amplifier 74a, its relatively interior supply voltage VII and reference voltage VREF, and the output comparative result is to the capable 74b of phase inverter.The steady state value of supply voltage VII in the generator of interior supply voltage VII produces, irrelevant with the fluctuation of the supply voltage VDD of outside supply.On the other hand, reference voltage VREF relies on the fluctuation of supply voltage VDD and changes.

When interior supply voltage VII was lower than reference voltage VREF, the output voltage of differential amplifier 74a descended.Differential amplifier 74a comprises and is used to receive reference voltage VREF to stop the mos capacitance device 74c to the reaction of the humble fluctuation of reference voltage VREF.In addition, the nMOS74d that is used to receive reference voltage VREF is placed on the path of ground wire VSS, flows to the electric current of ground wire VSS and reduces power consumption in the differential amplifier 74a operating process with restriction.NMOS74d operates in order to high resistant.Phase inverter 74e in the capable 74b of the phase inverter starting stage has the nMOS that is connected in series, so that have the logic threshold of the input signal consistent with differential amplifier 74a output.

Because supply voltage is supplied to DRAM, power-on circuit 76 becomes initiating signal STT into high level in the scheduled period.One receives the high level of initiating signal STTPZ high level or initiating signal STT, or (OR) circuit 78 is just exported the high level of initiating signal STTVII (reset signal).The initiating signal STTVII similar to the initiating signal among Fig. 3 is supplied to main circuit unit 20 and initial predetermined interior circuit.

Figure 17 illustrates the running time of above-mentioned DRAM when entering and withdrawing from the low power consumption mode.

At first, when CE2 signal (not shown) becomes low level, enter circuit 14 by the low-power among Fig. 3, DRAM enters into the low power consumption mode, and the generator of interior supply voltage VII stops its operation.Interior supply voltage VII (for example, in normal running for 2.0V) becomes and equals supply voltage VDD (for example, 2.5V) (Figure 17 (a)), and the ULP signal becomes high level (Figure 17 (b)).

Subsequently, the CE2 signal is just becoming high level, and DRAM discharges from the low power consumption mode and the ULP signal becomes low level (Figure 17 (c)).In other words, according to the level of the CE2 signal that receives in the low power consumption mode, DRAM discharges from the low power consumption mode.Low-power among Fig. 3 enters circuit 14 controls withdrawing from from the low power consumption mode.

Receive the negative edge of ULP signal, the detection circuit 72a among Figure 15 becomes the LPLS signal into low level (pulse) (Figure 17 (d)).Receive the low level of LPLS signal, the trigger 72c among Figure 15 becomes the REL signal into high level (Figure 17 (e)).

Because withdrawing from from the low power consumption mode, the power lead of the power lead of interior supply voltage VII and supply voltage VDD is disconnected, and the generator of simultaneously interior supply voltage VII begins its operation.Interior supply voltage VII descends a period of time (Figure 17 (f)) during from the startup of generator.(for example, in the time of 1.25V), the differential amplifier 74a output low level among Figure 16 is to the capable 74b of phase inverter when interior supply voltage VII is lower than reference voltage VREF.The capable 74b of phase inverter exports the high level (Figure 17 (g)) of STTPZ signal once the low level that receives differential amplifier 74a.Or circuit 78 becomes initiating signal STTVII into high level once the high level that receives the STTPZ signal.Initiating signal STTVII is initialised as the predetermined interior circuit of the main circuit unit among reset signal and Fig. 3 20.

After withdrawing from from the low power consumption mode, by sending operational order to DRAM, the RASZ signal is become high level (Figure 17 (h)) and the REL signal becomes low level (Figure 17 (i)).Owing to stoping, the low level of REL signal activates differential amplifier 74a.

As above-mentioned, when withdrawing from the low power consumption mode, when because interior supply voltage VII is lower than predetermined voltage (reference voltage VREF), during the operation of the interior circuit of supply voltage VII, it is unusual that the initialization of interior circuit stops its to occur in can not guaranteeing to be supplied with.

In this above-mentioned embodiment, when the state of the CE2 signal that receives is indicated withdrawing from of low power consumption mode, discharge the low power consumption mode in the low power consumption mode.This just allows easily chip to be withdrawed from from the low power consumption mode by the control signal of outside.

When withdrawing from the low power consumption mode, interior supply voltage VII be lower than reference voltage VREF during in, it is activated for the initiating signal STTVII that reset signal is used for circuit in the initialization.This just when the low power consumption mode is converted to normal mode of operation, make reset safely in circuit and stop in the circuit possibility that becomes that breaks down.

Control signal (CE2 signal) makes chip can enter into the low power consumption mode, and chip can be withdrawed from from the low power consumption mode.

Figure 18 shows the 5th embodiment of semiconductor storage unit of the present invention and the control method of the 4th embodiment.Describe identical circuit with the first and the 4th embodiment and point out, and omit their detailed description with equal reference numbers.

In this embodiment, form level detecting circuit 80, replace the level detecting circuit 74 in the 4th embodiment.Other the configuration with the 4th embodiment in identical.

Level detecting circuit 80 comprises: the differential amplifier 80a that is used for interior supply voltage VII of comparison and reference voltage VREF; The capable 80b of phase inverter that comprises even number of inverters; Be used for the booster voltage VPP of comparison word line (not shown) and the differential amplifier 80c of outer power voltage VDD; The capable 80d of phase inverter that comprises even number of inverters; With Sheffer stroke gate 80e.Be formed on the inside of chip by the booster voltage of stepup transformer generation.Differential amplifier 80a and 80c are identical with differential amplifier 74a among Figure 16, and are activated once the high level that receives the REL signal.Capable 80b of phase inverter and 80d are made up of the phase inverter of the subordinate phase of the capable 74b of phase inverter among the phase inverter that is in the starting stage and Figure 16.The capable 80b of transducer receives the output of differential amplifier 80a, and the logic level that output receives is to Sheffer stroke gate 80e, as initiating signal STT1X.The capable 80d of phase inverter receives the output of differential amplifier 80c, and the logic level that output receives is to Sheffer stroke gate 80e, as initiating signal STT2X.Sheffer stroke gate 80e as negative logic or circuit operation and output initiating signal STTPZ.

Figure 19 shows the running time of above-mentioned DRAM when entering and withdrawing from the low power consumption mode.

At first, when CE2 signal (not shown) became low level, DRAM entered into their operation of generator termination of generator and the booster voltage VPP of low power consumption mode and interior supply voltage VII.Interior supply voltage VII (for example, being 2.0V in normal running) and booster voltage VPP (for example, in normal running for 3.7V) become and equal supply voltage VDD (for example, 2.5V) (Figure 19 (a)) and ULP signal become high level (Figure 18 (b)).

Subsequently, the CE2 signal is just becoming high level, and DRAM discharges from the low power consumption mode, and the ULP signal becomes low level (Figure 19 (c)).As in Figure 17, the LPLS signal becomes low level (Figure 19 (d)), and the REL signal becomes high level (Figure 19 (e)).

Because withdrawing from from the low power consumption mode, the power lead of the power lead of interior supply voltage VII and supply voltage VDD is disconnected, and the generator of interior supply voltage VII begins its operation.Supply voltage descends a period of time (Figure 19 (f)) in during from the beginning of generator.Interior supply voltage VII be lower than reference voltage VREF (for example, 1.25V) during in, output STT1X low level (Figure 19 (g)).Similarly, being connected between the power lead of the power lead of booster voltage VPP and supply voltage VDD is disconnected, and the generator of booster voltage VPP begins its operation.Booster voltage VPP descends a period of time (Figure 19 (h)) when generator begins.Booster voltage VPP be lower than supply voltage VDD during in, the low level (Figure 19 (i)) of output STT2X signal.

STT1X signal or STT2X signal be in low level during in, the high level (Figure 19 (j)) of the Sheffer stroke gate 80e output STTPZ signal among Figure 18.In the high level of STTPZ signal, initiating signal STTVII (Figure 16) becomes high level.Initiating signal STTVII is as the predetermined interior circuit of the main circuit unit 20 in reset signal and the initial graph 3.

After withdrawing from from the low power consumption mode, initial its operation of DRAM becomes the same in low level (Figure 19 (the l)) image pattern 17 thereby the RASZ signal becomes high level (Figure 19 (k)) and REL signal.Because the low level of REL signal stops and activates differential amplifier 80a and 80c.

This embodiment can obtain and the similar effect of previous the 4th embodiment.And, in this embodiment, when the low power consumption mode withdraws from, the booster voltage VPP that produces in inside be lower than outer power voltage VDD during in, be used for initial in the initiating signal STTVII of circuit be activated.Particularly, when from the low power consumption mode, withdrawing from, at least a supply voltage VII be lower than respectively reference voltage VREF and supply voltage VDD during in, be used for initial in the initiating signal STTVII of circuit be activated.This just makes when the low power consumption mode is converted to normal mode of operation, in may resetting safely circuit and stop in circuit break down (unusually).

Figure 20 shows the initiating signal generator during the semiconductor storage in the sixth embodiment of the invention and the control method of the 5th embodiment.Describe identical circuit with the first and the 4th embodiment and point out, and omit their detailed description with equal reference numbers.

In the DRAM of this embodiment, form initiating signal generator 82, replace release detection circuit 72 and level detecting circuit 74 that the 4th embodiment is described.Other the configuration with Fig. 3 (first embodiment) in identical.

Initiating signal generator 82 is by being used to receive its CMOS phase inverter 82a for the CE2X signal of anti-phase CE2 signal, the mos capacitance device 82b that connects CMOS transducer 82a output is used to receive the input of CMOS phase inverter 82a and the differential amplifier 82c of reference voltage VREF forms.When the voltage of node ND4 is lower than reference voltage VREF, comprise that the differential amplifier 82c of current mirroring circuit becomes initiating signal STTPZ into high level.

The pMOS of CMOS phase inverter 82a has long channel length, to have high ON resistance.The CR time constant circuit is made up of pMOS and the mos capacitance device 82b of CMOS phase inverter 82a.Compare with the situation of using diffusion resistance, use transistorized ON resistance to form the size that the CR time constant circuit allows to reduce wiring diagram.

Figure 21 shows the running time of above-mentioned DRAM when entering and withdrawing from the low power consumption mode.

At first, when CE2 signal (not shown) became low level, the CE2X signal becomes high level and DRAM enters into the low power consumption mode.The generator of the generator of interior supply voltage VII and booster voltage VPP stops their operation.CMOS phase inverter 82a among Figure 20 opens nMOS and node ND4 is become low level (Figure 21 (a)) once the high level that receives the CE2X signal.When the voltage of node ND4 was lower than reference voltage VREF, differential amplifier 82c became the STTPZ signal into high level (Figure 21 (b)).

Subsequently, the CE2 signal is just being become high level and the CE2X signal is just becoming low level, and DRAM discharges (Figure 21 (c)) from the low power consumption mode.CMOS phase inverter 82 1 among Figure 20 receives the low level of CE2X signal, just pMOS is opened and node ND4 is become high level (Figure 21 (d)).At this moment, according to the time constant that ON resistance and the CMOS capacitor of pMOS are determined, the voltage of node ND4 raises gradually.When the voltage of node ND4 was higher than reference voltage VREF, differential amplifier 82c became the STTPZ signal into low level (Figure 21 (e)).

Therefore, during withdrawing from, the T2, activate (high level) STTPZ signal (reset signal) and initial interior circuit from the low power consumption mode.After from the low power consumption mode, withdrawing from, during the setting T2 and interior supply voltage VII be lower than predetermined voltage during corresponding, make can not guarantee supply in the interior circuit of supply voltage VII.In other words, initiating signal generator 8 is as timer operation, the length of T2 during being used for determining.

This embodiment can obtain and the similar effect of previous the 4th embodiment.And in this embodiment, when withdrawing from from the low power consumption mode, initiating signal generator 82 is as timer operation, producing the STTPZ signal, and during after the low power consumption mode withdraws from the T2, initial in circuit.This just makes that when the low power consumption mode conversion becomes normal mode of operation the interior circuit of circuit and prevention breaks down in may resetting reliably.

Because initiating signal generator 82 is as CR time constant circuit operation, on the basis in propagation delay time of the signal that propagates into the CR time constant circuit, T2 is possible during the setting.In this just makes and may be provided for resetting by ball bearing made using circuit during.

The ON resistance of pMOS is used to form the CR time constant circuit, the feasible size that can reduce the wiring diagram of initiating signal generator 82.

Figure 22 shows the 7th embodiment and the control method of semiconductor storage unit of the present invention.Be not described in detail the circuit identical here, with first embodiment by pointing out with equal reference numbers.

In this embodiment, DRAM comprises VII starter 10, VDD starter 12, and low-power enters circuit 84, command decoder 16, interior voltage generator 86 and main circuit unit 88.Interior voltage generator 86 has low pass filter 22, reference voltage generator 24, VPP detector 90, stepup transformer 92, pre-charge voltage generator 94, interior power supply voltage generator 96, VBB detector 98 and substrate voltage generator 100.Main circuit unit 88 has storage core 38, peripheral circuit 40, frequency divider 102 and oscillator 104.These frequency dividers 102 and oscillator 104 are to be used for producing timing signal to automatically perform the control circuit that upgrades operation in the self refresh mode.

Figure 23 shows the detail drawing of reference voltage generator 24.

Reference voltage generator 24 is equipped with the reference voltage generator 24a that is used to produce reference voltage VREF, by the starter 24b that pMOS forms, and differential amplifier 24c and regulator 24d.

Reference voltage generator 24a has the current mirroring circuit of being made by pMOS, two nMOS of the current mirroring circuit that is connected in series respectively, and be connected register between a nMOS source and ground wire VSS.The output of reference voltage generator 24a is connected in the leakage of the grid of nMOS and another nMOS, from wherein producing reference voltage VREF.The grid of another nMOS connect the source of another nMOS.

When initiating signal STTCRX was activated after energising, starter 24b rising reference voltage VREF was to high level.

Differential amplifier 24c has the current mirror parts of being made by pMOS, the differential input block of making by nMOS, and a nMOS gives grid reference voltage supplies and connects differential input block and ground wire VSS.Reference voltage VREF is fed on the grid of a nMOS of differential input block, reference voltage VRFV is fed on the grid of another nMOS.

By connect pMOS and be connected on power lead VDD and ground wire VSS between five resistors constitute regulator 24d.From the connected node of each element, difference output reference voltage VRFV, VPREF, VPRREFL and VPRREFH.Two terminals with the resistor that connects ground wire VSS connect source and the leakage of the nMOS that is controlled by low-power signal NAPX.When activating low-power signal NAPX (to low level), the resistor that connects ground wire VSS is bypassed.Therefore, in the low power consumption mode, reference voltage VRFV, VPREF, the level of VPRREFL and VPRREFH (absolute value) changes, and has reduced voltage thereby compare with normal mode of operation.

The detail drawing of power supply voltage generator 96 in Figure 24 shows.

By eliminating on-off circuit 32e and nMOS32d in the power supply voltage generator 32 in the first embodiment VII from Fig. 5 and by increasing stabilising condenser 96a, switch 96b and nMOS96c and power supply voltage generator 96 in constituting.The electric charge of power lead VII in a stabilising condenser 96a storage part is fed to, with reduce as otherwise the drift of the supply voltage VII that may be caused by power supply noise.For example, switch 96b is made up of the COMS transmission gate.As the inverted logic that the nMOS96c between power lead VII and ground wire VSS supplies low-power signal NAPX in being arranged on its grid by phase inverter.

When activating low-power signal NAPX, switch 96b closes, to disconnect regulator 32c and interior circuit.At this moment, close nMOS96c, power lead VII drops to ground voltage (0V) in making.In supply voltage VII is not fed on the circuit, make in the power consumption mode, take place in the leakage current of transistor etc. in the circuit.Particularly, the power consumption of interior circuit can be reduced to zero.At this moment, keep being connected between regulator 32c and stabilising condenser 96a, make stabilising condenser 96a as stored charge in normal running.

After discharging the low consumption mode, when stoping activation low-power signal NAPX, open switch 96b.Meanwhile, close nMOS96c to connect regulator 32c and interior circuit.At this moment, not only from the electric charge of regulator 32c supply and also be stored in electric charge the stabilising condenser 96a be supplied in power lead VII, in supply voltage VII raises and also is fed in making on the circuit.As a result, but after discharging the low power consumption mode circuit in the immediate operation.

Figure 25 shows stepup transformer 92, VPP detector 90, basic voltage detector 100 and VBB detector 98.

Stepup transformer 92 is equipped with and wants operated oscillator 106 and a plurality of unit 108 and 110 when initiating signal VPPEN is boosted in activation.When activating low-power signal NAPX, the pulse signal PLS1-PLS6 that unit 108 receives from oscillator 106 is to produce booster voltage VPP.Response is from the pulse signal PLS1-PLS6 of oscillator 106, no matter low-power signal NAPX, unit 110 at any time produces booster voltage VPP.On the basis that low-power signal NAPX activates, unit 108 stops its operation, makes that the power consumption of stepup transformer 92 descends in the power consumption mode.In the low power consumption mode, do not carry out and upgrade operation, make as will be described, even descending, the driving force of stepup transformer 92 do not go wrong yet.The unattended operation mode, according to the definite number of at any time wanting operated unit 110 of time durations (being the time characteristic), normal running is carried out in the back or renewal is operated up to returning from the low power consumption mode.

Substrate voltage generator 100 is equipped with by activating basic voltage detectable signal VBBDET and stoping and activates low-power signal NAPX and operated a plurality of unit 112, operated a plurality of unit 114 by activating basic voltage detectable signal VBBDET.When the operation of stop element 112 on the basis that low-power signal NAPX activates, the power consumption of substrate voltage generator 100 descends in the power consumption mode.The unattended operation mode is according to the definite number of wanting operated unit 114 of time durations (being the time characteristic) after turning back to normal mode of operation from the low power consumption mode or upgrading operation.

Figure 26 shows the detail drawing of the unit 108 of stepup transformer 92.

Unit 108 comprises four capacitor 108a that each is all made by nMOS, 108b, 108c and 108d and as the pMOS108e and the 108f of switching manipulation.When stoping activation low-power signal NAPX, capacitor 108a, 108b, 108c and 108d receive pulse signal PLS1, PLS2, the inverted logic of PLS3 and PLS4 in their termination respectively.The other end of capacitor 108a-108d connects power lead VDD by the nMOS that a plurality of diodes connect.When stoping activation low-power signal NAPPX, the grid of pMOS108e and 108f are by logic gate difference received pulse signal PLS5 and PLS6 on their grid.

Pulse signal PLS1, PLS2 and PLS5 and pulse signal PLS3, PLS4 and PLS6 are inverting each other.The high level voltage of low-power signal NAPX and pulse signal PLS5 and PLS6 equals booster voltage VPP, so that close pMOS108e and 108f reliably.

The pulse signal PLS1 of response input, PLS2, PLS3 and PLS4, capacitor 108a and 108b, 108c and 108d be charging and discharge alternately.Synchronous with the excitation operation of capacitor 108a and 108b and capacitor 108c and 108d, pMOS108e and 108f alternately open.And by these excitation operations, supply voltage VDD is added to booster voltage VPP.When activating low-power signal NAPX, unit 108 stops its operation.

Figure 27 shows the detail drawing of the unit 110 of stepup transformer 92.

Unit 110 is circuit of making by the logic that eliminates low-power signal NAPX and NAPPX from unit 108.In other words, the whenever operation of unit 110 behind power supply opening is to produce booster voltage VPP.

Figure 28 shows the detail drawing of VPP detector 90.

VPP detector 90 is equipped with differential amplifier 90a and is used for its voltage is fed to the voltage generator 90b of the input of differential amplifier 90a.

Differential amplifier 90a has the current mirror parts 90c that is made up of pMOS, the pair of differential input block 90d and the 90e that are made up of nMOS.The control signal VPP2 that the input end of differential input block 90d and 90e receives reference signal VPREF and produces from the level of the booster voltage VPP of voltage generator 90b by conversion.Differential input block 90d connects ground wire VSS by the nMOS that always opens, and differential input block 90e connects ground wire VSS by the nMOS that opens when stoping activation low-power signal NAPX.

In a word, differential input block 90d at any time operates, and differential input block 90e only operates when stoping activation low-power signal NAPX.Differential input block 90e stops its operation in the low power consumption mode, makes to reduce power consumption.When control voltage VPP2 was lower than reference voltage VPREF, differential amplifier 90a activated the initiating signal that boosts (to high level).

Be connected on by connection and be used to the producing node of booster voltage VPP and three resistors between ground wire VSS constitute voltage generator 90b.Control voltage VPP2 is from the other end output of the resistor of node one side that is used to supply booster voltage VPP.Two ends with the resistor that connects ground wire VSS connect source and leakage with the nMOS of low-power signal NAPX control respectively.When activating low-power signal NAPX, walk around the resistor that connects ground wire VSS.Therefore, in the low power consumption mode, the level of control signal VPP2 descends.

Figure 29 shows the detail drawing of the unit 112 of substrate voltage generator 100.

Unit 112 is equipped with oscillator 112a and exciting circuit 112b.

Oscillator 112a is configured to the circular oscillator be made up of the odd number level of logic gate.Be activated and low-power signal NAPX when being prevented from activating at basic voltage detectable signal VBBDET, oscillator 112a operates.

Exciting circuit 112b comprises having three pMOS being connected in series between power lead VDD and excitation node PND and the power voltage part 112c of a nMOS, connect the capacitor 112d that the pMOS of excitation node PND forms by grid, be used for connecting during at high level the nMOS112e of excitation node PND and ground wire VSS, the nMOS112f that is connected with the diode that is used to be connected excitation node PND and substrate node VBB at excitation node PND.

In exciting circuit 112b, when the pMOS of power supply unit 112c and capacitor 112d and nMOS received clock signal from oscillator 112a, excitation node PND had ground voltage and negative voltage convertibly.And when excitation node PND had negative voltage, the electric charge of substrate node VBB was pumped out, substrate node VBB to be set to negative voltage.In the low power consumption mode (when low-power signal NAPX activates), unit 112 stops its operation.

Figure 30 shows the detail drawing of the unit 114 of substrate voltage generator 100.

Unit 114 is equipped with oscillator 114a and exciting circuit 114b.

Oscillator 114a is the circuit of making by the logic that eliminates low-power signal NAPX from the oscillator 112a of unit 112.In a word, even in the power consumption mode, oscillator 114a response basic voltage detectable signal VBBDET operates, to produce basic voltage VBB.Exciting circuit 114b is the circuit identical with the exciting circuit 112b of unit 112.

Figure 31 shows the detail drawing of VBB detector 98.

VBB detector 98 is equipped with two probe unit 98a and 98b and is used to export as the unit 98a of basic voltage detectable signal VBBDET and result of detection or logic or the circuit 98c of 98b.

Probe unit 98a comprises: the reference voltage generation part 98d with resistor; PMOS and resistor in being connected in series between power lead VII and ground wire VSS; Level exploring block 98e with two nMOS that are connected in series; Has the CMOS phase inverter 98f that connects the pMOS of power lead VII by the pMOS load circuit; Be used to be connected the output node NOUT1 of level exploring block 98f and the nMOS98g of ground wire VSS.The grid of the pMOS of reference voltage generation part 98d and the grid of nMOS98g receive low-power signal NAPX.Therefore, in normal mode of operation, stop and activate probe unit 98a, but in the power consumption mode, be activated.When activating, the voltage of the output node NOUT1 of level exploring block 98e raises along with the rising of basic voltage VBB.In this embodiment, when basic voltage VBB be elevated to-during 0.5V, CMOS phase inverter 98f answers the requirement of the result of detection (being the voltage of output node NOUT1) of level exploring block 98d, output low level.When receiving the low level of CMOS phase inverter 98f, or circuit 98c activates basic voltage detectable signal VBBDET.

In probe unit 98b, the grid of the pMOS of reference voltage generation part 98d and the grid of nMOS98g are supplied the inverted logic of low-power signal NAPX.Remaining structure is identical with probe unit 98a's.In this embodiment, when basic voltage VBB in normal mode of operation be elevated to-during 1.0V, response levels exploring block 98e (being the voltage of output node NOUT1) result of detection, CMOS phase inverter 98f output low level.When low-power signal NAPX was in low level (in the power consumption mode), the output of the reference voltage generation part 98d of probe unit 98b had ground voltage VSS (0V).Therefore, at any time the output node NOUT2 of level exploring block 98e has low level.In a word, in the power consumption mode, stop activation probe unit 98b.

Therefore, when basic voltage VBB be elevated to-during 1.0V, VBB detector 98 only uses probe unit 98b and activates basic voltage detectable signal VBBDET in normal mode of operation.When activating basic voltage detectable signal VBBDET, shown in Figure 29 and 30, the unit 112 and 114 of basic voltage generation circuit 100 is operated, and makes basic voltage VBB descend.

In the low power consumption mode, on the other hand, when activating low-power signal NAPX, VBB detector 98 activates probe unit 98a but stops and activates probe unit 98b.As a result, reduce the power consumption of VBB detector 98.In the power consumption mode, only survey the level of basic voltage VBB, make to be elevated to-activate basic voltage detectable signal VBBDET during 0.5V at basic voltage VBB by detection circuit 98a.Detection level (with the absolute value) step-down of basic voltage VBB reduces the absolute value of the basic voltage VBB that must be produced by substrate voltage generator 100.In other words, compare, in the power consumption mode, further suppress the operation of substrate voltage generator 100 with normal mode of operation.As a result, can reduce power consumption.Difference between basic voltage VBB and ground voltage VSS reduces, thereby reduces the substrate seepage.Therefore, the frequency of occurrences of basic voltage detectable signal VBBDET reduces, to reduce the operating frequency of substrate voltage generator 100.As a result, can further reduce power consumption.

Figure 32 shows the detail drawing of pre-charge voltage generator 94.

Pre-charge voltage generator 94 is equipped with differential amplifier 94a and 94b and VPR generator 94c.

Differential amplifier 94a has current mirror parts 94d and a pair of differential input block 94e and the 94f that is made up of nMOS that is made up of pMOS.The input of differential input block 94e and 94f receives reference voltage VPRREFL and pre-charge voltage VPR.Differential input block 94e connects ground wire VSS by the nMOS that always opens, and differential input block 94f connects ground wire VSS by the nMOS that opens when stoping activation low-power signal NAPX.

In a word, differential input block 94e at any time operates, and differential input block 94f only operates when stoping activation low-power signal NAPX.Differential input block 94f stops its operation in the power consumption mode, makes to reduce power consumption.When reference voltage VPRREFL was higher than pre-charge voltage VPR, differential amplifier 94a was provided with output node NOUT3 to low level.

Differential amplifier 94b has current mirror parts 94g and a pair of differential input block 94h and the 94i that is made up of pMOS that is made up of nMOS.The input end of differential input block 94h and 94i receives reference voltage VPRREFH and pre-charge voltage VPR.Differential input block 94g connects power lead VDD by the pMOS that always opens, and differential input block 94i connects power lead VDD by the pMOS that opens when stoping activation low-power signal NAPX.

Differential input block 94h at any time operates, and differential input block 94i only operates when stoping activation low-power signal NAPX.In the low power consumption mode, differential input block 94i stops its operation, makes to reduce power consumption.When reference voltage VPRREFH was lower than pre-charge voltage VPR, differential amplifier 94b was provided with output node NOUT4 to low level.

VPR generator 94c has pMOS and the nMOS that is connected in series between power lead VDD and ground wire VSS.The grid of pMOS connect output node NOUT3.The grid of nMOS connect output node NOUT4.From the leakage of pMOS and nMOS, output pre-charge voltage VPR.Pre-charge voltage VPR is used as the equalizing voltage of paired bit line and the plate voltage of the storage unit in the storage core 38.

In the power consumption mode, the prevention of differential input block 94f and 94i activates the response that reduces by 94 pairs of pre-charge voltage drifts of pre-charge voltage generator.Yet, as will be described, in the power consumption mode, do not carry out read operation and upgrade operation, even make the response that reduces pre-charge voltage generator 94, do not go wrong yet.

Figure 33 shows the detail drawing of oscillator 104.

Oscillator 104 is equipped with the circular oscillator 104a with the CMOS transducer odd level that is connected in series, and is used for extracting from circular oscillator 104a the impact damper 104b of oscillator signal OSCZ.Frame of broken lines among Figure 33 is the switch that is used to adjust circular oscillator 104a progression (with corresponding during the self refresh).The arrangement mode of burning end by polysilicon fuse or the photomask by wiring layer is provided with the ON/OFF of these switches.In this example, the progression of circular oscillator 104a is changed to " 7 ".Load is connected interior power lead VII and ground wire VSS to the pMOS of CMOS phase inverter with nMOS by the pMOS load respectively with the source of nMOS.The grid of pMOS load and nMOS load are respectively by control voltage PCNTL and NCNTL control.Oscillator 104 has pMOS and the nMOS that is used to receive low-power signal NAPX.When activating low-power signal NAPX, those pMOS are opened, and to high level, still when those nMOS are closed, being connected between the nMOS of CMOS phase inverter and ground wire VSS is disconnected with the destined node of set collar line oscillator 104a.As a result, oscillator 104 stops its operation in the power consumption mode.

Figure 34 shows and is formed on the generator 116 that is used to produce control voltage PCNTL and NCNTL in the oscillator 104.

Generator 116 is equipped with: the pMOS in being connected in series between power lead VII and ground wire VSS, pMOS diode and resistor; Resistor in being connected in series between power lead VII and ground wire VSS, nMOS diode and nMOS; Be arranged in and be used to produce the node of control voltage PCNTL and the mos capacitance device between interior power lead VII; Be arranged in and be used to produce the node of control voltage NCNTL and the mos capacitance device between ground wire VSS.

Control voltage PCNTL produces from the connected node between pMOS diode and resistor, and changes along with the drift of interior supply voltage VII.Control voltage NCNTL produces from the connected node between nMOS diode and resistor, and changes along with the drift of ground voltage VSS.Therefore, always the grid of the pMOS of the CMOS transducer among Figure 33 and nMOS are constant to source voltage, make that be constant the oscillation period of circular oscillator 104a regardless of the drift of interior supply voltage VII.The mos capacitance device stops high frequency noise influence control voltage PCNTL and the control voltage NCNTL that occurs on interior power lead VII and the ground wire VSS.As a result, cancelled the drift of interior supply voltage VII and ground voltage VSS, made when activating oscillatory circuit 104 (in the self refresh mode), the scheduled period has always been produced oscillator signal OSCZ.

When activating low-power signal NAPX, close pMOS and nMOS.In other words, in the power consumption mode, stop activation generator 116.At this moment, control voltage PCNTL and NCNTL become low level and high level respectively.

In the DRAM that so describes, identical with first embodiment, low-power among Figure 22 enters circuit 84 and activates low-power signal NAPX (to low level), when receiving outside low level chip initiating signal CE2 at chip, makes it enter into the low power consumption mode.

When activating low-power signal NAPX, the reference voltage generator 24 among Figure 23 reduces reference voltage VRFV, VPREF, the level of VPREFL and VPREFH.VPP detector 90 among Figure 28 stops the level that activates differential input block 90e and reduce the control voltage VPP2 that will be supplied to differential input block 90d simultaneously.As shown in figure 25, the unit 112 of the unit 108 of stepup transformer 92 and substrate voltage generator 100 stops their operation.VBB detector 98 among Figure 31 stops activation probe unit 98b but activates probe unit 98a, with the detection level of rising basic voltage VBB.Particularly, when basic voltage VBB be elevated to-during 0.5V, activate basic voltage detectable signal VBBDET.The differential amplifier 94a of the pre-charge voltage generator 94 among Figure 32 and 94b stop differential input block 94f of activation and 94i respectively.Oscillator 104 among Figure 33 stops its operation.Generator 116 among Figure 34 is prevented from activating.

Figure 35 shows the operation of oscillator 104 and frequency divider 102.

When activating low-power signal NAPX, oscillator 104 is provided with oscillator signal OSCZ to low level.Because oscillator signal OSCZ stops its vibration, the frequency division of frequency divider 102 stops, and makes self refresh timer signal SRTZ become low level.Therefore, the power consumption of frequency divider 102 is zero substantially.

Therefore, compare with routine techniques, a plurality of control circuits are ended their operation or are reduced the detectivity of signal level, thereby reduce the power consumption in the low power consumption mode basically.Some control circuits continue their operation with low acquisition mode, make can begin normal running immediately from the low power consumption mode after discharging.

In this embodiment, as above-mentioned, in the power consumption mode, stop to be used for the oscillator 104 of self refresh, to stop at the operation of carrying out in the self refresh mode.As a result, can reduce power consumption in the power consumption mode.

Do not upgrade operation owing to carry out, interior voltage generator 86 can be operated with the power that is enough to compensate the electric power (leakage current) that is consumed by peripheral circuit 40.As a result, can reduce power consumption in the power consumption mode.

Even in the power consumption mode, interior voltage VPP, VBB and VPR are supplied on the interior circuit (comprising peripheral circuit 40, storage core 38 etc.).Therefore, after just from the low power consumption mode, discharging, can operate peripheral circuit 40, storage core 38 etc.

In the low power consumption mode, stop the operation of the unit 112 of the unit 108 of stepup transformer 92 and substrate voltage generator 100, make further to reduce power consumption in the power consumption mode.

In the low power consumption mode, being connected between power lead VII and stabilising condenser 96a in keeping, and being connected between power lead VII and interior circuit (peripheral circuit 40 and storage core 38) in disconnecting.Stop supplies can disappear the leakage current that obtains peripheral circuit 40 to the supply voltage of peripheral circuit 40, serves as zero to reduce power consumption.After from the low power consumption mode, discharging, in connecting when power lead VII and interior circuit, in the voltage corresponding with electric charge in being stored in stabilising condenser 96a is fed to by interior power lead VII on the circuit.Therefore, after discharging from the low power consumption mode, interior power supply voltage generator 96 produce predetermined in before the supply voltage VII, the voltage corresponding with electric charge in being stored in stabilising condenser 96a can be applied on the interior circuit.As a result, circuit can be operated immediately discharge the back from the low power consumption mode in.

In the low power consumption mode, stop differential input block 90e and the differential amplifier 94a of pre-charge voltage generator 94 and differential input block 94f and the 94i among the 94b among the differential amplifier 90a that activates VPP detector 90, make and to reduce differential amplifier 90a, the power consumption of 94a and 94b.

In the low power consumption mode, stop the operation of the unit 112 of the unit 108 of stepup transformer 92 and substrate voltage generator 100, make that the transition that suppresses booster voltage VPP and basic voltage VBB is discrete.In other words, can reduce the difference between minimum and maximum booster voltage VPP and basic voltage VBB, to reduce leakage current.

By reducing the reference signal VPREF that is produced by reference voltage generator 24, VRFV (VII), the level of VPRREFH and VPRREFL, reduce VPP detector 90, the absolute value of the detection level of VBB detector 98 and pre-charge voltage generator 94, and reduce booster voltage VPP, the level (absolute value) of the basic voltage VBB and the pre-charge voltage VPR that will be produced by pre-charge voltage generator 94.Owing to reduced voltage, can reduce leakage current to reduce power consumption.

In above-mentioned embodiment, the present invention is applied among the DRAM.Yet the present invention is not limited to this embodiment.For example, present invention can be applied to such as SDRAMs (synchronous dram s), DDR SDRAMs (double data rate SDRAMs), or on the semiconductor memory of FCRAMs (RAMs fast circulates).

Use semiconductor fabrication process of the present invention and be not limited to CMOS technology, but it is preferably Bi-CMOS technology.

In form the example that low-power enters circuit 50 by a plurality of delay circuit 54c that are connected in series, the second previous embodiment has been described.Yet the present invention is not limited thereto, for example, can be formed low-power by use by the latch circuit of STTCRX signal controlling and enter circuit.In this is revised, reduced the yardstick of circuit.

In the example that uses special-purpose low power consumption mode signal/LP, the 3rd previous embodiment has been described.For example, by stopping on the chip/LP signal and do not provide terminal for/LP signal, this DRAM even can be provided to the not user of required power consumption ways.By connecting or blow out fuse ,/LP signal can connect supply voltage VDD.Perhaps, by the photomask of selective interconnection layer ,/LP signal can connect supply voltage VDD.

In the embodiment that compares booster voltage VPP and supply voltage VDD, the 5th previous embodiment has been described.Yet the present invention is not limited to this embodiment, and for example, booster voltage VPP can compare with the reference voltage VREF that produces by reduction supply voltage VDD to the greatest extent.

At the initiating signal generator 82 of operation as timer, be used for determining the duration of T2 during when the low power consumption mode withdraws from and be used for during T2 activate in the example of the STTPZ signal (reset signal) of circuit in the initialization and described the 6th previous embodiment.The present invention is not limited to this embodiment.For example, when from the low power consumption mode, withdrawing from, operate as timer, so that the counting predetermined quantity with the counter of normal running.The reset signal that is used for initial interior circuit can be activated during rolling counters forward quantity.The refresh counter of the scheduler of indication storage unit etc. can be used as counter.

The present invention is not limited to above-mentioned embodiment, can make various modifications on the basis of not leaving spirit and scope of the invention.Can partly or entirely carry out any improvement.

Claims (16)

1. method of operating dynamic RAM, this dynamic RAM comprises dynamic storage cell, described storer has low power consumption mode and idle mode, in the low power consumption mode, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade, and the method comprising the steps of:

Enter idle mode;

Response comprise a plurality of control signals during the idle mode combination external command and enter the low power consumption mode.

2. according to the method for the operation dynamic RAM of claim 1, further comprise step:

Response second is ordered and is withdrawed from from the low power consumption mode.

3. according to the method for the operation dynamic RAM of claim 2, wherein

After from the low power consumption mode, withdrawing from, this storer of initialization.

4. method of operating semiconductor memory, this semiconductor memory comprises dynamic storage cell, the method comprising the steps of

Respond the special external control signal and enter the low power consumption mode, in the low power consumption mode, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade.

5. according to the method for the operation semiconductor memory of claim 4, wherein

Semiconductor memory response special external control signal from first voltage to second voltage change in voltage and enter the low power consumption mode.

6. according to the method for the operation semiconductor memory of claim 5, wherein

When having second voltage, the special external control signal keeps the low power consumption mode.

7. according to the method for the operation semiconductor memory of claim 5, wherein

The reverse voltage of semiconductor memory response special external control signal from second voltage to first voltage changes and withdraws from the low power consumption mode.

8. the method for an operational store system, this accumulator system comprise the semiconductor memory that contains dynamic storage cell and the controller of semiconductor memory, and the method comprising the steps of:

By controller dedicated control signal is outputed to semiconductor memory,

Make semiconductor memory enter the low power consumption mode, in the low power consumption mode, in response to dedicated control signal, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade.

9. the method for operational store system according to Claim 8 further comprises step:

When output during dedicated control signal, the voltage of dedicated control signal is changed over second voltage from first voltage.

10. according to the method for the operational store system of claim 9, further comprise step

The voltage that keeps dedicated control signal is in second voltage, to keep the low power consumption mode of semiconductor memory.

11. the method according to the operational store system of claim 10 further comprises step

The voltage of dedicated control signal is changed over first voltage from second voltage, make semiconductor memory withdraw from the low power consumption mode.

12. an accumulator system comprises:

The first memory that comprises dynamic storage cell, it has the low power consumption mode, and in the low power consumption mode, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade, and first memory has data terminal; And

The second memory that comprises flash memory cell, it has the data terminal that is connected with the data terminal of first memory, wherein

First memory enters the low power consumption mode in response to the external control signal of externally terminal reception, and receives supply voltage constantly during the low power consumption mode.

13. according to the accumulator system of claim 12, wherein

Before first memory enters the low power consumption mode, be stored in data in the dynamic storage cell in the first memory and transfer to flash memory cell in the second memory.

14. according to the accumulator system of claim 12, wherein

After first memory withdraws from the low power consumption mode, be stored in data in the flash memory cell in the second memory and transfer to dynamic storage cell in the first memory.

15. the cell phone with service state and waiting status comprises:

The first memory that comprises dynamic storage cell, it has the low power consumption mode, and in the low power consumption mode, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade, and first memory has data terminal;

The second memory that comprises flash memory cell, it has the data terminal that is connected with the data terminal of first memory, wherein

When service state is transformed into waiting status, the external control signal that receives in response to terminal externally, be stored in data in the dynamic storage cell in the first memory and transfer to flash memory cell in the second memory, first memory enters the low power consumption mode then

First memory receives supply voltage constantly during the low power consumption mode, and

When waiting status is transformed into service state, first memory in response to during the low power consumption mode externally the external control signal that receives of terminal withdraw from the low power consumption mode, be stored in data in the flash memory cell in the second memory then and transfer to dynamic storage cell in the first memory.

16. method of controlling first memory and second memory, first memory comprises dynamic storage cell, second memory comprises flash memory cell, wherein first memory has the low power consumption mode, in the low power consumption mode, dynamic storage cell is operated the data that do not keep wherein by stoping to upgrade, and the method comprising the steps of:

Before first memory enters the low power consumption mode, the data in the dynamic storage cell that is stored in the first memory are transferred to flash memory cell in the second memory;

Make first memory enter the low power consumption mode by the exterior terminal that the special external control signal is outputed to first memory,

During the low power consumption mode constantly to first memory power supply voltage,

During the low power consumption mode, make first memory withdraw from the low power consumption mode by the exterior terminal that the special external control signal is outputed to first memory; And

After first memory withdraws from the low power consumption mode, the data in the flash memory cell that is stored in the second memory are transferred to dynamic storage cell in the first memory.

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