CN100359607C - Shift register circuit - Google Patents
Shift register circuit Download PDFInfo
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- CN100359607C CN100359607C CNB031412475A CN03141247A CN100359607C CN 100359607 C CN100359607 C CN 100359607C CN B031412475 A CNB031412475 A CN B031412475A CN 03141247 A CN03141247 A CN 03141247A CN 100359607 C CN100359607 C CN 100359607C
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Abstract
The present invention relates to a shift register circuit which has a plurality of cascade shift cache units and comprises a PMOS transistor, a first NMOS transistor, a capacitor, a second NMOS transistor, a third NMOS transistor, a first phase reverser and a second phase reverser, wherein the source electrode of the PMOS transistor is coupled to an output signal of the output terminal of a previous shift cache unit, and the gate electrode is coupled to a reversed phase output signal of a previous shift cache unit; the grid electrode of the first NMOS transistor is connected to the drain electrode of the PMOS transistor, and the drain electrode of the first NMOS transistor is coupled to an input clock signal; the capacitor is connected between the grid electrode and the source electrode of the first NMOS transistor; the grid electrode of the second NMOS transistor is connected to the source electrode of the PMOS transistor, the drain electrode of the second NMOS transistor is connected to the source electrode of the first NMOS transistor, and the source electrode of the second NMOS transistor is connected to a grounded power source; the grid electrode of the third NMOS transistor is connected to the output terminal of a rear shift cache unit, and the drain electrode of the third NMOS transistor is connected to a connection point between the capacitor and the grid electrode of the first NMOS transistor, and the source electrode of the third NMOS transistor is connected to the grounded power source; the first phase reverser is connected to the first NMOS transistor; the second phase reverser is connected with the first phase reverser and outputs an output signal.
Description
Technical field
The present invention is relevant for a kind of shift register circuit, particularly relevant for a kind of shift register circuit that is applied to LCD (1iquid crystal display).
Background technology
Fig. 1 represents the patent number US 5 that Weisbrod proposed in nineteen ninety-five, 410,583 disclosed traditional shift register circuit (shift register) circuit structures, only show single level shift cache unit in Fig. 1, the shift cache unit of a plurality of serial connections can constitute complete shift register circuit.As shown in Figure 1, after input signal is imported by input end (INPUT), control nmos pass transistor 12 conductings and shutoff by the source electrode output of nmos pass transistor 10, when nmos pass transistor 12 conductings, output terminal (OUTPUT) gets final product the level of clock signal C1.Yet the nmos pass transistor 10 of conducting this moment can be considered a diode, and the signal level that therefore can cause controlling nmos pass transistor 12 reduces.
The conducting state of clock signal C 2 may command nmos pass transistors 14, when clock signal C2 is high level, nmos pass transistor 14 conductings, and conducting nmos pass transistor 16 is with the voltage level of drop-down output terminal (OUTPUT).In addition, the output signal of the shift cache unit of following two-stage feeds back to the conducting state of the grid of nmos pass transistor 18 with control nmos pass transistor 18, when nmos pass transistor 18 conductings, the grid level of nmos pass transistor 12 promptly descends rapidly, therefore nmos pass transistor 12 turn-offs, and output terminal stops output data.
Yet traditional shift register circuit need provide two kinds of input clocks (C1 and C2), so the clock generator has more stray capacitance, and has increased power attenuation.Moreover, because the feedback path of traditional shift register circuit is long, must control output at the corresponding levels by the output signal of following two-stage, more increase the weight of the difficulty of circuit trace configurations.
Summary of the invention
In view of this, in order to solve described problem, fundamental purpose of the present invention is to provide a kind of shift register circuit, and shift cache units at different levels only need the clock signal that provides single, and less signal source stray capacitance can reduce the loss of power.Moreover therefore the feedback signal series of shift cache units at different levels significantly reduces the complexity of circuit layout design from the output signal of adjacent levels.
For reaching described purpose, the present invention proposes a kind of shift register circuit, has the shift cache unit of a plurality of tandems, is applicable to a clock signal, and described shift cache unit comprises following assembly.The first transistor has first grid, first drain electrode and first source electrode, and first grid is connected to the output terminal of the shift cache unit of last tandem, and first drain electrode is connected to first power supply.Transistor seconds has second grid, second drain electrode and second source electrode, and second grid is connected to the output terminal of the shift cache unit of back one tandem, and second drain electrode is connected to first source electrode, and second source electrode is connected to second source.The 3rd transistor has the 3rd grid, the 3rd drain electrode and the 3rd source electrode, and the 3rd grid is connected to second grid, and the 3rd drain electrode is connected to first power supply.The 4th transistor has the 4th grid, the 4th drain electrode and the 4th source electrode, and the 4th grid is connected to first grid, and the 4th drain electrode is connected to the 3rd source electrode, and the 4th source electrode is connected to second source.The 5th transistor has the 5th grid, the 5th bushing and the 5th source electrode, and the 5th grid is connected to the 3rd source electrode, and the 5th drain electrode is connected to the tie point of first source electrode and second drain electrode, and the 5th source electrode is connected to second source.The 6th transistor has the 6th grid, the 6th drain electrode and the 6th source electrode, and the 6th grid is connected to the 5th drain electrode, and the 6th drain electrode couples clock signal, and the 6th source electrode is connected to output terminal.The 7th transistor has the 7th grid, the 7th drain electrode and the 7th source electrode, and the 7th grid is connected to the 5th grid, and the 7th drain electrode is connected to output terminal, and the 7th source electrode is connected to second source.
The invention provides a kind of shift cache unit, be applicable to a data-signal, a clock signal, first power supply and second source.Described shift cache unit comprises: a first transistor, have a first grid, one first drain electrode and one first source electrode, and described first grid couples one first input signal, and described first drain electrode is connected to described first power supply; One transistor seconds has a second grid, one second drain electrode and one second source electrode, and described second grid couples one second input signal, and described second drain electrode is connected to described first source electrode, and described second source electrode is connected to described second source; One the 3rd transistor has one the 3rd grid, one the 3rd drain electrode and one the 3rd source electrode, and described the 3rd grid is connected to described second grid, and described the 3rd drain electrode is connected to described first power supply; One the 4th transistor has one the 4th grid, one the 4th drain electrode and one the 4th source electrode, and described the 4th grid is connected to described first grid, and described the 4th drain electrode is connected to described the 3rd source electrode, and described the 4th source electrode is connected to described second source; One the 5th transistor, have one the 5th grid, one the 5th drain electrode and one the 5th source electrode, described the 5th grid is connected to described the 3rd source electrode, and described the 5th drain electrode is connected to the tie point of described first source electrode and second drain electrode, and described the 5th source electrode is connected to described second source; One the 6th transistor has one the 6th grid, one the 6th drain electrode and one the 6th source electrode, and described the 6th grid is connected to described the 5th drain electrode, and described the 6th drain electrode couples described clock signal, and described the 6th source electrode is connected to an output terminal; And one the 7th transistor, having one the 7th grid, one the 7th drain electrode and one the 7th source electrode, described the 7th grid is connected to described the 5th grid, and described the 7th drain electrode is connected to described output terminal, and described the 7th source electrode is connected to described second source.Wherein said first input signal is the signal by the circuit output of having of the last tandem circuit structure identical with described shift cache unit; Described second input signal is the signal by the circuit output with circuit structure identical with described shift cache unit of back one tandem.
In addition, the present invention proposes a kind of shift register circuit, has the shift cache unit of a plurality of tandems, comprises following assembly.The PMOS transistor has first grid, first drain electrode and first source electrode, first source electrode couples the output signal that the output terminal of the shift cache unit of last tandem is exported, and first grid couples the reversed-phase output signal that the shift cache unit of last tandem is exported.First nmos pass transistor has second grid, second drain electrode and second source electrode, and second grid is connected to first drain electrode, and second drain electrode couples an input clock signal.Capacitor is connected between the second grid and second source electrode.Second nmos pass transistor has the 3rd grid, the 3rd drain electrode and the 3rd source electrode, and the 3rd grid is connected to first source electrode, and the 3rd drain electrode is connected to second source electrode, and the 3rd source electrode is connected to earthing power supply.The 3rd nmos pass transistor has the 4th grid, the 4th drain electrode and the 4th source electrode, and the 4th grid is connected to the output terminal of the shift cache unit of back one tandem, and the 4th drain electrode is connected to the tie point of second grid and capacitor, and the 4th source electrode is connected to earthing power supply.First phase inverter is connected to the tie point of first nmos pass transistor and second nmos pass transistor, in order to the output reversed-phase output signal.Second phase inverter is connected with first phase inverter, in order to export an output signal.
For described purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 represents the circuit structure of traditional shift register circuit.
Fig. 2 represents the circuit structure diagram according to the described shift cache unit of first embodiment of the invention.
Fig. 3 represents the circuit structure diagram according to the described shift cache unit serial connections at different levels of first embodiment of the invention.
Fig. 4 represents the sequential chart according to the described shift register circuit of the embodiment of the invention.
Fig. 5 represents the circuit structure diagram according to the described shift cache unit serial connections at different levels of second embodiment of the invention.
Symbol description:
10,12,14,16,18,20,21,22,23,24,25,26,52,54,55,71:NMOS transistor
31A, 31B, 31C, 50A, 50B, 50C: shift cache unit
The 51:PMOS transistor
53,72: capacitor
56,57,70: phase inverter
A, B, C, D: node
C1, C2, CK, XCK: clock signal
INPUT, IN: input end
OUTPUT, OUT: output terminal
VDD: first power supply
VSS: second source
XIN: inverting input
Embodiment
First embodiment:
According to the described shift register circuit of the embodiment of the invention, be that the shift cache unit by a plurality of serial connections constitutes.The inner structure of each shift cache unit is below described.
Consult Fig. 2, Fig. 2 represents the circuit structure diagram according to the described shift cache unit of first embodiment of the invention, only showing single level shift cache unit at this, is example with N level shift cache unit, and the shift cache unit of a plurality of serial connections can constitute complete shift register circuit.Nmos pass transistor 20 has first grid, first drain electrode and first source electrode.First grid is connected to output terminal (N-1) OUT of the shift cache unit of last tandem (N-1 level), and first drain electrode is connected to first power supply (VDD).Nmos pass transistor 21 has second grid, second drain electrode and second source electrode.Second grid is connected to output terminal (N+1) OUT of the shift cache unit of back one tandem (N+1 level), and the second drain electrode system is connected with first source electrode, and second source electrode is connected to second source (VSS).Nmos pass transistor 22 has the 3rd grid, the 3rd drain electrode and the 3rd source electrode.The 3rd grid is connected to second grid, and the 3rd drain electrode is connected to first power supply (VDD).Nmos pass transistor 23 has the 4th grid, the 4th drain electrode and the 4th source electrode.The 4th grid is connected to first grid, and the 4th drain electrode is connected to the 3rd source electrode, and the 4th source electrode is connected to second source (VSS).Nmos pass transistor 24 has the 5th grid, the 5th drain electrode and the 5th source electrode.The 5th grid is connected to the 3rd source electrode, and the 5th drain electrode is connected to the tie point of first source electrode and second drain electrode, and the 5th source electrode is connected to second source (VSS).Nmos pass transistor 25 has the 6th grid, the 6th drain electrode and the 6th source electrode.The 6th grid is connected to the 5th drain electrode, and the outside clock signal C K that is provided is provided in the 6th drain electrode, and the 6th source electrode is output terminal (N) OUT of data.Nmos pass transistor 26 has the 7th grid, the 7th drain electrode and the 7th source electrode.The 7th grid is connected to the 5th grid, and the 7th drain electrode is connected to described output terminal (N) OUT, and the 7th source electrode is connected to second source (VSS).
Receive output terminal (N-1) OUT of the shift cache unit of last tandem (N-1 level) when the grid of nmos pass transistor 20, during the high level signal exported, nmos pass transistor 20 conductings, the voltage that the power supply of winning (VDD) is provided passes through nmos pass transistor 20 and conducting nmos pass transistor 25, so output terminal (N) OUT clock signal CK is to the next stage shift cache unit.In addition, because the output of next stage shift cache unit system feeds back to the grid of nmos pass transistor 21 and nmos pass transistor 22, therefore when the next stage shift cache unit was output as high level signal, nmos pass transistor 22 meeting conductings were so that the voltage turn-on nmos pass transistor 24 that first power supply (VDD) is provided.So the nmos pass transistor of conducting 21 and nmos pass transistor 24 so that nmos pass transistor 25 turn-offs, therefore stop output data with the voltage level of the grid of pull-down NMOS transistor 25.
Fig. 3 represents the circuit structure diagram according to the described shift cache unit serial connections at different levels of first embodiment of the invention.As shown in the figure, the shift cache unit of label 31A:31C representative serial connection.Fig. 4 represents the sequential chart according to the described shift register circuit of the embodiment of the invention.With Fig. 3 is example, and (N-1) OUT represents the output of shift cache unit 31A, and (N) OUT represents the output of shift cache unit 31B, and (N+1) OUT represents the output of shift cache unit 31C.As shown in the figure, according to the described shift register circuit of the embodiment of the invention, the output signal of shift cache units at different levels all differs the time of a clock period, meets the requirement of shift register circuit.
Second embodiment:
According to the described shift register circuit of the embodiment of the invention, be that the shift cache unit by a plurality of serial connections is constituted.It below is the inner structure of describing each shift cache unit.
Fig. 5 represents the circuit structure diagram according to the described shift cache unit serial connections at different levels of second embodiment of the invention.As shown in the figure, the shift cache unit of label 50A:50C representative serial connection, because the structure of each shift cache unit is identical, the circuit structure of shift cache unit 50B below only is described, is that N level shift cache unit, shift cache unit 50A are that (N-1) level shift cache unit and shift cache unit 50C are that (N+1) level shift cache unit is an example at this with shift cache unit 50B.
The source electrode of PMOS transistor 51 couples the output signal that the output terminals A of the shift cache unit 50A of last tandem is exported, its grid couples the reversed-phase output signal that the shift cache unit of last tandem is exported, this reversed-phase output signal is exported by Node B, has a phase inverter 70 between node A and the Node B.The grid of nmos pass transistor 52 is connected to the drain electrode of PMOS transistor 51, and its drain electrode couples clock signal XCK.In this situation that adopts the PMOS transistor can avoid conventional art (as shown in Figure 1) to cause incoming signal level to reduce in input end use nmos pass transistor.
When the clock signal C K of shift cache unit 50A is low level, the exit point A output high level signal of shift cache unit 50A, this moment, Node B was a low level signal, therefore PMOS transistor 51 and nmos pass transistor 54 conductings, so the voltage level of node D raises in capacitor 53 two ends formation voltage difference.When the clock signal C K of shift cache unit 50A becomes low level, the clock signal XCK of input shift cache unit 50B is a high level, exit point A output low level signal owing to shift cache unit 50A this moment, therefore nmos pass transistor 54 turn-offs, the formed voltage difference in capacitor 53 two ends this moment causes nmos pass transistor 52 conductings, make shift cache unit 50B export high level signal, this high level signal feed back to simultaneously shift cache unit 50A nmos pass transistor 71 grid and make its conducting, make the potential difference (PD) at capacitor 72 two ends of shift cache unit 50A eliminate.
Fig. 4 represents the sequential chart according to the described shift register circuit of the embodiment of the invention.As shown in the figure, according to the described shift register circuit of the embodiment of the invention, the output signal of shift cache units at different levels all differs the time of a clock period, meets the requirement of shift register circuit.
In sum, according to shift register circuit provided by the present invention, shift cache units at different levels only need the clock signal that provides single, effectively reduce the loss of power.Moreover the feedback signal series of shift cache units at different levels is from the output signal of next stage, must be provided by the shift cache unit of two-stage down compared to the feedback signal of conventional art, significantly reduces the complexity of circuit design.
Though the present invention with preferred embodiment openly as above; so it is not in order to limit scope of the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (5)
1. shift register circuit, the shift cache unit with a plurality of tandems is applicable to a clock signal, first power supply and second source, described shift cache unit comprises:
One the first transistor has a first grid, one first drain electrode and one first source electrode, and described first grid is connected to the output terminal of the shift cache unit of last tandem, and described first drain electrode is connected to described first power supply;
One transistor seconds, have a second grid, one second drain electrode and one second source electrode, described second grid is connected to the output terminal of the shift cache unit of back one tandem, and described second drain electrode is connected to described first source electrode, and described second source electrode is connected to described second source;
One the 3rd transistor has one the 3rd grid, one the 3rd drain electrode and one the 3rd source electrode, and described the 3rd grid is connected to described second grid, and described the 3rd drain electrode is connected to described first power supply;
One the 4th transistor has one the 4th grid, one the 4th drain electrode and one the 4th source electrode, and described the 4th grid is connected to described first grid, and described the 4th drain electrode is connected to described the 3rd source electrode, and described the 4th source electrode is connected to described second source;
One the 5th transistor, have one the 5th grid, one the 5th drain electrode and one the 5th source electrode, described the 5th grid is connected to described the 3rd source electrode, and described the 5th drain electrode is connected to the tie point of described first source electrode and second drain electrode, and described the 5th source electrode is connected to described second source;
One the 6th transistor has one the 6th grid, one the 6th drain electrode and one the 6th source electrode, and described the 6th grid is connected to described the 5th drain electrode, and described the 6th drain electrode couples described clock signal, and described the 6th source electrode is connected to an output terminal; And
One the 7th transistor has one the 7th grid, one the 7th drain electrode and one the 7th source electrode, and described the 7th grid is connected to described the 5th grid, and described the 7th drain electrode is connected to described output terminal, and described the 7th source electrode is connected to described second source.
2. as claim 1 a described shift register circuit, wherein said transistor is a nmos pass transistor.
3. a shift cache unit is applicable to a data-signal, a clock signal, first power supply and second source, and described shift cache unit comprises:
One the first transistor has a first grid, one first drain electrode and one first source electrode, and described first grid couples one first input signal, and described first drain electrode is connected to described first power supply;
One transistor seconds has a second grid, one second drain electrode and one second source electrode, and described second grid couples one second input signal, and described second drain electrode is connected to described first source electrode, and described second source electrode is connected to described second source;
One the 3rd transistor has one the 3rd grid, one the 3rd drain electrode and one the 3rd source electrode, and described the 3rd grid is connected to described second grid, and described the 3rd drain electrode is connected to described first power supply;
One the 4th transistor has one the 4th grid, one the 4th drain electrode and one the 4th source electrode, and described the 4th grid is connected to described first grid, and described the 4th drain electrode is connected to described the 3rd source electrode, and described the 4th source electrode is connected to described second source;
One the 5th transistor, have one the 5th grid, one the 5th drain electrode and one the 5th source electrode, described the 5th grid is connected to described the 3rd source electrode, and described the 5th drain electrode is connected to the tie point of described first source electrode and second drain electrode, and described the 5th source electrode is connected to described second source;
One the 6th transistor has one the 6th grid, one the 6th drain electrode and one the 6th source electrode, and described the 6th grid is connected to described the 5th drain electrode, and described the 6th drain electrode couples described clock signal, and described the 6th source electrode is connected to an output terminal; And
One the 7th transistor has one the 7th grid, one the 7th drain electrode and one the 7th source electrode, and described the 7th grid is connected to described the 5th grid, and described the 7th drain electrode is connected to described output terminal, and described the 7th source electrode is connected to described second source;
Wherein said first input signal is the signal by the circuit output of having of the last tandem circuit structure identical with described shift cache unit; Described second input signal is the signal by the circuit output with circuit structure identical with described shift cache unit of back one tandem.
4. as claim 3 a described shift cache unit, wherein said transistor is a nmos pass transistor.
5. shift register circuit, the shift cache unit with a plurality of tandems is applicable to a clock signal and an earthing power supply, described shift cache unit comprises:
One PMOS transistor, have a first grid, one first drain electrode and one first source electrode, described first source electrode couples the output signal that the output terminal of the shift cache unit of last tandem is exported, and described first grid couples the reversed-phase output signal that the shift cache unit of last tandem is exported;
One first nmos pass transistor has a second grid, one second drain electrode and one second source electrode, and described second grid is connected to described first drain electrode, and described second drain electrode couples described clock signal;
One capacitor is connected between the described second grid and second source electrode;
One second nmos pass transistor has one the 3rd grid, one the 3rd drain electrode and one the 3rd source electrode, and described the 3rd grid is connected to described first source electrode, and described the 3rd drain electrode is connected to described second source electrode, and described the 3rd source electrode is connected to described earthing power supply;
One the 3rd nmos pass transistor, have one the 4th grid, one the 4th drain electrode and one the 4th source electrode, described the 4th grid is connected to the output terminal of the shift cache unit of back one tandem, described the 4th drain electrode is connected to the tie point of described second grid and described capacitor, and described the 4th source electrode is connected to described earthing power supply;
One first phase inverter as a reversed-phase output, is connected to the tie point of described first nmos pass transistor and second nmos pass transistor, in order to export a reversed-phase output signal; And
One second phase inverter as an output terminal, is connected to described first phase inverter, in order to export an output signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031412475A CN100359607C (en) | 2003-06-04 | 2003-06-04 | Shift register circuit |
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| CNB031412475A CN100359607C (en) | 2003-06-04 | 2003-06-04 | Shift register circuit |
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| CN100359607C true CN100359607C (en) | 2008-01-02 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446127C (en) * | 2005-10-12 | 2008-12-24 | 友达光电股份有限公司 | Shift register circuit |
| US7432737B2 (en) * | 2005-12-28 | 2008-10-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and electronic device |
| TWI326445B (en) | 2006-01-16 | 2010-06-21 | Au Optronics Corp | Shift register turning on a feedback circuit according to a signal from a next stage shift register |
| TWI406503B (en) * | 2010-12-30 | 2013-08-21 | Au Optronics Corp | Shift register circuit |
| CN102708925B (en) * | 2011-05-26 | 2015-08-12 | 京东方科技集团股份有限公司 | Shift register for thin-film transistor and application process thereof |
| TWI500265B (en) * | 2012-11-22 | 2015-09-11 | Au Optronics Corp | Shift register |
| CN104008779B (en) * | 2014-05-27 | 2017-03-15 | 上海天马有机发光显示技术有限公司 | Shift register and its driving method, shift register group and its driving method |
| TWI651638B (en) * | 2018-02-13 | 2019-02-21 | 友達光電股份有限公司 | Touch sensing device |
| CN108847174B (en) * | 2018-07-03 | 2021-01-26 | 京东方科技集团股份有限公司 | Shift register circuit and driving method thereof, gate drive circuit and display panel |
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| US4733111A (en) * | 1985-07-17 | 1988-03-22 | CSELT--Centro Studi e Laboratori Telecomunicazioni S.p.A. | Sequential-logic basic element in CMOS technology operating by a single clock signal |
| CN1116752A (en) * | 1993-10-28 | 1996-02-14 | Rca汤姆森许可公司 | Shift register useful as a select line scanner for a liquid crystal |
| US6339631B1 (en) * | 1999-03-02 | 2002-01-15 | Lg. Philips Lcd Co., Ltd. | Shift register |
| CN1395256A (en) * | 2001-06-29 | 2003-02-05 | 卡西欧计算机株式会社 | Shift register and electronic device |
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2003
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4733111A (en) * | 1985-07-17 | 1988-03-22 | CSELT--Centro Studi e Laboratori Telecomunicazioni S.p.A. | Sequential-logic basic element in CMOS technology operating by a single clock signal |
| CN1116752A (en) * | 1993-10-28 | 1996-02-14 | Rca汤姆森许可公司 | Shift register useful as a select line scanner for a liquid crystal |
| US6339631B1 (en) * | 1999-03-02 | 2002-01-15 | Lg. Philips Lcd Co., Ltd. | Shift register |
| CN1395256A (en) * | 2001-06-29 | 2003-02-05 | 卡西欧计算机株式会社 | Shift register and electronic device |
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