CN100351819C - Disk array system with error ending and load balancing - Google Patents
Disk array system with error ending and load balancing Download PDFInfo
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- CN100351819C CN100351819C CNB2004100806194A CN200410080619A CN100351819C CN 100351819 C CN100351819 C CN 100351819C CN B2004100806194 A CNB2004100806194 A CN B2004100806194A CN 200410080619 A CN200410080619 A CN 200410080619A CN 100351819 C CN100351819 C CN 100351819C
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Abstract
The present invention relates to a magnetic disk array system with error ending and load balancing functions, which is used for storing data of a host computer. The present invention comprises a microprocessor, a first bus line, at least one controller, a storage, a second bus line and a plurality of magnetic disks, wherein the microprocessor is controlled by software to process the running the host computer and has error ending and load balancing functions; the first bus line transmits data output by the microprocessor and is provided with a plurality of first communication channels; the controller is used for connecting the first bus line; the storage is used for connecting the controller and has the function of storing instructions transferred by the microprocessor and buffering data; the second bus line is used for connecting the controller and is provided with a plurality of second communication channels; the magnetic disks are used for connecting the communication channels.
Description
Technical field
The invention relates to a kind of disc array system, in particular to a kind of disc array system with error ending and load balance.
Background technology
Modern computer system needs a large amount of storage devices to hold the lot of data demand, and the disc array system (RAID) of controlling a plurality of disks in conjunction with controller by a main frame is the solution that the computing machine dealer usually provides.More complete data storage system must possess the data schedule backup, detects wrong disk, the function of detecting mistake controller and equilibrium criterion load balance.Above-mentioned functions can be by the main frame host bus adapting card (HBA) of arranging in pairs or groups, connect the running of a plurality of disks and reach by controller, as mentioning to have the host computer of host bus adapting card in the United States Patent (USP) No. 6578158 " method and device thereof with error of transmission termination and error back Magnetic Disk Controller are provided ", respectively connect two identical data transmission port and error ending ports with two breakout boxs (hub) with controller of data transmission and error ending function, these two controllers are controlled a plurality of disks, its function mode is that the data in the main frame are conveyed in the disk via the data transmission port of controller through two breakout boxs and store, and the data in the disk also can transfer in the main frame via identical approach and operate.Controller and disk have identity identification device (uniqueidentifier) and logic unit number (logic unit number) respectively, interrelate with main frame, having channel between the controller simultaneously links up mutually, this channel can be small computer system interface (Small Computer System Interface),, whether normal between the controller to determine the controller running constantly with " ping " signal communicating information each other.Under general situation, the main frame data transfer to disk by a master controller and place, certainly disk can return data to main frame by this master controller too and deal with, when controller " ping " the other side, can't receive the other side's response message, operate normal controller and judge that just the other side is in the state that can't operate, this error ending port that operates normal controller receives and writes down the identity identification device and the logic unit number of the controller that can't operate, and, keep the normal operation of disc array system whereby by the data that the transmission of error ending port is originally transmitted by the data transmission port of controller that can't normal operation.The benefit of this technology is that controller has data transmission and error ending function, do not need main frame operating system to handle the error event of disk or the incident that controller can't operate, yet the cost costliness of this technology, need outside the cost of breakout box, the controller that more needs to have function sets up this cover disc array system, common people can't load so expensive expensive, and the dealer just taxes one's ingenuity to develop the with low cost and practical disc array system of a cover to address the above problem.
Summary of the invention
Fundamental purpose of the present invention is to be to provide a kind of disc array system, it has a software that is installed on the main frame, this software has the function of termination of control disk error and data payload balance, can utilize the high-performance microprocessor on the main frame to carry out the error ending of disc array system and the function of data payload balance, saving known techniques need be to have the cost that the control disk error stops and the data payload balance controller operates.
Secondary objective of the present invention is to be to provide a kind of controller, can transmit data and give each disk.
Another purpose of the present invention is to be to provide a kind of storer, can have storage instruction and data buffering function.
Another purpose of the present invention is to be to provide a kind of SATA bus, can give disc storage with the data transmission of main frame, or will be stored in data in the disk and return to main frame and handle.
A kind of disc array system of the present invention stores the data of a main frame in the mode with fault-tolerant processing, and it comprises: a microprocessor to handle the running of this main frame, has the function of error ending and load balance by a software control; One first bus connects this microprocessor, and this first bus has a plurality of first channels; One controller connects this first bus, and described controller comprises storer, disk array processor and second bus; Described storer connects the disk array processor of this controller, has the function of storage instruction and data buffering; Described second bus is connected in the disk array processor of this controller, and this second bus has a plurality of second channels; And a plurality of disks, these a plurality of disks connect these a plurality of second channels.
Description of drawings
Fig. 1 is the hardware structure synoptic diagram of disc array system of the present invention;
Fig. 2 is the operation workflow figure of disc array system of the present invention;
Fig. 3 is the embodiment synoptic diagram of disc array system of the present invention;
Fig. 4 is the embodiment synoptic diagram of disc array system of the present invention;
Fig. 5 is the embodiment synoptic diagram of disc array system of the present invention;
Fig. 6 is the embodiment synoptic diagram of disc array system of the present invention.
Symbol description:
100～main frame, 110～microprocessor
120～bus, 131～channel
132～channel, 133～channel
134～channel, 200～controller
210～disk array processor, 220～storer
231～channel, 232～channel
233～channel, 234～channel
240～bus, 250～bus
261～channel, 262～channel
263～channel, 264～channel
270～disk, 300～data ABCD
310～data A, 311～data A/3
312～data A/2,320～data B
322～data B/2,330～data C
340～data D
Embodiment
A kind of disc array system of the present invention is to utilize a kind of software that is installed on the host computer, carry out the processing on the data transmission problems between disc array system and the host microprocessors, its hardware structure as shown in Figure 1, main frame 100 contains the software microprocessor 110 of (figure does not show) is installed, this software has the channel 131-134 that can't operate, 231-234 cease to function (fail over) return to the data of main frame with the data that microprocessor is transmitted out or by disk and make load balance (load balance), the microprocessor 110 of main frame 100 transfers out main frame 100 via bus 120 via channel 131-134 with data, and be transmitted in the controller 200 via channel 231-234, bus 240 via controller 200 is transmitted into disk array processor 210, storer 220 stores error ending and load balance instruction and data buffering function, data are done reduction and are transferred to bus 250, and be transmitted into hard disk 270 via channel 261-264 and deposit, the data in the hard disk 270 also receive same instructions according to same paths and return microprocessor to main frame 100.
The operation workflow of disc array system please refer to shown in Figure 2, at first by the 110 running software startup host bus adapting card-steps 410 of the microprocessor in the main frame 100, restart controller 200-step 420, then begin System Operation, carry out the data transmission between main frame 100 and the disk 270, transmission manner is that data are at microprocessor 110,210 accept the indication of load balance in the software, data are divided into several portions then divides and tasks each channel 131-134,231-234 is transferred to bus 120,240 in microprocessor 110 that transfers to main frame 100 or hard disk 270-step 430, the SATA channel 131-134 of main frame 100 can be automatically ceaselessly sensing channel whether operate normally-step 440, wherein there is channel to break down if detect, the microprocessor 110 of main frame 100 just sees through software and assigns the instruction-step 450 that stops this damages channel operating, and then the microprocessor 110 of main frame 100 is just assigned the instruction of load balance and will be originally operated normal channel transmission-step 460 via the data of this damage channel transmission with other.
It below is a preferred embodiment of the present invention, data can deposit to disk 270 data transfer via controller 200 by the microprocessor 110 of main frame 100 in the disc array system, and emphasis of the present invention just is to reach with software the function of channel error termination and load balance, guarantees that the transmission of data is no problem.Please refer to Fig. 1 and shown in Figure 3, under normal operation, the microprocessor 110 of main frame 100 or the disk array processor 210 of controller 200 are divided into data (A) 310 with data (ABCD) 300, data (B) 320, data (C) 330, data (D) 340 4 parts, via bus 120 four partial data branches are delivered to channel 131-134 and transfer out main frame 100, be transmitted into again in channel 231-234 sends into controller 200 via bus 240 the disk array processor 210 data (A) 310, data (B) 320, data (C) 330, data (D) 340 are reduced to data (ABCD) 300 and pass to disk 270 via bus 250 via channel 261-264 and deposit.
Please refer to Fig. 1 and shown in Figure 4, when microprocessor 110 detects communication between channel 131 and the channel 231 when not normal, microprocessor 110 at first stops the running between channel 131 and the channel 231, follow the data (A) 310 that to transmit by channel 131 and channel 231 originally and be divided into three piece of data (A/3) 311 also respectively together with data (B) 320, data (C) 330, data (D) 340 transfer out main frame 100 by channel 132-134, are transmitted in channel 232-234 sends into controller 200 via bus 240 the disk array processor 210 three piece of data (A/3) 311 again, data (B) 320, data (C) 330, data (D) 340 are reduced to data (ABCD) 300 and pass to disk 270 via bus 250 via channel 261-264 and deposit.
Please refer to Fig. 1 and shown in Figure 5, when microprocessor 110 detects communication between channel 131 and the channel 231 and the communication between channel 132 and the channel 232 when all not normal, microprocessor 110 at first stops the running between channel 131 and channel 231 and channel 132 and the channel 232, then the original data of transmitting by channel 131 and channel 231 (A) 310 are divided into two piece of data (A/2) 312 and original data (B) 320 by channel 132 and channel 232 transmission are divided into two piece of data (B/2) 322 also respectively together with data (C) 330, data (D) 340 transfer out main frame 100 by channel 133-134, are transmitted in channel 233-234 sends into controller 200 via bus 240 the disk array processor 210 two piece of data (A/2) 312 again, two piece of data (B/2) 322, data (C) 330, data (D) 340 are reduced to data (ABCD) 300 and pass to disk 270 via bus 250 via channel 261-264 and deposit.
Please refer to Fig. 1 and shown in Figure 6, when microprocessor 110 detects communication between channel 131 and the channel 231, when the communication between communication between channel 132 and the channel 232 and channel 133 and the channel 233 is all not normal, microprocessor 110 at first stops channel 131 and channel 231, running between communication between channel 132 and the channel 232 and channel 133 and the channel 233, then will be originally by the data (A) 310 of channel 131 with channel 231 transmission, transfer out main frame 100 together with data (D) 340 by channel 134 with data (C) 330 that channel 233 transmits with the data (B) 320 of channel 232 transmission and by channel 133 by channel 132, be transmitted into channel 234 again and send into via bus 240 in the disk array processor 210 of controller 200 data (A) 310, data (B) 320, data (C) 330, data (D) 340 are reduced to data (ABCD) 300 and pass to disk 270 via bus 250 via channel 261-264 and deposit.
The present invention utilizes the operating capability of high-performance microprocessor on the existing host microprocessors, the controller architecture of simplifying with software and function goes out high-transmission ability, disc array system with low cost, the integrality of control disc array system data transmission, save known techniques and must handle disc array system, about the disappearance of channel termination, load balance with expensive hardware control.
Claims (6)
1. disc array system with error ending and load balance is in order to storing the data of a main frame, it is characterized in that described disc array system with error ending and load balance comprises:
One microprocessor, control is used for error ending and load balance to handle the running of this main frame;
One first bus is transmitted the data that this microprocessor is exported, and this first bus has a plurality of first channels;
At least one controller connects this first bus, and described controller comprises storer, disk array processor and second bus;
Described storer connects the disk array processor of this controller, has the function of storage instruction and data buffering;
Described second bus is connected in the disk array processor of this controller, and this second bus has a plurality of second channels;
A plurality of disks, these a plurality of disks connect these a plurality of second channels.
2. a kind of disc array system with error ending and load balance according to claim 1 is characterized in that: by this first bus of this microprocessor driven to carry out the transmission of this host data.
3. a kind of disc array system with error ending and load balance according to claim 2 is characterized in that: by this this controller of first bus rear drive of this microprocessor driven.
4. a kind of disc array system according to claim 3 with error ending and load balance, it is characterized in that: this microprocessor is detected the wrong of at least one first channel of this disc array system and is stopped its running, and the data of delivering to first channel of this mistake originally all are distributed into normal first channel.
5. a kind of disc array system according to claim 4 with error ending and load balance, it is characterized in that: wherein normal first channel also needs to transmit the data that the first wrong channel is all given normal first channel except transmitting the data of distributing originally.
6. a kind of disc array system with error ending and load balance according to claim 1 is characterized in that: this first bus and this second bus are to be the Serial ata bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100806194A CN100351819C (en) | 2004-09-29 | 2004-09-29 | Disk array system with error ending and load balancing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100806194A CN100351819C (en) | 2004-09-29 | 2004-09-29 | Disk array system with error ending and load balancing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1755654A CN1755654A (en) | 2006-04-05 |
| CN100351819C true CN100351819C (en) | 2007-11-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100806194A Expired - Fee Related CN100351819C (en) | 2004-09-29 | 2004-09-29 | Disk array system with error ending and load balancing |
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| Country | Link |
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| CN (1) | CN100351819C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275240B1 (en) * | 1999-05-27 | 2001-08-14 | Intel Corporation | Method and apparatus for maintaining load balance on a graphics bus when an upgrade device is installed |
| US6578158B1 (en) * | 1999-10-28 | 2003-06-10 | International Business Machines Corporation | Method and apparatus for providing a raid controller having transparent failover and failback |
| CN1487428A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Controller for outer multi-channel network disc array and its protocol fitting method |
-
2004
- 2004-09-29 CN CNB2004100806194A patent/CN100351819C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275240B1 (en) * | 1999-05-27 | 2001-08-14 | Intel Corporation | Method and apparatus for maintaining load balance on a graphics bus when an upgrade device is installed |
| US6578158B1 (en) * | 1999-10-28 | 2003-06-10 | International Business Machines Corporation | Method and apparatus for providing a raid controller having transparent failover and failback |
| CN1487428A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Controller for outer multi-channel network disc array and its protocol fitting method |
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| Publication number | Publication date |
|---|---|
| CN1755654A (en) | 2006-04-05 |
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