CN100350260C - Device and method for transmitting hidden signal in boundary scan test interface - Google Patents
Device and method for transmitting hidden signal in boundary scan test interface Download PDFInfo
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- CN100350260C CN100350260C CNB2004100048280A CN200410004828A CN100350260C CN 100350260 C CN100350260 C CN 100350260C CN B2004100048280 A CNB2004100048280 A CN B2004100048280A CN 200410004828 A CN200410004828 A CN 200410004828A CN 100350260 C CN100350260 C CN 100350260C
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Abstract
The present invention relates to a device and a method fro transmitting hidden signal in a marginal scan test interface. A null state loop is defined in the marginal scan test interface, and the input of a state transfer graph of the marginal scan test interface is monitored at the beginning of the marginal scan test interface; thereby, when a first preset input string is detected, the output of first data of the first preset input string, which meets the null state loop, is generated, and the output of second data is generated when a second preset input string is detected, wherein the second preset input string is different from the first preset input string and is an input string meeting the null state loop.
Description
Technical field
The present invention relates to marginal sweep test interface tech, refer to a kind of apparatus and method that are applicable to transmission hidden signal in the marginal sweep test interface especially.
Background technology
Complicated along with wafer package and multilayer board technology, tradition has been difficult to contact with node on the printed circuit board (PCB) with the test mode of needle-bar, and because the maturing of surface adhering technology, make how IC directly adheres on the surface of circuit, thereby the difficulty that causes the IC internal signal directly to measure.For solving this problem, limit scanning (Boundary scan) technology just in response to and give birth to, the boundary scan of JTAG (Joint Test Action Group) for example, its official standard name is called IEE1149.1, and the Digtal Test Access Port interface of IEEE119.4, just defined the marginal sweep test interface that can be used for test I C, it mainly is to carry out the test of IC interior module with sequence scanning chain (Serial scan chain), be illustrated in figure 1 as the interface architecture of JTAG, it adopts five signal pin position (TDI, TDO, TMS, TCK, nTRST) as the operation of scan chain data, wherein, TDI pin position is to import as sequence data, TDO pin position is to export as sequence data, TMS pin position is to import as model selection, TCK pin position is to import as time pulse signal, the function that nTRST pin position then provides system to reset, and as shown in the figure, the JTAG framework include one the test access interface (Test Access Port, TAP) controller 11, one test data working storage 12 (Test data register), one instruction registor 13, and a demoder 14 etc.
In test data working storage 12, one group of scan chain working storage 121 (Scan chain register) provides as one scan chain (Scan chain), can store the tandem data of TDI pin residence input, one identification code working storage 122 is in order to store special numbering, it is only for output, and a bypass working storage 123 is directly to be passed to TDO pin position to export in order to the input with TDI pin position.
This instruction registor 13 is in order to storing the sequence instruction that TDI pin position is imported, and by a demoder 14 decodings to control the running of this TAP controller 11.
This TAP controller 11 promptly carries out the state transfer according to the input of TMS pin position, and according to the decoded result of the data of test data working storage 12 and demoder 14 and operate, Fig. 2 demonstrates the state transfer figure of this TAP controller 11, it is the signal of sampling TMS when the positive edge of TCK and do state transfer, as shown in the figure, when initial, TAP controller 11 is at the Test-LogicReset state, afterwards, it may enter idle processing 21, the data working storage handles 22, and instruction registor is handled three partial status such as 23, wherein, be input as 1 as TMS, the Test-LogicReset state remains unchanged, and when TMS was input as 0, the state transfer was idle 21 the Run-Test/Idle state of handling; When the Run-Test/Idle state, be input as 0 as TMS, the Run-Test/Idle state remains unchanged, and when TMS was input as 1,22 Select-DR-Scan state was handled in the state transfer for the data working storage; When the Select-DR-Scan state, be input as 0 as TMS, then enter the Capture-DR state, and then carry out processing for test data working storage 12, when TMS was input as 1,23 Select-IR-Scan state was handled in the state transfer for instruction registor; When the Select-IR-Scan state, be input as 0 as TMS, then enter the Capture-IR state, and then carry out processing for instruction registor 13, when TMS is input as 1, the Test-Logic Reset state when the state transfer is initial.
With the framework of above-mentioned JTAG,, all read and write, yet the data reading-writing of TDI and TDO has its gradualness, is detected by the people easily through TDI and TDO pin position for the transmission of controlling signal or the access of working storage.Therefore can't protect for example controlling signal of confidentiality.But in the exploitation of processor now, regular meeting runs into and will protect developing instrument, not by situation that other people usurp.So how in marginal sweep test Interface Standard, to protect the transmission of the controlling signal of confidentiality, just become a problem that needs to be resolved hurrily.
Summary of the invention
Fundamental purpose of the present invention is the apparatus and method of transmission hidden signal in a kind of marginal sweep test interface is provided; it need not to get final product input signal via the input and output pin position of standard, and is implemented in the purpose of the transmission of protection confidentiality controlling signal in the marginal sweep test Interface Standard.
Another object of the present invention is the apparatus and method of transmission hidden signal in a kind of marginal sweep test interface is provided, so that can be compatible under the marginal sweep test Interface Standard, parse the controlling signal of confidentiality, and do not influence the path of all states of marginal sweep test interface and data fully.
For achieving the above object, the present invention proposes the device of transmission hidden signal in a kind of marginal sweep test interface, this sweep test interface, limit is to operate according to a predetermined state transfer figure, this state transfer figure carries out the state transfer according to an input, wherein, the state transfer of being carried out comprises at least one no active state loop, this device comprises: a state detector, in order to monitor this input, with when having detected one first default input string, produce the output of one first data, afterwards, when having detected one second default input string, the output that produces one second data, wherein, this first default input string and the second default input string are the different input strings that meet this adiaphorous state loop.
The device of transmission hidden signal in the described marginal sweep test interface, it more comprises a shift registor, in order to store the combination of first and second data that this state detector exports.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this sweep test interface, limit is a JTAG interface, this is input as TMS input.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this sweep test interface, limit is an IEEE1149.1 interface, this is input as TMS input.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, the Digtial Test Access Port interface that this sweep test interface, limit is an IEEE1149.4, this is input as TMS input.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this state transfer figure is initiated at a Test-Logic Reset state, and is input as 1 o'clock state at TMS and remains unchanged, when TMS is input as 0, the state transfer is the Run-Test/Idle state, and be input as at 0 o'clock at TMS, state remains unchanged, when continuous three TMS are input as 1, the state transfer is Test-Logic Reset state, and forms this at least one no active state loop.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this first default input string is ' 0111 ', this second default input string is ' 1 '.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this first data is ' 1 ', this second data is ' 0 '.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this first default input string is
, this second default input string is ' 1 ', in the middle of
Represent at least one 0.
The device of transmission hidden signal in the described marginal sweep test interface, wherein, this first data is ' 1 ', this second data is ' 0 '.
For achieving the above object, the method of transmission hidden signal in a kind of marginal sweep test provided by the invention interface, this sweep test interface, limit is to operate according to a predetermined state transfer figure, this state transfer figure carries out the state transfer according to an input, wherein, the state transfer of being carried out comprises at least one no active state loop, and this method comprises:
(A) monitor this input, with when having detected one first default input string, the output that produces one first data, wherein, this first default input string is an input string that meets this adiaphorous state loop;
(B) monitor this input, when having detected one second default input string, the output that produces one second data, wherein, this second default input string is the input string that is different from this first default input string and meets this adiaphorous state loop.
The method of transmission hidden signal in the described marginal sweep test interface, it more comprises the combination of a step (C) with first and second data of storing this output.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, this sweep test interface, limit is a JTAG interface, this is input as TMS input.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, this sweep test interface, limit is an IEEE1149.1 interface, this is input as TMS input.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, this sweep test interface, limit is one to meet the Digital Test Access Port interface of IEEE1149.4, this is input as TMS input.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, this state transfer figure is initiated at a Test-Logic-Reset state, and is input as 1 o'clock state at TMS and remains unchanged, when TMS is input as 0, the state transfer is the Run-Test/Idle state, and be input as at 0 o'clock at TMS, state remains unchanged, when continuous three TMS are input as 1, the state transfer is Test-Logic Reset state, and forms this at least one no active state loop.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, in step (A), this first default input string is ' 0111 ', and this first data is ' 1 ', and in step (B), this second default input string is ' 1 ', and this second data is ' 0 '.
The method of transmission hidden signal in the described marginal sweep test interface, wherein, in step (A), this first default input string is
, this first data is ' 1 ', in the middle of
Represent at least one 0, and in step (B), this second default input string is ' 1 ', this second data is ' 0 '.
By above explanation as can be known; the present invention is by transmitting hidden signal by adiaphorous state loop among the state transfer figure that uses marginal sweep test interface; need not to get final product input signal via the data input output pin position of standard; can reach the purpose of the transmission of protection confidentiality controlling signal in marginal sweep test interface; and do not influence the path of all states of marginal sweep test interface and data fully, and be compatible to the marginal sweep test interface of standard fully.
Description of drawings
Fig. 1 is the Organization Chart for known JTAG interface;
Fig. 2 is the state transfer figure for the TAP controller at JTAG interface;
Fig. 3 is the Organization Chart according to marginal sweep test of the present invention interface;
Fig. 4 is the adiaphorous state loop that shows among the state transfer figure of TAP controller;
Fig. 5 is the circuit diagram for the confidential data detecting device at foundation marginal sweep test of the present invention interface;
Fig. 6 is the operation workflow figure for state detector.
Embodiment
Your, be described as follows especially exemplified by a preferred embodiment for allowing juror can more understand technology contents of the present invention.
The apparatus and method of transmission hidden signal in the relevant marginal sweep test of the present invention interface, please be earlier with reference to Organization Chart shown in Figure 3, it includes a TAP controller 31, one test data working storage 32, one instruction registor 33, one demoder 34, an and confidential data detecting device 35, wherein, marginal sweep test of the present invention interface can be JTAG, IEEE1149.1, IEEE1149.4 or other similar interfaces, in present embodiment, sweep test interface, limit is to be a JTAG interface, so these TAP controllers 31, test data working storage 32, instruction registor 33, and demoder 34 is to operate according to the standard of JTAG, it adopts sequence data input (TDI), sequence data output (TDO), model selection input (TMS), time pulse signal input (TCK), five signal pin positions such as system's replacement (nTRST) are used as the operation of scan chain data, and aforementioned confidential data detecting device 35 is the inputs that can realize secret signal according to the TMS signal.
Please refer to shown in Figure 2ly again, by the defined state of JTAG standard transfer figure as can be known, under original state, this state transition diagram is at Test-Logic Reset state.When desiring to make the JTAG interface to be failure to actuate, TMS pin position input be continuously 1 (that is, a series of ' 1 ' input is arranged), make it remain on Test-Logic Reset state, when desiring start JTAG interface, just the TMS input is changed into 0 to carry out the state transfer, yet, mistake produces one 0 start JTAG mistakenly in a series of 1 in order to avoid, therefore, be input as 0 and after being passed to the Run-Test/Idle state in TMS pin position, still be continuously 1 as the input of TMS pin position, then state will be via the Select-DR-Scan state, the Select-IR-Scan state, and transfer back initial Test-LogicReset state, in fact only carried out an adiaphorous state loop, and can not enter the state of any actual act, thereby avoid generation of false action.
Fig. 4 shows aforementioned adiaphorous state loop, meeting the TMS input of this adiaphorous state loop, all can not produce the action of any reality at the JTAG interface, therefore, the present invention be by by the definition at least two TMS input strings that meet this adiaphorous state loop, with respectively as the input of two kinds of data with different A and B, in present embodiment, A is a binary zero, B is a binary one, and as shown in the figure, the present invention is that preferably definition of T MS input string ' 0111 ' is input data B (=1), and definition TMS input string ' 1 ' subsequently is input data A (0).In addition, because the Run-Testdata/Idle state did not all change its state at 0 o'clock in input, therefore, also definable TMS input string
Be input data A or input data B, wherein
Represent at least one 0.
Please refer to the circuit diagram of aforementioned confidential data detecting device 35 shown in Figure 5 again, it comprises a state detector 51, one shift registor 52, the operation workflow figure of this state detector 51 as shown in Figure 6, it imports TCK, TMS and the JTAG state that produces by TAP controller 31, when being initial Test-Logic Reset state at the state of judging this TAP controller 31, begin to monitor the TMS input, and when having detected a TMS input string ' 0111 ', output (step S601) at its data output terminal 511 generations one data B (=1), afterwards, when having detected a TMS input string ' 1 ', output (step S602) at its data output terminal 511 generations one data A (=0), and this data output terminal 511 is when having output, and the data combination of being exported then deposits in this shift registor 52.Therefore, by by combination in the suitable word string of TMS pin position input, just can produce the data combination that will import at the data output terminal 511 of state detector 51, this data combination is to be temporary in this shift registor 52, thereby reaches the purpose of transmission hidden signal.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (18)
1, the device of transmission hidden signal in a kind of marginal sweep test interface, it is characterized in that, this sweep test interface, limit is to operate according to a predetermined state transfer figure, this state transfer figure carries out the state transfer according to an input, wherein, the state transfer of being carried out comprises at least one no active state loop, this device comprises: a state detector, in order to monitor this input, with when having detected one first default input string, produce the output of one first data, afterwards, when having detected one second default input string, the output that produces one second data, wherein, this first default input string and the second default input string are the different input strings that meet this adiaphorous state loop.
2, according to the device of transmission hidden signal in the described marginal sweep test of claim 1 interface, it is characterized in that it more comprises a shift registor, in order to store the combination of first and second data that this state detector exports.
3, according to the device of transmission hidden signal in the described marginal sweep test of claim 2 interface, it is characterized in that, should sweep test interface, limit be a JTAG interface wherein, and this is input as TMS input.
4, according to the device of transmission hidden signal in the described marginal sweep test of claim 2 interface, it is characterized in that, should sweep test interface, limit be an IEEE1149.1 interface wherein, and this is input as TMS input.
5, according to the device of transmission hidden signal in the described marginal sweep test of claim 2 interface, it is characterized in that, should sweep test interface, limit be the Digtial TestAccess Port interface of an IEEE1149.4 wherein, and this is input as TMS input.
6, according to the device that transmits hidden signal in the described marginal sweep test of claim 3 interface, it is characterized in that, wherein this state transfer figure is initiated at a Test-Logic Reset state, and being input as 1 o'clock state at TMS remains unchanged, when TMS is input as 0, the state transfer is the Run-Test/Idle state, and be input as at 0 o'clock at TMS, state remains unchanged, when continuous three TMS are input as 1, the state transfer is Test-Logic Reset state, and forms this at least one no active state loop.
According to the device of transmission hidden signal in the described marginal sweep test of claim 6 interface, it is characterized in that 7, wherein this first default input string is ' 0111 ', this second default input string is ' 1 '.
8, according to the device of transmission hidden signal in the described marginal sweep test of claim 7 interface, it is characterized in that wherein this first data is ' 1 ', this second data is ' 0 '.
According to the device of transmission hidden signal in the described marginal sweep test of claim 6 interface, it is characterized in that 9, wherein this first default input string is
This second default input string is ' 1 ', in the middle of
Represent at least one 0.
10, according to the device of transmission hidden signal in the described marginal sweep test of claim 9 interface, it is characterized in that wherein this first data is ' 1 ', this second data is ' 0 '.
11, the method for transmission hidden signal in a kind of marginal sweep test interface, it is characterized in that, this sweep test interface, limit is to operate according to a predetermined state transfer figure, this state transfer figure carries out the state transfer according to an input, wherein, the state transfer of being carried out comprises at least one no active state loop, and this method comprises:
(A) monitor this input, with when having detected one first default input string, the output that produces one first data, wherein, this first default input string is an input string that meets this adiaphorous state loop;
(B) monitor this input, when having detected one second default input string, the output that produces one second data, wherein, this second default input string is the input string that is different from this first default input string and meets this adiaphorous state loop.
According to the method for transmission hidden signal in the described marginal sweep test of claim 11 interface, it is characterized in that 12, it more comprises the combination of a step (C) with first and second data of storing this output.
13, according to the method for transmission hidden signal in the described marginal sweep test of claim 12 interface, it is characterized in that, should sweep test interface, limit be a JTAG interface wherein, and this is input as TMS input.
14, according to the method for transmission hidden signal in the described marginal sweep test of claim 12 interface, it is characterized in that, should sweep test interface, limit be an IEEE1149.1 interface wherein, and this is input as TMS input.
15, according to the method for transmission hidden signal in the described marginal sweep test of claim 12 interface, it is characterized in that, wherein should sweep test interface, limit be one to meet the Digtal TestAccess Port interface of IEEE1149.4, and this is input as TMS input.
16, according to the method for transmitting hidden signal in the described marginal sweep test of claim 13 interface, it is characterized in that, wherein this state transfer figure is initiated at a Test-Logic-Reset state, and being input as 1 o'clock state at TMS remains unchanged, when TMS is input as 0, the state transfer is the Run-Test/1dle state, and be input as at 0 o'clock at TMS, state remains unchanged, when continuous three TMS are input as 1, the state transfer is Test-Logic Reset state, and forms this at least one no active state loop.
17, transmission hidden signal method in the marginal sweep test according to claim 16 interface, it is characterized in that, wherein in step (A), this first default input string is ' 0111 ', this first data is ' 1 ', and in step (B), this second default input string is ' 1 ', and this second data is ' 0 '.
18, transmission hidden signal method in the marginal sweep test according to claim 16 interface is characterized in that, wherein in step (A), this first default input string is
This first data is ' 1 ', in the middle of
Represent at least one 0, and in step (B), this second default input string is ' 1 ', this second data is ' 0 '.
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| CNB2004100048280A CN100350260C (en) | 2004-02-09 | 2004-02-09 | Device and method for transmitting hidden signal in boundary scan test interface |
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| US5659508A (en) * | 1995-12-06 | 1997-08-19 | International Business Machine Corporation | Special mode enable transparent to normal mode operation |
| US5768196A (en) * | 1996-03-01 | 1998-06-16 | Cypress Semiconductor Corp. | Shift-register based row select circuit with redundancy for a FIFO memory |
| US5898704A (en) * | 1996-11-13 | 1999-04-27 | Fujitsu Limited | Processing system having testing mechanism |
| US6052808A (en) * | 1997-10-31 | 2000-04-18 | University Of Kentucky Research Foundation | Maintenance registers with Boundary Scan interface |
| US6073254A (en) * | 1996-08-30 | 2000-06-06 | Texas Instruments Incorporated | Selectively accessing test access ports in a multiple test access port environment |
| CN1305226A (en) * | 1999-09-03 | 2001-07-25 | 索尼公司 | Semiconductor circuit possessing scaning path circuit |
| US6378090B1 (en) * | 1998-04-24 | 2002-04-23 | Texas Instruments Incorporated | Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port |
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2004
- 2004-02-09 CN CNB2004100048280A patent/CN100350260C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659508A (en) * | 1995-12-06 | 1997-08-19 | International Business Machine Corporation | Special mode enable transparent to normal mode operation |
| US5768196A (en) * | 1996-03-01 | 1998-06-16 | Cypress Semiconductor Corp. | Shift-register based row select circuit with redundancy for a FIFO memory |
| US6073254A (en) * | 1996-08-30 | 2000-06-06 | Texas Instruments Incorporated | Selectively accessing test access ports in a multiple test access port environment |
| US5898704A (en) * | 1996-11-13 | 1999-04-27 | Fujitsu Limited | Processing system having testing mechanism |
| US6052808A (en) * | 1997-10-31 | 2000-04-18 | University Of Kentucky Research Foundation | Maintenance registers with Boundary Scan interface |
| US6378090B1 (en) * | 1998-04-24 | 2002-04-23 | Texas Instruments Incorporated | Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port |
| CN1305226A (en) * | 1999-09-03 | 2001-07-25 | 索尼公司 | Semiconductor circuit possessing scaning path circuit |
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