CN100347993C - Protocol interoperation characteristic test generating method based on communication multi-port finite state machine - Google Patents

Protocol interoperation characteristic test generating method based on communication multi-port finite state machine Download PDF

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CN100347993C
CN100347993C CNB2005100865197A CN200510086519A CN100347993C CN 100347993 C CN100347993 C CN 100347993C CN B2005100865197 A CNB2005100865197 A CN B2005100865197A CN 200510086519 A CN200510086519 A CN 200510086519A CN 100347993 C CN100347993 C CN 100347993C
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CN1741482A (en
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吴建平
王之梁
尹霞
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Tsinghua University
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Abstract

The present invention relates to a test generating method of protocol interoperability based on a communication multi-port finite state machine, which belongs to the technical field of network protocol test techniques. The present invention is characterized in that the method orderly comprises the following steps: a protocol system specification is described into a model of a communication multi-port finite state machine; an abstraction test set 1 is generated via an interoperability testing generating technique base on a single excitation principle; the error coverage degree of the test set 1 is computed; when necessary, an abstraction test set 2 with a higher error coverage degree is generated via an enhanced test generating method; a distributed test architecture is determines according to an actual test scenario; when the test set 2 is distributed on each test part, the observation controlling problem is solved via a method that coordination messages among the test parts are added in a test sequence, and an abstraction test set 3 is obtained; the abstraction test set 3 can be further converted into an actual test script. The present invention is suitable for various different distributed test architectures, and has certain universality.

Description

Protocol interoperation characteristic test generating method based on communication multi-port finite state machine
Technical field
The invention belongs to Internet technical field, relate in particular to the network protocol testing technical field.
Background technology
The protocol test technology be guarantee network communication protocol correct realize and the different network equipment between the important means of correct interconnection.Uniformity test is the basic protocol method of testing, and its target is whether the detection protocol realization is consistent with protocol specification.As replenishing of uniformity test, the main target of HIST be the two or more agreements of test be implemented in whether can be correct in the network operation environment mutual, thereby finish the function of stipulating in the consensus standard.HIST also is widely used in the process of design of protocol by IETF (the Internet engineering duty group) and ETSI International Standards Organization such as (ETSIs) in addition.
Generating based on the HIST of formalization method is major issue in this field, and its target is the formalized model from protocol specification, generates the test set (or cycle tests) that is used for test activity.In the HIST generation technique that great majority have proposed, its basic thought is with system under test (SUT) (System Under Test, be called for short SUT) be modeled as the system of a communication finite state machine, it is carried out the global state approachability analysis, and and then generate cycle tests.
Some problems below in the HIST generation technique that has proposed, existing: first, only considered the simple case of " one to one ", that is to say, tested realization (the ImplementationUnder Test that in system under test (SUT), only comprises two protocol entities, be called for short IUT), do not relate to for more general situations such as " one-to-manies ".The latter's a example is as follows: in mobile IPv 6 protocol, have different node: the communication node CN (Correspondent Node) of three classes, home agent HA (Home Agent) and mobile node MN (Mobile Node).In the mobile IP v 6 network, can regard a kind of more general interoperability alternately as between three category nodes.The second, test generates the covering that mainly is conceived to the interoperability of system behavior, and lacks the network analysis that mistake is covered, and the test set error coverage of generation is not high.The 3rd, the interoperability system under test (SUT) itself has distributed and characteristic concurrency, therefore in order not weaken the error detection capability of test macro, be necessary to adopt distributed test architecture to carry out HIST, but existing correlation technique does not consider to adopt the situation of distributed test architecture.
At above-mentioned deficiency, the present invention proposes a kind of based on the communication multi-port finite state machine protocol interoperation characteristic test generating method of (CommunicatingMulti-port Finite State Machine is called for short CMpFSM).This method has reflected the distributed nature of system under test (SUT) better by introduce multiport in model; In the process that test generates, adopt wrong covering analyzing technology, generate test set with higher wrong covering; At distributed test architecture, generate the distributed testing sequence.
Summary of the invention
The object of the present invention is to provide the universal method of testing generation under a kind of distributed test architecture based on the protocol interoperability of communication multi-port finite state machine.
The thinking of method proposed by the invention is: adopt a kind of general formalized model communication multi-port finite state machine to describe the standard of protocol system.At first adopt existing HIST generation technique spanning set Chinese style cycle tests based on approachability analysis; Then it is carried out wrong covering analyzing, if necessary, further adopt a kind of test generation method of enhancing to obtain the test set of higher error coverage; Select suitable distributed test architecture at last, and obtain final distributed testing collection by the distribution of centralized cycle tests.
The invention is characterized in:
Described method is in the network operation environment interoperability system under test (SUT) that is made of the different network equipments to be realized successively according to the following steps:
Step 1: in computer, the tested system specifications of interoperability is described as a communication multi-port finite state machine model M s:
If: in a described tested system of interoperability, comprise two or more protocol entities, and the standard of each protocol entity is known; Then: the tested system of described interoperability is described with a communication multi-port finite state machine, and this communication multi-port finite state machine is the set of m component states machine, represents Ms={M with Ms 1, M 2..., M m;
Each component states machine is used to describe the standard of each protocol entity, has defined the port mapping relation between each component states machine simultaneously, with the network topology of this described tested system of relationship description; Component states machine M iExpression, i=1,2 ..., m, M iBe a multi-port finite state machine that comprises n port, its port is numbered 1～n, M respectively iBe one eight tuple, M i=(S, I, O, δ, λ, s 0, Q, R):
● S is M iFinite state set, s 0∈ S is M iInitial condition;
● I=(I 1, I 2... I k..., I n), I wherein kBe the set of the incoming symbol on the port k, k=1,2 ..., n; A ∈ I kCan remember and make k:a; I=I 1∪ I 2∪ ... ∪ I k∪ ... ∪ I nBe M iThe set of all incoming symbols;
● O=(O 1, O 2..., O k..., O n), O wherein kBe the set of the output symbol on the port k, k=1,2 ..., n; B ∈ O kCan remember and make k:b; O=O 1∪ O 2∪ ... ∪ O k∪ ... ∪ O nBe M iThe set of all output symbols;
● δ is status change function: δ: S * I → S, wherein → and the expression mapping relations; λ is an output function: λ: S * I → O, wherein → the expression mapping relations; Article one, transition t can be expressed as (s 1, in/out, s 2) or S wherein 1, s 2∈ S, in ∈ I, out ∈ O and δ (s 1, in)=s 2, λ (s 1, in)=out; All transition set are designated as T;
● Q=(Q 1, Q 2... Q k..., Q n), Q wherein kBe the input rank of port k, k=1,2 ..., n; These formations all are the fifo fifo formations;
● R=(R 1, R 2..., R n) expression port mapping relation, wherein R kBe the port mapping relation of port k, k=1,2 ..., n, its form is 1) M j: h, wherein j ≠ i represents M iPort k be connected to M jPort h; Or 2) env, expression M iPort k link to each other with external environment condition; The port that will be connected with external environment condition is called " outside port ", is called " internal port " with the port of other component states machine communication; Be called the outside with inputing or outputing of external environment condition exchange and input or output, inputing or outputing of exchanging between the different component states machines is called inside and inputs or outputs;
Step 2: adopt HIST generation technique to generate abstract test suite 1, carry out according to the following steps successively based on single excitation principle:
For foregoing tested system specifications model M s, if each component states machine M iCurrent state be respectively s i, i=1,2 ..., m, then the global state of Ms can be expressed as vector (s 1, s 2..., s m), the initial global state of Ms then is (s 10, s 20..., s M0), s wherein I0Be M iInitial condition, i=1,2 ..., m; Corresponding with global state, the state of each component states machine is called local state; Stable global state refers to, and under these global states, if do not apply outside input from environment, then state can not change; In contrast, other state then is called temporary transient global state; The transition of stablizing between the global state are called overall transition, promptly under certain stable global state, apply an outside input, and overall transition are formed in the transition that each component states machine is experienced in the system chronologically; Corresponding, the transition in each component states machine are called local transition;
Step 2.1 adopts the method based on BFS, generates the leading test step of all test subjects and all stable global states, promptly by the cycle tests of initial global state to this global state:
If the formation of a global state is To_extend, a global state set is Extended, then
(1) initialization procedure: empty To_extend and Extended;
(2) with initial global state (s 10, s 20..., s N0) be pressed into formation To_extend from tail of the queue;
(3), then carry out (4)～(8) step if formation To_extend is not empty; If formation To_extend is empty, then stop;
(4) head of the queue from formation To_extend takes out a global state, and note is made gs;
(5) if gs belongs to set Extended, then forwarded for (3) step to;
(6) gs is joined among the set Extended;
(7) gs is set to the current global state of the Ms of system, for all possible outside input ein, carries out following steps:
(7.1) calculate Ms under global state gs, apply the overall transition that outside input ein forms, note is made gt; Calculate the new global state of Ms simultaneously, note is made new_gs;
(a) gt being set is ein, and incoming symbol in is set is ein;
(b) apply input on Ms, obtain output, note is made out, the additional out at the gt end; Upgrade the Ms global state simultaneously;
(c) obtain out place port, note is made P 1Follow according to the port mapping relation, obtain its mapped port P 2
(d) if P 2Be external environment condition env, then step (7.1) is finished, record gt, and the new global state new_gs of record Ms;
(e) otherwise in is set is out, forward (b) to;
(7.2) gt is noted as a test subject;
(7.3) if new_gs does not belong to set Extended, then
(a) ask for the leading test step of new_gs: the leading test step of new_gs is the leading test step affix gt of gs;
(b) the leading test step of record new_gs;
(c) new_gs is pressed into formation To_extend from tail of the queue;
(8) forwarded for (3) step to;
Step 2.2 is assembled into the HIST example with test subject and leading test step:
(1), carry out following steps for all test subjects:
(1.1) obtain the initial global state of this test subject, note is made gs;
(1.2) obtain the leading test step of gs;
(1.3) test subject is appended to after the leading test step of gs, promptly obtain a test case;
(2) all test cases are promptly formed abstract test suite 1;
Step 3: the test set 1 that step 2 is generated carries out the error coverage analysis, carries out according to the following steps successively:
Step 3.1 generation error model:
The possible errors of model has output error and transition mistake two classes; Certain component states machine M at described system specifications iTransition tr of middle selection changes the last current state or the output of these transition, obtains wrong transition ftr, at M iIn replace tr with ftr, can obtain a single error model, note is made Ms (M i.tr, M i.ftr);
Step 3.2 generates all single error models in the described tested system, and corresponding set is designated as Impl (Ms);
Step 3.3 abstract test suite 1 that Simulation execution obtains from step 2 on each model of described Impl (Ms), apply outside input, check whether output is identical with expection, if different, show that then the corresponding test case in the abstract test suite 1 can't pass through, test set 1 can detect model errors;
Step 3.4 adopts following formula to calculate the error coverage of described test set 1:
FC ( Ms , IOTS ) = Nt ( Ms ) - Np ( Ms , IOTS ) Nt ( Ms )
Wherein, Nt (Ms) is a wrong sum of realizing state machine among the described Impl (Ms); IOTS is given described test set 1; (Ms is the number that can realize by the mistake of described test set 1 among the Impl (Ms) IOTS) to Np, can be calculated by step 3.3;
Step 4:, then adopt the test generation method that strengthens to generate the higher abstract test suite 2 of coverage according to following steps successively if the error coverage that step 3 obtains does not reach set point:
For each transition error model, execution in step 4.1～step 4.2:
Step 4.1 is each test case of Simulation execution successively, if test case comprises the transition mistake but can't detect this mistake, then it is noted, as alternative;
Step 4.2 is selected a test case of length minimum in a plurality of test cases that step 4.1 is noted; If have only a test case, then select this test case to get final product; This test case is added last current state checking sequence, obtain a new test case, its steps in sequence is as follows:
Set: error model Ms (M i.tr, M i.ftr), its wrong component states machine M that is positioned at iIn; The test case of length minimum is tc k
(1) computing system standard Ms is executing test case tc kAfter overall last current state, note is made end_gs (Ms, tc k), thereby obtain M iLocal state, note is made local_state i(end_gs (Ms, tc k));
(2) at this moment only need checking M iLocal state whether be local_state i(end_gs (Ms, tc k)) get final product, adopt the method for following successor tree to ask for last current state checking sequence: the root node of successor tree is labeled as M under the initial situation iInstitute might a local state set, add each bar branch from this node, each branch is labeled as possible outside input respectively, but according to applying this possible observed behavior of outside input back system, set is divided to initial condition; Continue said process, up to being verified local state local_state i(end_gs (Ms, tc k)) be divided into singleton; The state verification sequence is from root node to the transition sequence that is verified on the plain collector node of the state cell path, if a plurality of transition sequences that satisfy condition are arranged, then select the shortest one of length, minimum one of the local transition number that promptly comprises, as the last current state checking sequence of being asked, note is made DS (end_gs (Ms, tc k), M i);
(3) by test case tc kThe new test case that expansion obtains then is tc kDS (end_gs (Ms, tc k), M i), promptly at tc kLast current state checking sequence D S (end_gs (Ms, tc are added in the back k), M i);
Step 4.3 substitutes former test case corresponding the test set 1 with all newly-generated test cases that obtains from step 4.1～step 4.2, obtains new abstract test suite 2;
Step 5: the test scene according to reality is determined distributed test architecture; Described distributed test architecture comprises:
Some test components and for some accessing points of tested system: each test component comprises one or more accessing points to system under test (SUT), and the effect of test component is to carry out the behavioral test relevant with its accessing points that comprises in the test case; Described accessing points comprises PCO PCO and point of observation PO two classes: PCO PCO is used to control and observe the external behavior on the tested realization IUT outside port, and point of observation PO does not then have controlled function, only is used to observe mutual between the IUT; Test component is divided into two classes: main test component MTC and from test component PTC, be used to control the accessing points that comprises wherein from test component, main test component then is used to create other four concurrent testing parts, and calculating the global decision of test case, all test components can carry out each other communication by a communication channel;
Step 6: test set 2 is distributed on each test component, finally generates the distributed synchronization cycle tests, obtain abstract test suite 3:
Each test case in the test set 2 can be expressed as the sequence of overall transition, establishes a test case tc k=Gt 1Gt 2... Gt L, Gt wherein i=Lt I_1Lt I_2... Lt I_li, i=1,2 ..., L, li are overall transition Gt iThe number of the local transition that comprised, Lt I_jRepresent each local transition, j=1,2 ..., li; Corresponding distributed test architecture comprises n test component TC 1, TC 2..., TC n, comprise some accessing points PCO or PO in each test component; If the distributed synchronization cycle tests is DTS (TC i), i=1,2 ..., n, expression is distributed to the cycle tests on each test component respectively; Then:
Step 6.1 is with each DTS (TC i) be initialized as empty sequence, i=1,2 ..., n;
Step 6.2 is carried out following steps successively for each the overall transition in the test case:
(1) pairing accessing points and place test component thereof are imported in the outside that obtains these overall situation transition, and note is made ePCO and TC respectively h
(2) if should overall situation transition be first overall transition in the test case, then: different if last of ePCO and last adjacent overall transition exported pairing accessing points, then
(a) last that obtains adjacent overall transition exported the test component at pairing accessing points place, and note is made TC k
(b) at DTS (TC k) a middle co-ordination message transmission incident, the note work of adding! CM (TC k→ TC h), expression is from test component TC kTo TC hSend a co-ordination message;
(c) at DTS (TC h) a middle co-ordination message reception incident, the note work of adding? CM (TC k→ TC h);
(3) obtain the pairing all-access point of output that causes by this overall situation transition, for each accessing points:
(a) obtain the test component TC at this accessing points place K '
(b) if TC K 'With TC hDifference is then at DTS (TC h) a middle co-ordination message transmission incident, the note work of adding! CM (TC h→ TC K '); At DTS (TC K ') a middle co-ordination message reception incident, the note work of adding? CM (TC h→ TC K ');
(4) at DTS (TC h) the middle outside incoming event that adds these overall situation transition;
(5), in the cycle tests of corresponding test component, add this outgoing event for each output action;
Step 6.3 is for each test case in the test set 2, and execution in step 6.1 and 6.2 obtains corresponding distributed synchronization test case, and all these test cases are formed test set 3;
Step 7: the resulting abstract test suite 3 of step 6 is converted to actual test script by automatic or manual mode, can actual execution on aforementioned distributed test architecture.
The versatility of test generation method proposed by the invention be embodied in following some: (1) protocol system adopts general formalized model communication multi-port finite state machine to describe, the simple case of " one to one " can be described, also more complicated situations such as " one-to-manies " can be described; (2) test generation method adopts and generates centralized cycle tests earlier, chooses distributed test architecture again, generates the strategy of distributed testing sequence, and this makes this method can adapt to various distributed test architecture.
Description of drawings
Fig. 1. the example of the interoperability system under test (SUT) that communication multi-port finite state machine is represented;
Fig. 2. be applied to the distributed test architecture of system under test (SUT) among Fig. 1;
Fig. 3. the protocol interoperability based on communication multi-port finite state machine is tested the overall framework that generates;
Fig. 4. the global state of Fig. 1 model and the example of overall transition;
Fig. 5. the example of a HIST example of Fig. 1 system under test (SUT);
Fig. 6. error model example: (a) M 2An output error; (b) M 1A transition mistake;
Fig. 7. last current state checking sequence is found the solution example;
Fig. 8. test case tc 7' the result that generates of distributed synchronization cycle tests:
(a) do not add the distributed testing sequence of co-ordination message;
(b) the distributed testing sequence after the interpolation co-ordination message.
Embodiment
Test generation method of the present invention has following steps successively:
(1) with the protocol system specification description is a communication multi-port finite state machine model M s;
(2) adopt existing HIST generation technique to generate abstract test suite 1 based on single excitation principle;
(3) test set 1 that generates is carried out the error coverage analysis, concrete steps are as follows:
(3-1) choose error model (fault model): the possible errors of model has output error and transition mistake two classes.Certain component states machine M at system specifications iTransition tr of middle selection changes the last current state or the output of these transition, obtains wrong transition ftr, at M iIn replace tr with ftr, can obtain a single error model, note is made Ms (M i.tr, M i.ftr)
(3-2) all single error models in the generation system, this set is designated as Impl (Ms);
(3-3) Simulation execution test set on each model of Impl (Ms) applies outside input, checks that whether output is identical with expection, if different, shows that then this test case can't pass through; If there is test case not pass through in the test set, show that then this test set can detect this mistake.
(3-4) adopt following formula to calculate the error coverage of test set:
FC ( Ms , IOTS ) = Nt ( Ms ) - Np ( Ms , IOTS ) Nt ( Ms )
Wherein, IOTS is given test set 1, and Ms is the protocol system standard; Nt (Ms) is a wrong sum of realizing state machine among the Impl (Ms), Np (Ms, IOTS) number (can be calculated by step 3-3) for realizing by the mistake of test set among the Impl (Ms).
(4) if error coverage not ideal enough (set point of error coverage is given by the user, as 100%) then adopts the test generation method that strengthens to generate the higher abstract test suite 2 of coverage, specific algorithm is seen " algorithm 1 ";
(5) select suitable distributed test architecture according to the test scene of reality, wherein comprise some test components (TestComponent) and for the accessing points of system under test (SUT);
(6) test set 2 is distributed on each test component, in this course, in cycle tests, adds the co-ordination message between the test component, to solve the controlled observation problem, the final distributed synchronization cycle tests that generates obtains abstract test suite 3, and specific algorithm is seen " algorithm 2 ";
(7) abstract test suite 3 is converted to actual test script by automatic or manual mode, so that actual execution on test macro.
Below, will relevant step be elaborated:
(1) formalized model:
In an interoperability system under test (SUT), comprise two or more protocol entities.For testing the interoperability of this system, the standard of supposing each protocol entity all is known, is referred to as the HIST based on standard (Specification-based).In order to describe system under test (SUT) exactly, the agreement behavior of each tested realization in (1) system should be described; (2) comprise the abstract topological structure of the network of each tested realization.The present invention adopts formalized model " communication multi-port finite state machine " to describe the interoperability system under test (SUT), this model is expressed as a multi-port finite state machine (Multi-port FSM) with each component states machine (Component machine), be used to describe the standard of each protocol entity, defined the port mapping relation between the component states machine simultaneously, with the network topology of this relationship description system under test (SUT).
[definition 1] communication multi-port finite state machine CMpFSM (Communicating Multi-port Finite StateMachines)
The set M={M that communication multi-port finite state machine is a m component states machine 1, M 2..., M m; Component states machine M i(i=0,1 ..., be a multi-port finite state machine (np-FSM) that comprises n port m), its port is numbered 1～n, M respectively iBe one eight tuple M i=(S, I, O, δ, λ, s 0, Q, R), wherein:
● S is M iFinite state set, s 0∈ S is M iInitial condition;
● I=(I 1, I 2... I k..., I n), I wherein k(k=1,2 ..., n) be the set of the incoming symbol on the port k, a ∈ I kCan remember and make k:a; I=I 1∪ I 2∪ ... ∪ I k∪ ... ∪ I nBe M iThe set of all incoming symbols;
● O=(O 1, O 2..., O k..., O n), O wherein k(k=1,2 ..., n) be the set of the output symbol on the port k, b ∈ O kCan remember and make k:b; O=O 1∪ O 2∪ ... ∪ O k∪ ... ∪ O nBe M iThe set of all output symbols;
● δ is status change function: δ: S * I → S (→ expression mapping relations); λ is an output function: λ: S * I → O (→ expression mapping relations); Article one, transition t can be expressed as (s 1, in/out, s 2) or S wherein 1, s 2∈ S, in ∈ I, out ∈ O and δ (s 1, in)=s 2, λ (s 1, in)=out; All transition set are designated as T;
● Q=(Q 1, Q 2... Q k..., Q n), Q wherein k(k=1,2 ..., n) being the input rank of port k, these formations all are the fifo fifo formations;
● R=(R 1, R 2..., R n) expression port mapping relation, wherein R k(k=1,2 ..., be the port mapping relation of port k n), its form is 1) M j: h (j ≠ i), expression M iPort k be connected to M iPort h; Or 2) env, expression M iPort k link to each other with external environment condition.
In above-mentioned definition, the port that will be connected with external environment condition is called " outside port ", is called " internal port " with the port of other component states machine communication; Be called outside input (going out) with the input (going out) of external environment condition exchange, the input (going out) that exchanges between the different component states machines is called inner input (going out).
Example: as shown in Figure 1, three component states machines in the system under test (SUT) are 2 port finite state machines (2p-FSM).M wherein 1Comprise two ports, be denoted as P in the drawings 11And P 12M 1Standard in comprise two state a and b, work as M 1When being positioned at a state, if from port P 11Receive an outside input i 2, transition then take place At P 11Export o on the port 1, M 1State become b.It is that (1) is to M that the port mapping of system is closed 1, R={R 1=env, R 2=M 3: 1}; (2) to M 2, R={R 1=env, R 2=M 3: 2}; (3) to M 3, R={R 1=M 1: 2, R 2=M 2: 2}.Adopt an example to explain the semantic as follows of port mapping relation: M 1Port P 12Be mapped as M 3Port P 31(promptly to M 1, R 2=M 3: 1), work as M like this 1At port P 12When producing an output u, u will become M 3Port P 31Input.The I/O assemble of symbol of model is as shown in the table:
The component states machine M 1 M 2 M 3
Port 1(P 11) 2(P 12) 1(P 21) 2(P 22) 1(P 31) 2(P 32)
Input i 1，i 2 z x 1，x 2 v U w
Output o 1，o 2 u y 1，y 2 w Z v
(2) distributed test architecture
In HIST, system under test (SUT) SUT comprises two or more tested realization IUT, has typical distribution formula characteristic.Therefore for carrying out HIST, it is very necessary adopting distributed test architecture.In the test activity of reality, can select different test configurations flexibly according to test scene.Fig. 2 is the distributed test architecture of resolution chart 1 system under test (SUT) " complete ".Wherein comprise two class accessing points: PCO PCO is used to control and observe the external behavior on the tested realization IUT outside port, and point of observation PO does not then have controlled function, only is used to observe mutual between the IUT.In distributed test architecture, also introduced the notion of test component (Test Component), each test component comprises one or more accessing points to system under test (SUT), and the effect of test component is to carry out the behavioral test relevant with its accessing points that comprises in the test case.In the example of Fig. 2, concurrent testing parts PTC1～4 are respectively applied for control accessing points PCO1, PCO2, PO1, PO2; Main test component MTC then is used to create other four concurrent testing parts, and calculates the global decision of test case.All test components can carry out each other communication by a communication channel.
(3) test generation method
Fig. 3 is based on the overall framework of the protocol interoperation characteristic test generating method of communication multi-port finite state machine.The starting point that test generates is the formalized model of system under test (SUT); In the phase I, at first adopt existing method generating test set 1, then this test set is carried out the error coverage analysis,, can adopt an additional enhancing test generation method to generate test set 2 with higher error coverage for the mistake that improves test set covers.For adapting to distributed test architecture, also the cycle tests that generates should be distributed on each test component.The cycle tests that comprises system under test (SUT) all of the port behavior description that generates in the phase I is called centralized cycle tests CTS, and the cycle tests that is distributed on each test component is called distributed testing sequence D TS.Similar with consistent property testing, the controlled observation problem may take place in the distributed testing sequence of HIST, solution is the co-ordination message of adding in cycle tests between the test component, finally obtains the distributed synchronization cycle tests.Therefore, in test generic frame shown in Figure 3, second stage will be selected suitable test configurations, i.e. distributed test architecture according to the test scene of reality; In the phase III, carry out the distribution of cycle tests, test set 2 is converted into final distributed synchronization test set 3.
Below will progressively explain in detail:
1. basic skills: based on the analysis method of reachability of single excitation principle
In the phase I that test generates, according to the protocol specification model of system under test (SUT), global state reachability graph that can generation system therefrom can further obtain centralized cycle tests.In existing HIST generation technique, for fear of famous state explosion problem, done two hypothesis: (1) slow environment (slow environment) supposes that promptly system works is in slow environment; (2) there is not livelock (livelock) in protocol specification and the realization.Based on above-mentioned hypothesis, two principles that test generates have been proposed: stable state principle and single excitation principle.
Said method is expanded on the communication multi-port finite state machine model: the model of establishing system under test (SUT) is M={M 1, M 2..., M m, M wherein i(i=0 ..., state m) is S iLike this, the global state of M can be expressed as vector (S 1, S 2..., S m).According to stable state and single excitation principle, in the global state reachability graph, only consider the global state that those are stable, promptly under these global states, if do not apply outside input from environment, then state can not change; In contrast, other state then is called transition condition.Test generation method based on single excitation principle only just can apply outside input when system under test (SUT) is in stable state.In the global state reachability graph, the transition between the stable global state are called overall transition, and are corresponding, and the transition in each component states machine are called local transition.
Fig. 4 is the global state of Fig. 1 model and the example of overall transition.(a, 1, C) and (a, 1, be to stablize global state D).When system mediates two temporary transient global states, all have in the input rank of a component states machine to have incoming symbol, even therefore do not apply outside input, system also can not remain under these two global states.Between these two overall stable states, three local transition (i1/u) are arranged, (u/z) and (z/o2).They have formed overall transition, and the note work (i1/u, u/z, z/o2).
The main purpose of HIST is that the formalized model according to system under test (SUT) finds the interbehavior between the tested protocol entity as much as possible, and check system under test (SUT) whether can correct execution they.A HIST collection is made up of several test cases, and each test case is all from the initial global state of system, the form of test case be (Preamble, Testbody, Postamble).Wherein, test subject (Test body) is the main purpose of test, the interbehavior between the promptly tested realization; Leading test step (Preamble) is used for system under test (SUT) is directed to the initial global state of test subject, and follow-up test step (Postamble) then is used for the initial global state of system that system under test (SUT) is led back to.Discuss for convenient, suppose that component states machines all in the system all has " function of reset " (reset capability), promptly have a kind of special input r, can make the state of state machine become initial condition.Have the test case of complete structure for these, they are separate each other, and promptly they can be carried out independently with any order.
Employing can generate all test subjects and leading test step based on the algorithm of depth-first search (DFS) or BFS (BFS), and then they can be assembled into test case.Fig. 5 is the example of a HIST example: test subject be overall transition (i1/u, u/v, v/w, w/z, z/o2).From the initial global state of system (a, 1, C) set out, test case use leading test step (i1/u, u/z, z/o2) (x1/y1) with system under test (SUT) be directed to global state (a, 2, D), carry out test subject then.
In HIST, basic testing requirement is the interbehavior between the different agreement entity.Therefore we to stipulate to test selection strategy as follows: the test case that only comprises a plurality of protocol entity behaviors just is selected into test set, example as shown in Figure 5.If only comprise certain protocol entity factum in the test case, then it abandoned.
[definition 2] HIST example (sequence)
A HIST example (sequence) is defined as IoTC (M)=Gt 1Gt 2... Gt L, wherein, a) L is the sum of overall transition; B) Gt i=Lt I_1Lt I_2... Lt I_li(i=1,2 ..., L), wherein, l iBe overall transition Gt iIn the sum of local transition.
For simplicity, a HIST example also can be expressed as an outside list entries, i.e. the overall transition of each in the test case are represented with its outside input.Test case shown in Figure 5 can be simplified shown as tc=i 1x 1i 1
2. error coverage analysis
One of purpose of HIST is the mistake that detects in the agreement realization, and it is very necessary therefore the error coverage of HIST collection being analyzed and estimated.Here be defined as follows two class error models (fault model): (1) output error: the output of transition makes a mistake in certain component states machine, the output of mistake might be other output on the same port, also might be the output on other port.Fig. 6 (a) is M 2An output error example.Mistake output y 1With correct output w not on same port.(2) transition mistake: the last current state of transition makes a mistake in certain component states machine, supposes that this mistake can not increase the status number of this component states machine, and promptly Cuo Wu last current state only may be other existing state, and can not be a new state of introducing.Fig. 6 (b) is M 1A transition error example.
If the protocol specification model of system under test (SUT) is Ms, given one group of possible system realizes finite aggregate Impl (Ms), and supposing does not have with the corresponding to realization of protocol specification Ms in this set, i.e. realization in this set is " mistake realization ".A given HIST collection IOTS, calculating its basic thought to the error coverage of Impl (Ms) is: establish Nt (Ms) for realizing the sum of state machine among the Impl (Ms), Np (Ms, IOTS) be the number that can pass through the realization of test set among the Impl (Ms), then test set IOTS for the error coverage of realizing set Impl (Ms) is
FC ( Ms , IOTS ) = Nt ( Ms ) - Np ( Ms , IOTS ) Nt ( Ms )
It is the sum can detected error realized of test set and the ratio of wrong realization sum.Be the mistake in computation coverage, the selected of set Impl (Ms) is a key issue, and ideal situation is to enumerate all possible fully and the realization of the inconsistent system of system specifications, but this way obviously is unpractical.The present invention only considers single error model, promptly in system under test (SUT), has only to comprise a mistake in the component states machine, and other component states machine all is correct.Why do such qualification, be because we think: the mistake that comprises in the system is many more, easy more being detected (promptly causing test case to pass through).Single mistake is detected least easily, and it is carried out wrong covering analyzing important directive significance.Single error model can adopt following method to generate: at certain component states machine M of system specifications iTransition tr of middle selection changes the last current state or the output of these transition, obtains wrong transition ftr, at M iIn replace tr with ftr, can obtain a single error model, note is made Ms (M i.tr, M i.ftr); The set of all single error models of system is Impl (Ms).Can adopt the method mistake in computation coverage of " emulation testing " (Simulation Testing), promptly Simulation execution test set on each model of Impl (Ms) applies outside input, checks whether output is identical with expection, if different, show that then this test case can't pass through; If there is test case not pass through in the test set, show that then this test set can detect this mistake.
3. the test generation method of Zeng Qianging:
The HIST collection that is obtained by basic test generation method might can't reach 100% mistake covering.On the one hand, because based on the limitation of the method for single excitation principle itself, the HIST collection might can't cover some transition, so test set can't detect the error model that is obtained by these transition of modification, for this type of situation, the present invention will not discuss; On the other hand, for the transition that some test set covers, the transition mistake that is obtained by these transition of modification still can't be detected, and the reason that this thing happens then is because test case lacks last current state checking sequence.For improving the error coverage of HIST collection, should select some test cases to add last current state checking sequence for it.According to above thinking, algorithm 1 has provided a kind of test generating algorithm of enhancing.
The test generating algorithm that [algorithm 1] strengthens
INPUT (1) system specifications model M s={M i; (2) former test set old_TS={tc k(k=1,2 ..., n, n are the test case number);
OUTPUT adds the new test set new_TS after the last current state checking sequence;
BEGIN
(1) each transition error model Ms (M of for Ms i.tr, M i.ftr) do
(2) each test case tc among for old_ts kDo
(3) detected_flag:=false; Whether // this mistake can detect by tested collection
(4) with tc kAt Ms (M i.tr, M i.ftr) go up execution;
(5) the if execution result is PASS then
(6) iftc kComprise transition M i.tr and tc kCarry out the overall situation last current state mistake then of back system
(7) write down the sequence number of this test case; //tc kComprise the mistake transition, and can't detect mistake
(8)else
(9) detected_flag:=true; //tc kCan detect wrong M i.ftr
(10) break; // need not to add last current state to verify sequence
(11) if (! Detected_flag) and have test case to be recorded then
(12) from the test case that is recorded, select one;
(13) for this test case adds last current state checking sequence, obtain a new test case;
(14) with the former test case of alternative its correspondence of all newly-generated test cases, obtain new test set new_TS;
END.
In above-mentioned algorithm, for each transition error model, each test case of Simulation execution if test case comprises the transition mistake but can't detect this mistake, is then noted it, as alternative successively.For detecting the transition mistake not come out, write down a plurality of test cases in the test set inspection if take turns one, then only need in these test cases, to select one to add last current state checking sequence and get final product.Selecting the method for test case can be to select at random, and better method then is of selection length minimum.
Be the state explosion problem of avoiding overall situation combination to cause, when adding last current state checking sequence, do not need to verify overall last current state, and only need verify local last current state.The basic thought that adds last current state checking sequence is as follows: establish (the M for error model Ms i.tr, M i.ftr), needing the test case of interpolation last current state checking sequence is tc kAt first computing system standard Ms is executing test case tc kAfter overall last current state, note is made end_gs (Ms, tc k), M iLocal state be local_state i(end_gs (Ms, tc k)); At error model Ms (M i.tr, M i.ftr) in, mistake is positioned at component states machine M iIn, can suppose M j(all correct (=local_state of the local state of j ≠ i) j(end_gs (Ms, tc k))), last current state checking sequence only need be verified M iLocal state whether correct, note is made DS (end_gs (Ms, tc k), M i); Like this, by test case tc kThe new test case that expansion obtains then is tc kDS (end_gs (Ms, tc k), M i).
Find the solution last current state and verify that sequence can adopt the method based on successor tree (Successor Tree), Fig. 7 has provided one and has found the solution example.Its system model is Fig. 1 model, supposes M 2, M 3Local state be respectively 1 and C, checking M 1Local state whether be a.Global state (*, 1, C) expression here.The root node of successor tree is labeled as M under the initial situation 1Possible state set a, b} is from this node, each branch is labeled as possible outside input respectively (because in HIST, it is controlled having only outside input), but according to applying this possible observed behavior of outside input back system, set is divided to initial condition; Continue said process, be divided into singleton up to the state of being verified; The state verification sequence is from root node to the transition sequence that is verified on the plain collector node of the state cell path.As shown, under initial situation, apply outside input i 1If, M 1State is a, and then Dui Ying overall transition are { i 1/ u, u/z, z/o 2; If M 1State is b, and then Dui Ying overall transition are { i 1/ o 1.But both observed behaviors are different, therefore outside input i 1Can be with M 1The set of possible initial condition be divided into two singleton { a}{b}.This shows by applying i 1Can realize M 1The checking of local state.For finding the shortest last current state of length checking sequence, also this layer all can have been expanded, as shown in the figure, optimum last current state verify sequence be DS ((a, 1, C), M 1)={ i 2/ o 1.
4. the distribution of cycle tests:
Behind the spanning set Chinese style cycle tests, next step then is to select a suitable distributed test architecture according to the test scene of reality, generates the distributed testing sequence in view of the above.Its basic thought is each test event in the given centralized cycle tests to be distributed to each test component according to its corresponding accessing points get on.This process is referred to as the distribution of cycle tests.
Yet, in HIST, when adopting distributed test architecture to carry out the distributed testing sequence that obtains, control and observation problem might take place.Before these two problems of discussion, provide several functions earlier and be defined as follows:
[definition 3] several function definitions
(1) Input (Lt) returns the input of local transition Lt; Input (Gt) returns the outside input of overall transition Gt;
(2) Output (Lt) returns the output of local transition Lt;
(3) Port (s) returns the pairing accessing points of input s.
Say that intuitively control problem refers to test component can't determine when that applying the outside on its PCO imports.In order to satisfy slow environmental postulates, have only when system under test (SUT) is in stable state and could apply outside input it.Therefore test component must guarantee this point when applying an outside input.
The condition that control problem takes place: a given HIST sequence IoTS=Gt 1Gt 2... Gt LFor two adjacent overall transition Gt iAnd Gt I+1(i=1,2 ..., L-1): as Port (Input (Gt I+1)) ≠ Port (Output (Lt I_li)) time, apply Gt to system under test (SUT) I+1Outside when input control problem takes place.
Promptly for two adjacent overall transition, if the outside of second overall transition import pairing PCO and first overall transition last export pairing accessing points not simultaneously, test component can't determine when the outside input that applies second overall transition to system under test (SUT).For solving control problem, should be from receiving the test component TC of first overall last output of transition iTo the test component TC that applies second outside input of overall transition jSend a co-ordination message, note is made CM (TC i→ TC j).The purpose of this co-ordination message is notice test component TC jCan apply the outside has imported.
Say that intuitively observation problem refers to test component and can not determine when begin to observe (reception) IO action on its PCO (or PO).Observation problem will cause detecting output placement error (output-shift fault).
The condition that observation problem takes place: a given HIST sequence IoTS=Gt 1Gt 2... Gt LFor overall transition Gt i: as Port (Input (Gt i)) ≠ Port (Output (Lt I_j)) (j=1,2 ..., in the time of li), when observing these outputs, observation problem will take place.
Promptly import pairing PCO when inequality when the outside of the pairing PCO of the output of certain overall transition (or PO) and these overall situation transition, relevant test component will not known from when beginning to observe the output of these overall situation transition.For solving observation problem, should before applying outside input, send co-ordination message to the test component that all receive output from the test component that applies outside input.The purpose of this co-ordination message is to notify each test component to begin to observe output, and this has just set up causality between excitation and response.
Based on the above discussion as can be known, cause the basic reason of controlled observation problem to be that the introducing of a plurality of discrete testers (test component) has weakened the control and the observation ability of test macro.Therefore in order not weaken the error detection capability of test macro, should between test component, add co-ordination message.The algorithm that cycle tests distributes is as follows:
[algorithm 2] distributed synchronization cycle tests generating algorithm
INPUT:1. given centralized cycle tests: IoTS=Gt 1Gt 2... Gt L, Gt wherein i=Lt I_1Lt I_2... Lt I_li(i=1,2 ..., L);
2. test configurations: n test component TC 1, TC 2..., TC n, and the PCO that comprises (or PO).
OUTPUT: distributed synchronization cycle tests DTS (TC i) (i=1,2 ..., n).
BEGIN
(1)for?i?from?1?to?n?do
(2) DTS (TC i) ← Φ; // initialization
(3)for?i?from?1?to?L?do
(4)e_input_PCO←Port(Input(Gt i))；
(5) obtain the test component TC at e_input_PCO place h
(6) first transition of if (i＞1) then//do not need to consider
(7) if (e_input_PCO ≠ Port (Output (Lt (i-1) _ l (i-1)))) then//generation control problem
(8) obtain Port (Output (Lt (i-1) _ l (i-1))) the test component TC at place k
(9)DTS(TC k)←DTS(TC k)·！CM(TC k→TC h)；
(10)DTS(TC h)←DTS(TC h)·？CM(TC k→TC h)；
(11)output_PCO_set←Φ；
(12)for?j?from?1?to?l i?do
(13)output_PCO_set←output_PCO_set∪Port(Output(Lt i_j))；
(14)for?each?PCO k’in?output_PCO_set?do
(15) obtain PCO kThe test component TC at place k
(16) if (e_input_PCO ≠ PCO K ') then//generation observation problem
(17)DTS(TC h)←DTS(TC h)·！CM(TC h→TC k)；
(18)DTS(TC k)←DTS(TC k)·？CM(TC h→TC k)；
(19) DTS (TC h) ← DTS (TC h) Input (Gt i); // add the outside to import
(20) forj from 1 to l iAll outputs of do//interpolation
(21) if (Port (Output (Lt I_j)) in test configurations, be defined) then
(22) obtain Port (Output (Lt I_j)) the test component TC at place k
(23)DTS(TC k)←DTS(TC k)·Output(Lt i_j)；
Annotate: "! " expression " transmission " co-ordination message, "? " expression " receiving " co-ordination message.
(4) experimental result
With the system under test (SUT) model of describing among Fig. 1 is example explanation said method, at first adopt basic analysis method of reachability spanning set Chinese style test set, and the error coverage of calculating generating test set, its statistics (" replacement " incident that does not comprise system in the statistics) as shown in the table:
Method The test case number Overall situation transition number (N gt) Local transition number (N lt) The test event number Error coverage
(N tc) (N te＝N gt+N lt) (1-fault)
Based on BFS 24 64 162 226 87.5％
Based on DFS 26 76 198 274 93.8％
Two kinds of methods have obtained the HIST example of different numbers: less based on the test set scale that the method for BFS obtains, however with regard to error coverage, DFS method (93.8%) is better than BFS method (87.5%).
In the test set that the test method of generationing (algorithm 1) that strengthens is applied to obtain based on the DFS method (selecting to add the checking sequence at random), the new test set that obtains contrasts with former test set and adds up as shown in the table:
Test set Test case number (N tc) Overall situation transition number (N gt) Local transition number (N lt) Test event number (N te＝N gt+N lt) Error coverage (1-fault) Error coverage (2-faults)
Former test set 26 76 198 274 93.8％ 99.8％
New test set 26 78 200 278 100％ 100％
Example: through the error coverage analysis as can be known, former test set can not detect the transition mistake shown in Fig. 6 (b).Be M 1Transition (b, i 1/ o 1, a) the transition mistake takes place, last current state becomes b.Use algorithm 1, in former test set, have 3 test cases to cover this transition, therefrom select one to add last current state checking sequence: tc at random 7=x 1i 2x 1i 1The solution procedure of the last current state checking sequence of this test case as shown in Figure 7.Therefore the new test case that finally obtains is tc 7'=x 1i 2x 1i 1i 2As above shown in the table, new test set is compared with former test set, has only increased by 4 test events, and error coverage then brings up to 100%.Last table has also compared the single error coverage and the 2-error coverage of two test sets, and therefrom the 2-error coverage of each test set always is not less than the single error coverage of this test set as can be seen.
Adopt " complete " distributed test architecture shown in Figure 2, use algorithm 2 above-mentioned test set further is converted into the distributed synchronization test set.The statistics of test event number is as shown in the table: concentrate 186 incidents relevant with co-ordination message of having added altogether at distributed testing.
Test set The test case number Total test event number The co-ordination message event number
Centralized 26 278 0
Distributed 26 464 186
Example: with test case tc 7'=x 1i 2x 1i 1i 2For the distribution of example explanation cycle tests, use algorithm 2, the distributed synchronization test case that obtains is as follows, and Fig. 8 is its diagrammatic representation.10 incidents relevant have been added in the test case of Fig. 8 (b) with co-ordination message.
DTS(PTC1)＝{？CM(PTC2→PTC1)， PCO1！i 2，
PCO1？o 1，！CM(PTC1→PTC2)，？CM(PTC2→PTC1)，PCO1！i 1，PCO1？o 1，PCO1！i 2，
PCO1？o 1}.
DTS(PTC2)＝{PCO2！x 1，PCO2？y 1，！CM(PTC2→PTC1)，？CM(PTC1→PTC2)，！CM(PTC2→PTC3)，！CM(PTC2→PTC4)，PCO2！x 1，PCO2？y 1，！CM(PTC2→PTC1)}.
DTS(PTC3)＝{？CM(PTC2→PTC3)，PO1？z，PO1？u，PO1？z，PO1？u}.
DTS(PTC4)＝{？CM(PTC2→PTC4)，PO2？w，PO2？v?}.
Annotate: "? " expression receives from accessing points; "! " represent to send from accessing points.
This shows that the present invention has reached intended purposes.

Claims (1)

  1. Based on the protocol interoperation characteristic test generating method of communication multi-port finite state machine, it is characterized in that 1, described method is in the network operation environment interoperability system under test (SUT) that is made of the different network equipments to be realized successively according to the following steps:
    Step 1: in computer, the tested system specifications of interoperability is described as a communication multi-port finite state machine model M s:
    If: in a described tested system of interoperability, comprise two or more protocol entities, and the standard of each protocol entity is known; Then: the tested system of described interoperability is described with a communication multi-port finite state machine, and this communication multi-port finite state machine is the set of m component states machine, represents Ms={M with Ms 1, M 2..., M m;
    Each component states machine is used to describe the standard of each protocol entity, has defined the port mapping relation between each component states machine simultaneously, with the network topology of this described tested system of relationship description; Component states machine M iExpression, i=1,2 ..., m, M iBe a multi-port finite state machine that comprises n port, its port is numbered 1～n, M respectively iBe one eight tuple, M i=(S, I, O, δ, λ, s 0, Q, R):
    ● S is M iFinite state set, s 0∈ S is M iInitial condition;
    ● I=(I 1, I 2... I k..., I n), I wherein kBe the set of the incoming symbol on the port k, k=1,2 ..., n; A ∈ I kCan remember and make k:a; I=I 1∪ I 2∪ ... ∪ I k∪ ... ∪ I nBe M iThe set of all incoming symbols;
    ● O=(O 1, O 2..., O k..., O n), O wherein kBe the set of the output symbol on the port k, k=1,2 ..., n; B ∈ O kCan remember and make k:b; O=O 1∪ O 2∪ ... ∪ O k∪ ... ∪ O nBe M iThe set of all output symbols;
    ● δ is status change function: δ: S * I → S, wherein → and the expression mapping relations; λ is an output function: λ: S * I → O,
    Wherein → the expression mapping relations; Article one, transition t can be expressed as (s 1, in/out, s 2) or s 1 → in / out s 2 , S wherein 1, s 2∈ S, in ∈ I, out ∈ O and δ (s 1, in)=s 2, λ (s 1, in)=out; All transition set are designated as T;
    ● Q=(Q 1, Q 2... Q k..., Q n), Q wherein kBe the input rank of port k, k=1,2 ..., n; These formations all are the fifo fifo formations;
    ● R=(R 1, R 2..., R n) expression port mapping relation, wherein R kBe the port mapping relation of port k, k=1,2 ..., n, its form is 1) M j: h, wherein j ≠ i represents M iPort k be connected to M iPort h; Or 2) env, expression M iPort k link to each other with external environment condition; The port that will be connected with external environment condition is called " outside port ", is called " internal port " with the port of other component states machine communication; Be called the outside with inputing or outputing of external environment condition exchange and input or output, inputing or outputing of exchanging between the different component states machines is called inside and inputs or outputs;
    Step 2: adopt HIST generation technique to generate abstract test suite 1, carry out according to the following steps successively based on single excitation principle:
    For foregoing tested system specifications model M s, if each component states machine M iCurrent state be respectively s i, i=1,2 ..., m, then the global state of Ms can be expressed as vector (s 1, s 2..., s m), the initial global state of Ms then is (s 10, s 20..., s M0), s wherein I0Be M iInitial condition, i=1,2 ..., m; Corresponding with global state, the state of each component states machine is called local state; Stable global state refers to, and under these global states, if do not apply outside input from environment, then state can not change; In contrast, other state then is called temporary transient global state; The transition of stablizing between the global state are called overall transition, promptly under certain stable global state, apply an outside input, and overall transition are formed in the transition that each component states machine is experienced in the system chronologically; Corresponding, the transition in each component states machine are called local transition;
    Step 2.1 adopts the method based on BFS, generates the leading test step of all test subjects and all stable global states, promptly by the cycle tests of initial global state to this global state:
    If the formation of a global state is To_extend, a global state set is Extended, then
    (1) initialization procedure: empty To_extend and Extended;
    (2) with initial global state (s 10, s 20..., s N0) be pressed into formation To_extend from tail of the queue;
    (3), then carry out (4)～(8) step if formation To_extend is not empty; If formation To_extend is empty, then stop;
    (4) head of the queue from formation To_extend takes out a global state, and note is made gs;
    (5) if gs belongs to set Extended, then forwarded for (3) step to;
    (6) gs is joined among the set Extended;
    (7) gs is set to the current global state of the Ms of system, for all possible outside input ein, carries out following steps:
    (7.1) calculate Ms under global state gs, apply the overall transition that outside input ein forms, note is made gt; Calculate the new global state of Ms simultaneously, note is made new_gs;
    (a) gt being set is ein, and incoming symbol in is set is ein;
    (b) apply input on Ms, obtain output, note is made out, the additional out at the gt end; Upgrade the Ms global state simultaneously;
    (c) obtain out place port, note is made P 1Follow according to the port mapping relation, obtain its mapped port P 2
    (d) if P 2Be external environment condition env, then step (7.1) is finished, record gt, and the new global state new_gs of record Ms;
    (e) otherwise in is set is out, forward (b) to;
    (7.2) gt is noted as a test subject;
    (7.3) if new_gs does not belong to set Extended, then
    (a) ask for the leading test step of new_gs: the leading test step of new_gs is the leading test step affix gt of gs;
    (b) the leading test step of record new_gs;
    (c) new_gs is pressed into formation To_extend from tail of the queue;
    (8) forwarded for (3) step to;
    Step 2.2 is assembled into the HIST example with test subject and leading test step:
    (1), carry out following steps for all test subjects:
    (1.1) obtain the initial global state of this test subject, note is made gs;
    (1.2) obtain the leading test step of gs;
    (1.3) test subject is appended to after the leading test step of gs, promptly obtain a test case;
    (2) all test cases are promptly formed abstract test suite 1;
    Step 3: the test set 1 that step 2 is generated carries out the error coverage analysis, carries out according to the following steps successively:
    Step 3.1 generation error model:
    The possible errors of model has output error and transition mistake two classes; Certain component states machine M at described system specifications iTransition tr of middle selection changes the last current state or the output of these transition, obtains wrong transition ftr, at M iIn replace tr with ftr, can obtain a single error model, note is made Ms (M iTr, M iFtr);
    Step 3.2 generates all single error models in the described tested system, and corresponding set is designated as Impl (Ms);
    Step 3.3 abstract test suite 1 that Simulation execution obtains from step 2 on each model of described Impl (Ms), apply outside input, check whether output is identical with expection, if different, show that then the corresponding test case in the abstract test suite 1 can't pass through, test set 1 can detect model errors;
    Step 3.4 adopts following formula to calculate the error coverage of described test set 1:
    FC ( Ms , IOTS ) = Nt ( Ms ) - Np ( Ms , IOTS ) Nt ( Ms )
    Wherein, Nt (Ms) is a wrong sum of realizing state machine among the described Impl (Ms); IOTS is given described test set 1; (Ms is the number that can realize by the mistake of described test set 1 among the Impl (Ms) IOTS) to Np, can be calculated by step 3.3;
    Step 4:, then adopt the test generation method that strengthens to generate the higher abstract test suite 2 of coverage according to following steps successively if the error coverage that step 3 obtains does not reach set point:
    For each transition error model, execution in step 4.1～step 4.2:
    Step 4.1 is each test case of Simulation execution successively, if test case comprises the transition mistake but can't detect this mistake, then it is noted, as alternative;
    Step 4.2 is selected a test case of length minimum in a plurality of test cases that step 4.1 is noted; If have only a test case, then select this test case to get final product; This test case is added last current state checking sequence, obtain a new test case, its steps in sequence is as follows:
    Set: error model Ms (M iTr, M iFtr), its mistake is positioned at component states machine M iIn; The test case of length minimum is tc k
    (1) computing system standard Ms is executing test case tc kAfter overall last current state, note is made end_gs (Ms, tc k), thereby obtain M iLocal state, note is made local_state i(end_gs (Ms, tc k));
    (2) at this moment only need checking M iLocal state whether be local_state i(end_gs (Ms, tc k)) get final product, adopt the method for following successor tree to ask for last current state checking sequence: the root node of successor tree is labeled as M under the initial situation iInstitute might a local state set, add each bar branch from this node, each branch is labeled as possible outside input respectively, but according to applying this possible observed behavior of outside input back system, set is divided to initial condition; Continue said process, up to being verified local state local_state i(end_gs (Ms, tc k)) be divided into singleton; The state verification sequence is from root node to the transition sequence that is verified on the plain collector node of the state cell path, if a plurality of transition sequences that satisfy condition are arranged, then select the shortest one of length, minimum one of the local transition number that promptly comprises, as the last current state checking sequence of being asked, note is made DS (end_gs (Ms, tc k), M i);
    (3) by test case tc kThe new test case that expansion obtains then is tc kDS (end_gs (Ms, tc k), M i), promptly at tc kLast current state checking sequence D S (end_gs (Ms, tc are added in the back k), M i);
    Step 4.3 substitutes former test case corresponding the test set 1 with all newly-generated test cases that obtains from step 4.1～step 4.2, obtains new abstract test suite 2;
    Step 5: the test scene according to reality is determined distributed test architecture; Described distributed test architecture comprises:
    Some test components and for some accessing points of tested system: each test component comprises one or more accessing points to system under test (SUT), and the effect of test component is to carry out the behavioral test relevant with its accessing points that comprises in the test case; Described accessing points comprises PCO PCO and point of observation PO two classes: PCO PCO is used to control and observe the external behavior on the tested realization IUT outside port, and point of observation PO does not then have controlled function, only is used to observe mutual between the IUT; Test component is divided into two classes: main test component MTC and from test component PTC, be used to control the accessing points that comprises wherein from test component, main test component then is used to create other four concurrent testing parts, and calculating the global decision of test case, all test components can carry out each other communication by a communication channel;
    Step 6: test set 2 is distributed on each test component, finally generates the distributed synchronization cycle tests, obtain abstract test suite 3:
    Each test case in the test set 2 can be expressed as the sequence of overall transition, establishes a test case tc k=Gt 1Gt 2Gt L, Gt wherein i=Lt I_1Lt I_2Lt I_li, i=1,2 ..., L, li are overall transition Gt iThe number of the local transition that comprised, Lt I_jRepresent each local transition, j=1,2 ..., li; Corresponding distributed test architecture comprises n test component TC 1, TC 2..., TC n, comprise some accessing points PCO or PO in each test component; If the distributed synchronization cycle tests is DTS (TC i), i=1,2 ..., n, expression is distributed to the cycle tests on each test component respectively; Then:
    Step 6.1 is with each DTS (TC i) be initialized as empty sequence, i=1,2 ..., n;
    Step 6.2 is carried out following steps successively for each the overall transition in the test case:
    (1) pairing accessing points and place test component thereof are imported in the outside that obtains these overall situation transition, and note is made ePCO and TC respectively h
    (2) if should overall situation transition be first overall transition in the test case, then: different if last of ePCO and last adjacent overall transition exported pairing accessing points, then
    (a) last that obtains adjacent overall transition exported the test component at pairing accessing points place, and note is made TC k
    (b) at DTS (TC k) a middle co-ordination message transmission incident, the note work of adding! CM (TC k→ TC h), expression is from test component TC kTo TC hSend a co-ordination message;
    (c) at DTS (TC h) a middle co-ordination message reception incident, the note work of adding? CM (TC k→ TC h);
    (3) obtain the pairing all-access point of output that causes by this overall situation transition, for each accessing points:
    (a) obtain the test component TC at this accessing points place K '
    (b) if TC K 'With TC hDifference is then at DTS (TC h) a middle co-ordination message transmission incident, the note work of adding! CM (TC h→ TC K '); At DTS (TC K ') a middle co-ordination message reception incident, the note work of adding? CM (TC h→ TC K ');
    (4) at DTS (TC h) the middle outside incoming event that adds these overall situation transition;
    (5), in the cycle tests of corresponding test component, add this outgoing event for each output action;
    Step 6.3 is for each test case in the test set 2, and execution in step 6.1 and 6.2 obtains corresponding distributed synchronization test case, and all these test cases are formed test set 3;
    Step 7: the resulting abstract test suite 3 of step 6 is converted to actual test script by automatic or manual mode, can actual execution on aforementioned distributed test architecture.
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