CN100344125C - A solution method of data transmission deadlock - Google Patents
A solution method of data transmission deadlock Download PDFInfo
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- CN100344125C CN100344125C CNB2003101154776A CN200310115477A CN100344125C CN 100344125 C CN100344125 C CN 100344125C CN B2003101154776 A CNB2003101154776 A CN B2003101154776A CN 200310115477 A CN200310115477 A CN 200310115477A CN 100344125 C CN100344125 C CN 100344125C
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000012360 testing method Methods 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims description 12
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000012546 transfer Methods 0.000 description 6
- 230000009849 deactivation Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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Abstract
The present invention provides a method for solving data transmission deadlock, which is characterized in that a timer is arranged at a data transmission interface. The method comprises the steps as follows: a. launching the timer for timing when the data transmission interface generates a timer starting signal; b. testing whether the timing of the timer reaches the length of set time or not, if true, then the timer is reset, an interface reset signal is sent to the data transmission interface for resetting the data transmission interface, and the processing is finished, else, execute step c; c. using the data transmission interface to test whether the current data transmission is finished, if true, then a timer reset signal is generated for resetting the timer, and the processing is finished; else, return to step b. The present invention can be used for solving the problem of the deadlock which occurs in the data transmission of the data transmission interface.
Description
Technical field
The present invention relates to data transmission technology, be meant a kind of solution of deadlock especially.
Background technology
Universal Test ﹠ Operations PHY Interface for ATM (UTOPIA) has defined physical layer (PHY) and upper layer module, comprises the interface between ATM layer and the various management entity.This UTOPIA interface makes various types of physical layers can support public ATM layer.
The sequential chart that Fig. 1 sends for the UTOPIA interface data, in this sequential chart, the UTOPIA interface adopts cell level transmission control.As shown in Figure 1, TxClk is the synchronised clock of ATM layer and the work of PHY layer; TxClav is the cell flow control signal from the PHY layer, is used to refer to PHY layer buffering area and whether can receives new cell; TxData is a data/address bus, is used to carry the data that transmit between ATM layer and the PHY layer; TxEnb is the transmission enable signal that the ATM layer sends, and in the time of effectively, the data on the expression TxData are effective; TxSOC is the cell initial signal, is used to refer to first byte of the cell of ATM layer transmission.
When the ATM layer will be when the PHY layer sends a cell, the ATM layer at first detects the TxClav signal that the PHY layer sends over, if the TxClav signal is significant level a--high level, then ATM course data/address bus TxData goes up and sends first data H1, ATM layer driving TxEnb and TxSOC signal are effective simultaneously, shown in the 2nd clock cycle of TxClk among the figure.When the PHY layer detects TxEnb signal and TxSOC signal when effective, then the PHY layer starts the receiving course to this cell.
The complete ATM cell of data bus 8 bit wides is made up of 53 bytes, under the normal condition, if not dorsal support backrest transmission of PHY layer, the PHY layer is receiving the 49th byte of this cell, promptly during the P44 byte among the figure, driving the TxClav signal is disarmed state, shown in the 50th clock cycle of TxClk among the figure.The ATM layer is after detecting the TxClav invalidating signal, and the ATM layer can continue to send remaining P44 to these 4 bytes of P48, drives the TxEnb invalidating signal afterwards, finishes the transmission of a cell, shown in the 51st to the 54th clock cycle of TxClk among the figure.For the PHY layer, after driving TxClav signal is disarmed state, need continue to detect 4 efficient clock cycles of TxEnb signal,, just can finish the receiving course of a cell to receive 4 effective bytes corresponding that ATM sends over effective TxEnb signal.
But, if send P44 in the process of P48 byte at the ATM layer, the TxEnb signal that the ATM layer sends is interfered and when the saltus step of disarmed state occurring, can cause the PHY layer can't detect 4 efficient clock cycles of TxEnb signal, the PHY layer can think that the cell that the ATM layer is not finished this as yet sends, and continue to wait for the reception remainder bytes, so the TxClav signal is always inactive level; For the ATM layer, TxEnb is an output signal, can't learn that the TxEnb signal is interfered, so the ATM layer sends and just finish this cell after last 4 bytes and send, the ATM layer is waited for the transmission of restarting next cell after the TxClav signal of PHY layer becomes effectively once more.Therefore, in this case, make ATM layer, PHY layer both sides all wait for the other side's signal, this UTOPIA interface just is in the state of hanging, and forms deadlock, even causes that communication service interrupts, and information dropout has had a strong impact on the reliability of system.
Summary of the invention
In view of this, goal of the invention of the present invention is to provide a kind of solution of deadlock, to solve the deadlock that data transmission interface occurs in the transmission data.
Realize the present invention, at the data transmission interface that adopts cell level transmission control a timer is set, the timing length of setting this timer is at least greater than transmitting a needed clock cycle of complete cell under the normal condition; Need following steps:
Data transmission interface produces the timer enabling signal and starts the timer timing; Judge timer whether timing if then timer resets, and data transmission interface is resetted process ends to the described timing length of setting to data transmission interface transmission interface reset signal; Otherwise data transmission interface judges whether the current data transmission finishes, if then produce timer reset signal and timer is resetted process ends; Otherwise, carry out described judge timer whether timing to the step of the described timing length of setting.
Wherein, the clock synchronization of timer and data transmission interface.
Wherein, described data transmission interface generation timer enabling signal is: the control signal that data transmission interface produces when log-on data is transmitted.
Wherein, described timer comprises to the data transmission interface method that data transmission interface is resetted that transmits control signal: timer is adjusted timer signal by logical circuit and is amplified, and converts the required control signal control data transmission interface of data transmission interface to and resets.
Wherein, the described data transmission interface of this method is Universal Test ﹠ Operations PHY Interface for ATM UTOPIA.Then, the method for described data transmission interface generation timer start-up control signal enabling timer timing comprises: the UTOPIA interface produces the UTOPIA interface when log-on data is transmitted cell initial signal TxSOC starts the timer timing.Perhaps, the UTOPIA interface receives the physical layer FIFO memory transmission of UTOPIA before the log-on data transmission expression memory is the empty signal that can receive data, by this signal enabling timer timing.
Wherein, the timer reset signal of described data transmission interface transmission is: the timer reset signal of exporting when detecting the UTOPIA interface for idle condition.Perhaps be: the full signal of physical layer FIFO memory transmitting and receiving data that the UTOPIA interface receives.
The timing length of described setting is the duration greater than the synchronised clock cycle of 53 UTOPIA interfaces work.
By said method as can be seen, the present invention controls the data transmission procedure of data transmission interface, occur at data transmission interface under the situation of deadlock, can automatically terminate the deadlock of this interface, recover the normal condition of this interface, effectively raise the functional reliability and the fault-tolerant ability of data transmission interface, make the transmission course of data more reliable.The present invention not only can be used for the UTOPIA interface, also can be used for other similar data coffrets.
Description of drawings
The sequential chart that Fig. 1 sends for the UTOPIA interface data.
Fig. 2 solves the flow chart of deadlock for the present invention.
Embodiment
The present invention transmits in the process of data at the UTOPIA interface, and a timer is set, and the timing length that sets in advance this timer transmits needed duration greater than finishing a cell under the normal condition.When the UTOPIA interface starts the cell transmission, start timer simultaneously, if in the timing length of timer, UTOPIA finishes the transmission of cell, then to the timer zero clearing; If the UTOPAI interface is hung, and cause in timing length, not finishing the transmission of cell under abnormal conditions, when then timer arrives predetermined duration, to directly or indirectly control the UTOPIA interface, this interface is carried out enforceable resetting, make interface revert to initial condition, thereby remove deadlock.
Fig. 2 solves the flow chart of deadlock for the present invention.For making purpose of the present invention, technical scheme and advantage clearer, below be sent as example with the data of UTOPIA interface, with reference to accompanying drawing 2, the present invention is described in more detail.
Step 201: the timing length that preestablishes timer.Wherein the clock frequency of timer adopts the TxClk clock frequency.In this example, the UTOPIA interface adopts cell level transmission control, because a cell comprises 53 bytes, at least need 53 TxClk clock cycle a cell could be sent to the PHY layer from the ATM layer, therefore set this timer timing length at least greater than transmitting a needed clock cycle of complete cell under the normal condition, consider the situations such as transmission time-out that might occur, the setting timer is a duration greater than 53 TxClk clock cycle, for example, the timing length that timer can be set is 100 TxClk clock cycle.
When step 202:UTOPIA interface starts the cell transmission, produce the timer enabling signal simultaneously and start the timer timing.Because when ATM course data/address bus TxData goes up first data H1 that sends cell, can drive TxSOC and produce a positive pulse signal, so, this signal deactivation timer timing can be passed through.Perhaps TxEnb, TxClav and TxSOC signal are made up, and by the timing of logical circuit generation timer enabling signal deactivation timer, for example, TxEnb and TxSOC signal are made up, be low level when determining TxEnb, when TxSOC is high level, generate the timing of timer enabling signal deactivation timer by logical circuit.In addition, the UTOPIA interface is before starting the cell transmission, and the expression memory that can receive the FIFO memory transmission of PHY layer is the empty signal that can receive data, the startup that also can remove control timer by this signal.Wherein above-described logical circuit can be realized by PLC.
Step 203: in each TxClk clock cycle, timer adds up 1, and judges whether to be added to predefined duration, if then execution in step 205, otherwise, execution in step 204.
Step 204: according to prior art, the UTOPIA interface judges whether the current cell that transmits transmits end, if then produce a timer reset signal to the timer zero clearing that resets, process ends; Otherwise, continue the transfer of data of this cell, return step 203.For example, locate in the 55th the TxClk clock cycle shown in Figure 1, the ATM layer is sent to the PHY layer normally with this cell, can detect the UTOPIA interface and transfer idle condition to, the zero clearing that resets of timer reset signal of UTOPIA interface output then, control timer.For example, finish when data normally transmit, the FIFO memory of PHY layer can send one and receive the full signal of data, can go resetting of logic control timer by this signal.
Step 205: the timer zero clearing that resets, control the UTOPIA interface simultaneously and reset.Wherein, timer can directly be controlled the UTOPIA interface by timer to the control of UTOPIA, also can adjust timer signal and amplifies by logical circuit, converts the required signal of UTOPIA to and removes to control the UTOPIA interface.When timer is added to predefined threshold values, timer is not received the zero clearing reset signal that the UTOPIA interface sends over as yet, representing then that ATM course PHY layer sends in the process of cell deadlock occurs, at this moment, timer resets by logical circuit control UTOPIA interface, make the UTOPIA Interface status transfer initial condition to, removed the deadlock that occurs in the data transmission procedure, to carry out the transmission of next cell.Logical circuit wherein can be realized by PLC.
As mentioned above, the startup and the zero clearing of UTOPIA interface control timer, or the resetting of timer control UTOPIA interface all can realize by logical circuit.And timer can be provided with according to actual conditions flexibly to the control of UTOPIA interface.Timer can be to the control that resets of whole UTOPIA interface; Also can only control certain signal of this interface, for example, the TxClav signal that sends by control PHY layer resets to the deadlock of the UTOPIA interface that disarmed state also can remove in the background technology to be mentioned.
Timer can carry out timing controlled to the duration that transmits one or more cells, also can carry out timing controlled to certain stage in the cell transport process, as when the saltus step of TxClav signal is disarmed state, just starts timer and carries out timing controlled.
In the process that control UTOPIA interface resets, data in the PHY layer buffering area can be eliminated, but can control the correctness of transfer of data by upper-layer protocol, as require data re-transmitting or the like, this part is not an emphasis of the present invention, no longer narrates herein.
More than be that example describes with the data transmission procedure of UTOPIA interface, DRP data reception process for the UTOPIA interface, the principle that use the present invention solves deadlock is identical, and its moment of distinguishing the starting and ending that only is timer is relevant with the moment of the starting and ending of DRP data reception process.And this method not only is used for the transfer of data of UTOPIA interface, also can be used for the transfer of data of other similar interfaces, as POS-PHY (Packet Over SONET Physical), interfaces such as Any-PHY, CellBus.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of solution of deadlock, it is characterized in that, at the data transmission interface that adopts cell level transmission control a timer is set, the timing length of setting this timer is at least greater than transmitting a needed clock cycle of complete cell under the normal condition; This method may further comprise the steps:
Data transmission interface produces the timer enabling signal and starts the timer timing;
Judge timer whether timing if then timer resets, and data transmission interface is resetted process ends to the described timing length of setting to data transmission interface transmission interface reset signal; Otherwise,
Data transmission interface judges whether the current data transmission finishes, if then produce timer reset signal and timer is resetted process ends; Otherwise, carry out described judge timer whether timing to the step of the described timing length of setting.
2, method according to claim 1 is characterized in that, the clock synchronization of timer and data transmission interface.
3, method according to claim 1 is characterized in that, described data transmission interface produces the timer enabling signal and is: the control signal that data transmission interface produces when log-on data is transmitted.
4, method according to claim 1, it is characterized in that, described timer comprises to the data transmission interface method that data transmission interface is resetted that transmits control signal: timer is adjusted timer signal by logical circuit and is amplified, and converts the required control signal control data transmission interface of data transmission interface to and resets.
5, method according to claim 1 is characterized in that, the described data transmission interface of this method is Universal Test ﹠ Operations PHY Interface for ATM UTOPIA.
6, method according to claim 5, it is characterized in that the method that described data transmission interface produces the timing of timer start-up control signal enabling timer comprises: the UTOPIA interface produces the UTOPIA interface when log-on data is transmitted cell initial signal TxSOC starts the timer timing.
7, method according to claim 5, it is characterized in that, the method that described data transmission interface produces the timing of timer start-up control signal enabling timer further comprises: the UTOPIA interface receives the physical layer FIFO memory transmission of UTOPIA before the log-on data transmission expression memory is the empty signal that can receive data, by this signal enabling timer timing.
8, method according to claim 5 is characterized in that, the timer reset signal that described data transmission interface sends is: the timer reset signal of exporting when detecting the UTOPIA interface for idle condition.
9, method according to claim 5 is characterized in that, the timer reset signal that described data transmission interface sends is: the full signal of physical layer FIFO memory transmitting and receiving data that the UTOPIA interface receives.
10, method according to claim 5 is characterized in that, the timing length of described setting is the duration greater than the synchronised clock cycle of 53 UTOPIA interfaces work.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101154776A CN100344125C (en) | 2003-11-26 | 2003-11-26 | A solution method of data transmission deadlock |
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| CNB2003101154776A CN100344125C (en) | 2003-11-26 | 2003-11-26 | A solution method of data transmission deadlock |
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| CN1622526A CN1622526A (en) | 2005-06-01 |
| CN100344125C true CN100344125C (en) | 2007-10-17 |
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| CNB2003101154776A Expired - Lifetime CN100344125C (en) | 2003-11-26 | 2003-11-26 | A solution method of data transmission deadlock |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576830B (en) * | 2009-06-04 | 2011-11-30 | 中兴通讯股份有限公司 | Deadlock detection method and device of database transaction lock mechanism |
| CN105207907A (en) * | 2015-08-14 | 2015-12-30 | 浪潮集团有限公司 | Method and device used for controlling data forwarding |
| CN105391643B (en) * | 2015-12-09 | 2018-05-25 | 中国航空工业集团公司西安航空计算技术研究所 | Packet stream amount control circuit and method are cascaded durings based on IEEE_std 1394-2008 protocol link layers etc. |
| CN106506279B (en) * | 2016-11-11 | 2019-12-13 | 盛科网络（苏州）有限公司 | Network deadlock state detection method and device |
| CN111277401A (en) * | 2020-01-19 | 2020-06-12 | 芜湖荣芯电子科技有限公司 | Timing reset system and method for ensuring completion of asynchronous communication |
| CN111538599A (en) * | 2020-04-23 | 2020-08-14 | 杭州涂鸦信息技术有限公司 | LINUX-based multithreading deadlock problem positioning method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1986003085A1 (en) * | 1984-11-14 | 1986-05-22 | American Telephone & Telegraph Company | Lockup detection and recovery in a packet switching network |
| CN1337832A (en) * | 2000-08-07 | 2002-02-27 | Lg电子株式会社 | Method for controlling data-flow in communication system |
| CN1350740A (en) * | 1999-03-03 | 2002-05-22 | 汤姆森许可贸易公司 | Method and apparatus for transferring data on a bus to or from a device to be controlled by said bus |
| CN1388455A (en) * | 2002-06-21 | 2003-01-01 | 华中科技大学 | Protocol converting method and device between in-situ bus and serial interface equipment |
| US20030053468A1 (en) * | 1998-10-30 | 2003-03-20 | Feng Deng | Method and apparatus for exiting a deadlock condition |
-
2003
- 2003-11-26 CN CNB2003101154776A patent/CN100344125C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1986003085A1 (en) * | 1984-11-14 | 1986-05-22 | American Telephone & Telegraph Company | Lockup detection and recovery in a packet switching network |
| US20030053468A1 (en) * | 1998-10-30 | 2003-03-20 | Feng Deng | Method and apparatus for exiting a deadlock condition |
| CN1350740A (en) * | 1999-03-03 | 2002-05-22 | 汤姆森许可贸易公司 | Method and apparatus for transferring data on a bus to or from a device to be controlled by said bus |
| CN1337832A (en) * | 2000-08-07 | 2002-02-27 | Lg电子株式会社 | Method for controlling data-flow in communication system |
| CN1388455A (en) * | 2002-06-21 | 2003-01-01 | 华中科技大学 | Protocol converting method and device between in-situ bus and serial interface equipment |
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