CN100340972C - Method for implementing logarithm computation by field programmable gate array in digital auto-gain control - Google Patents
Method for implementing logarithm computation by field programmable gate array in digital auto-gain control Download PDFInfo
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- CN100340972C CN100340972C CNB2005100749336A CN200510074933A CN100340972C CN 100340972 C CN100340972 C CN 100340972C CN B2005100749336 A CNB2005100749336 A CN B2005100749336A CN 200510074933 A CN200510074933 A CN 200510074933A CN 100340972 C CN100340972 C CN 100340972C
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Abstract
The present invention relates to a calculation for realizing level gain errors of loop filter medium frequency input signals in base station receivers in a broadband code division multiple access mobile communication system with field programmable gate arrays when digital automatic gain control is carried out. The calculation is realized by a logarithm operation method of error input signals. The method fully uses the characteristics of data after partial squares of the mantissa of the argument of binary data for recursion bit by bit, and thereby, the numerical value of each bit of the result of data to be calculated is derived. Thereby, calculation is rapidly converged, and calculation errors are reduced in a geometric series mode along with the addition of system resources. One clock cycle is used simply by utilizing high calculation speed of the method, and high-precision requirements can be satisfied by occupying fewest hardware sources because of high convergence speed of calculation.
Description
Technical field
Realize the calculating of electric-level gain error of the intermediate frequency input signal of loop filter when the present invention relates to carry out in the base station receiver digital Auto Gain control in Wideband Code Division Multiple Access (WCDMA) (WCDMA) mobile communication system with field programmable gate array (FPGA), this calculates the logarithm operation method that adopts error input signal and realizes.
Background technology
When in WCDMA (Wideband Code Division Multiple Access (WCDMA)) system base station receiver, carrying out digital Auto Gain control (AGC), need carry out the binary logarithm computing to the loop filter error input signal, to obtain the electric-level gain error of intermediate frequency input signal.The binary logarithm computing method of prior art are look-up table or Series Expansion Method.
Look-up table is exactly that mantissa (size is between 1 and 2) and result data to be obtained as independent variable are made a binary data table, contrasts this tables of data during practical application and just can find the required data of obtaining.If utilize field programmable gate array (FPGA) to realize this logarithm operation in base station receiver, computing velocity is very fast, only needs two clock period.But owing to need store table of logarithm in advance, thereby take the memory resource of system in a large number.And use look-up method institute error calculated bigger, and the data precision of obtaining is difficult to control, and especially when independent variable was big, the independent variable subtle change just can make result of calculation numerical value very big variation occur.When the logarithm operation accuracy requirement is high, just require to enlarge in a large number the capacity of table of logarithm, thereby occupied memory resource quantity will be the geometric series rising.
Series Expansion Method is calculated after exactly logarithmic function being converted into taylor series expansion again, and is as follows:
ln(1+u)＝u-u
2/2+u
3/3-u
4/4+……
Increase along with the progression number of times, the Taylor expansion speed of convergence of logarithmic function is slack-off, if require its error of calculation less than 1%, then to calculate at least in the expansion preceding 100 add up and, and require its logarithm error of calculation less than 0.1% in the real figure AGC control, therefore to calculate at least in the expansion preceding 1000 add up and, so huge operand just need take a large amount of multiplier resources.If when utilizing FPGA to carry out high-precision series expansion algorithm logarithm operation in base station receiver, the FPGA arithmetical unit resource that need take is the geometric series formula and rises, and in fact existing FPGA device is difficult to provide so a large amount of arithmetical unit resource.
Therefore, need to propose a kind of relative few loop filter error input signal logarithm operation method of arithmetical unit resource that takies FPGA with memory resource.
Summary of the invention
The object of the present invention is to provide a kind of FPGA of utilization to realize the loop filter error input signal is asked for the method for logarithm, this method can utilize limited multiplier and totalizer resource to realize logarithm operation.
Method of the present invention makes full use of the data characteristics recursion by turn after the binary data independent variable magnitude portion square, thereby differentiate goes out to wait to ask each bit value of data result, thereby make very rapid convergence of computation process, the error of calculation is geometric series with the increase of system resource and reduces.When utilizing FPGA to realize this patent computing method, computing velocity is the fastest only uses a clock period, and because calculated convergence rate is very fast, only takies few FPGA hardware resource and just can satisfy high-precision requirement.
The field programmable gate array that utilizes of the present invention is asked for the method for logarithm to the loop filter error originated from input, comprises step:
The first step, a plurality of error originated from input data of waiting to ask logarithm are selected to wait to ask in the data certain error originated from input data to enter to ask after MUX successively counting unit are calculated under the management coordination unit controls;
Second step, ask the part of the normalization in the counting unit is obtained the integral part of logarithm numerical value, the error originated from input data radix point that normalization is about to binary representation moves to left or moves to right, left and right figure place of moving is the integral part numerical value of logarithm numerical value, move to left then that the integral part of this logarithm numerical value is a positive integer, move to right then that the integral part of this logarithm numerical value is a negative integer, will treat that through normalization computing error originated from input data limit is (1,2) between, satisfied the condition of the fraction part of asking logarithm;
The 3rd step, ask the fraction part of square comparing unit in the counting unit being obtained logarithm numerical value, concrete steps are:
Binary numeral is with 1.X after the normalization
1X
2X
3---X
mExpression is carried out asking the fraction part of its logarithm numerical value 2 to be the logarithm operation of the truth of a matter to this binary fraction, and this logarithm value fraction part is expressed as 0.Y
1Y
2Y
3---Y
n
Utilize the FPGA multiplier to 1.X
1X
2X
3---X
nSquare calculate, the result is expressed as b
1, with b
1With 2 compare, if b
1〉=2, then infer and know Y
1=1, on the contrary Y then
1=0; Obtain the right primary Y as a result of radix point of binary logarithm numerical value Y thus
1
Obtaining Y
1After can draw Y
2The recursion independent variable Q of position
2=0.Y
2Y
3Y
n, under the situation of Y1=0, mean 1.X
1X
2X
3---X
nSquare B
1Less than 2, can derive Q
2=b
1At Y
1Under=1 the situation, mean 1.X
1X
2X
3---X
nSquare more than or equal to 2, then this square numerical value is expressed as 1X with binary digit
11.X
21X
31---X
M1, can be equivalent to radix point and move to left one with this numerical value divided by 2, obtain numerical value Q thus
2=b
1/ 2, thus can be with Q
2Be expressed as binary digit 1.X
11X
21X
31---X
M1, utilize the FPGA multiplier then to 1.X
11X
21X
31---X
M1Square calculate, the result is expressed as b
2, with b
2With 2 compare, if b
2〉=2, then Y is known in deducibility
2=1, on the contrary Y then
2=0; Obtain the right deputy Y as a result of radix point of binary logarithm numerical value Y thus
2
Obtaining Y
2After can draw Y
3The recursion independent variable Q of position
3=0.Y
3Y
4Y
n, at Y
2Under=0 the situation, mean 1.X
11X
21X
31---X
M1Square B
2Less than 2, can derive Q
3=b
2At Y
2Under=1 the situation, mean 1.X
11X
21X
31---X
M1Square more than or equal to 2, then this square numerical value is expressed as 1X with binary digit
12.X
22X
32---X
M2, can be equivalent to radix point and move to right one with this numerical value divided by 2, obtain numerical value Q thus
3=b
2/ 2, thus can be with Q
2Be expressed as binary digit 1.X
12X
22X
32---X
M2, utilize the FPGA multiplier then to 1.X
12X
22X
32---X
M2Square calculate, the result is expressed as b
3, with b
3With 2 compare, if b
3〉=2, then Y is known in deducibility
3=1, on the contrary Y then
3=0; Obtain the right deputy Y as a result of radix point of binary logarithm numerical value Y thus
3
Carry out repeatedly according to above-mentioned steps, up to the Y that obtains required precision
1, Y
2, Y
3..., Y
n, obtain the fraction part of logarithm value thus;
The 4th step, ask the integral part of the logarithm numerical value that the anti-normalization in the counting unit is partly partly tried to achieve normalization and the fraction part of the logarithm numerical value that square comparing unit is tried to achieve to add up, obtain needed result;
In the 5th step, demultplexer is sent to needed result successively in the corresponding data register and exports under the management coordination unit controls.
The present invention utilizes the addition among the FPGA and function combinations such as multiply each other, and only just can realize the logarithm of asking of complex input signal error with very little resources costs, is a kind of simple, reliable, practical method.
Description of drawings
Fig. 1 carries out the main functional modules synoptic diagram of binary logarithm operational method for FPGA of the present invention.
Fig. 2 carries out asking in the binary logarithm operational method step of logarithm numerical value fraction part for FPGA of the present invention.
Embodiment
Describe method of the present invention in detail below in conjunction with accompanying drawing.
Actual when utilizing FPGA to realize digital AGC, usually there are the error originated from input data of a plurality of loop filters need ask for logarithm numerical value, and these known input data are 32 or 16 positive integers, logarithm value to be obtained contains integer and fraction part, therefore need take time-multiplexed mode to obtain the logarithm value that each waits to ask data successively, promptly the data to be asked that will import successively are sent to special-purpose asking counting unit are calculated, the result that will try to achieve outputs in the corresponding logarithm value register simultaneously, so just need the management coordination unit to manage, and when asking each to wait to ask the logarithm of data at every turn, all want earlier its normalization, the radix point that is about to binary numeral moves to left or moves to right, make binary numeral be limited between (1,2), obtain fraction part according to process shown in Figure 2 then.
Explain that in conjunction with Fig. 1 the FPGA of utilization of the present invention asks for total step of logarithm numerical method to the error originated from input data of loop filter:
The first step waits to ask data under the management coordination unit controls, selects wherein certain error originated from input data to enter to ask after MUX successively counting unit is calculated;
Second step, ask the part of the normalization in the counting unit is obtained integral part, the error originated from input numerical value radix point that normalization is about to binary representation moves to left or moves to right, left and right figure place of moving is the integral part numerical value of logarithm numerical value, move to left then that this integral part is a positive integer, move to right then that this integral part is a negative integer, will treat that through normalization computing error originated from input data limit is (1,2) between, satisfied the condition of the fraction part of asking logarithm;
In the 3rd step, ask the fraction part of square comparing unit in the counting unit being obtained logarithm numerical value;
In the 4th step, the decimal of asking integer that the part of the anti-normalization in the counting unit is partly tried to achieve normalization and square comparing unit to try to achieve is added up, and obtains needed result;
In the 5th step, demultplexer is sent to needed result successively in the corresponding data register and exports under the management coordination unit controls.
In the above-mentioned third step, after the error originated from input of loop filter carries out normalization, treat that it is 1 binary fraction that the operand value becomes integral part, with 1.X
1X
2X
3---X
mExpression, wherein X
1, X
2, X
3..., X
mNumerical value be 0 or 1.This binary fraction is carried out asking its logarithm value 2 to be the logarithm operation of the truth of a matter, and this logarithm value is expressed as 0.Y
1Y
2Y
3---Y
n
If establish U=1.X
1X
2X
3---X
m, Y=0.Y
1Y
2Y
3---Y
n, then logarithm operation is:
Y＝LOG
2U
Above-mentioned formula is expressed as with exponential form:
2
0Y1Y2Y3……Yn＝1.X
1X
2X
3---X
m (1)
With the following formula both sides simultaneously square, it is as follows to draw equation:
2
Y1Y2Y3……Yn＝(1.X
1X
2X
3---X
m)
2 (2)
In the formula 2, formula 1 left side square is equivalent to index and takes advantage of 2, and for binary fraction 0.Y
1Y
2Y
3---Y
nMultiply by two and equal radix point and move to right one,
Note b1=(1.X
1X
2X
3---X
m)
2
Utilize a multiplier among the FPGA to 1.X
1X
2X
3---X
nSquare calculate, try to achieve b
1Numerical value compares this numerical value and 2, if b
1〉=2, then Y is known in deducibility
1=1, on the contrary Y then
1=0; Obtain the right primary Y as a result of radix point of binary logarithm numerical value Y thus
1
Obtain Y
1After, recursion is obtained Y again
2
By formula (2) as can be known:
Work as Y
0=0 o'clock, 2
0.Y2Y3 ... Yn=B
1(this moment B
1Between 1 and 2)
Work as Y
1=1 o'clock, 2
0.Y2Y3 ... Yn=B
1/ 2; (this moment B
1Between 2 and 4, B
1/ 2 between 1 and 2)
Thereby can remember and make following formula:
2
0.Y2Y3…Yn＝1.X
11X
21X
31---X
M1 (3)
With formula 3 two ends simultaneously square, can obtain formula 4:
2
Y2.Y3…Yn＝(1.X
11X
21X
31---X
m1)
2 (4)
If b2=(1.X11X21X31---Xm1)
2
Utilize multiplier of FPGA to 1.X
11X
21X
31---X
M1Square calculate, try to achieve b
2Numerical value compares this numerical value and 2, if b
2〉=2, then Y is known in deducibility
2=1, on the contrary Y then
2=0; Obtain the right deputy Y as a result of radix point of binary logarithm numerical value Y thus
2
Obtain Y
2After, recursion is obtained Y again
3
By formula (4) as can be known:
Work as Y
2=0 o'clock, 2
0.Y2Y3 ... Yn=B
2(this moment B
2Between 1 and 2)
Work as Y
2=1 o'clock, 2
0.Y2Y3 ... Yn=B
2/ 2; (this moment B
2Between 2 and 4, B
2/ 2 between 1 and 2)
Thereby can remember and make following formula:
2
0.Y2Y3…Yn＝1.X
12X
22X
32---X
m2 (5)
With formula 5 two ends simultaneously square, can obtain formula 6:
2
Y2.Y3…Yn＝(1.X
12X
22X
32---X
m2)
2 (6)
If b3=is (1.X
12X
22X
32---X
M2)
2
Utilize multiplier of FPGA to 1.X
12X
22X
32---X
M2Square calculate, try to achieve b
3Numerical value compares this numerical value and 2, if b
3〉=2, then Y is known in deducibility
3=1, on the contrary Y then
3=0; Obtain the right deputy Y as a result of radix point of binary logarithm numerical value Y thus
3
Carry out repeatedly according to above-mentioned steps, up to the Y1 that obtains required precision, Y2, Y3 ..., Yn, obtain the fraction part of logarithm value thus.
When realizing above-mentioned algorithm, only just can calculate the one digit number value the slowlyest with three clock period with FPGA.Can be during specific implementation according to the system resource of the pipeline system configuration FPGA that adopts.Find the solution n bit value (Y with needs
1Y
2Y
n) be example, if adopt Fully-pipelined mode, need n multiplier, be that each square operation takies a multiplier, take FPGA resource maximum like this, but computing velocity be the fastest, ask for one logarithmic data on average only taken a clock period, overall delay 3n clock period.If adopt no pipeline system, only use a multiplier, when asking the square operation of bits per inch value, share, occupying system resources is minimum like this, but computing velocity is the slowest, asks for one and need take 3n clock period to logarithmic data.If adopt the semi-fluid pipeline mode, promptly comprehensive above-mentioned two kinds of account forms, a multiplier is shared in the calculating of partial data position, pipeline system is adopted in the calculating of partial data position, suitably allocate in conjunction with the actual FPGA resource that has, in the hope of exchanging suitable computing velocity and data delay for suitable FPGA resource.
Claims (1)
1. one kind is utilized field programmable gate array that the loop filter error originated from input is asked for the method for logarithm, comprises step:
The first step, a plurality of error originated from input data of waiting to ask logarithm are selected wherein certain error originated from input data to enter to ask after multichannel is selected divider successively counting unit are calculated under the management coordination unit controls;
Second step, ask the part of the normalization in the counting unit is obtained the integral part of logarithm numerical value, the error originated from input data radix point that normalization is about to binary representation moves to left or moves to right, left and right figure place of moving is the integral part numerical value of logarithm numerical value, move to left then that the integral part of this logarithm numerical value is a positive integer, move to right then that the integral part of this logarithm numerical value is a negative integer, will treat that through normalization computing error originated from input data limit is (1,2) between, satisfied the condition of the fraction part of asking logarithm;
The 3rd step, ask the fraction part of square comparing unit in the counting unit being obtained logarithm numerical value, concrete steps are:
Binary numeral is with 1.X after the normalization
1X
2X
3---X
mExpression is carried out asking the fraction part of its logarithm numerical value 2 to be the logarithm operation of the truth of a matter to this binary fraction, and this logarithm numerical value is made as Y, is expressed as Y=0.Y
1Y
2Y
3---Y
n
Utilize the FPGA multiplier to 1.X
1X
2X
3---X
mSquare calculate, the result is expressed as b
1, with b
1With 2 compare, if b
1〉=2, then infer and know Y
1=1, on the contrary Y then
1=0; Obtain the right primary Y as a result of radix point of binary logarithm numerical value Y thus
1
Obtaining Y
1After draw Y
2The recursion independent variable Q of position
2=0.Y
2Y
3Y
n, at Y
1Under=0 the situation, mean 1.X
1X
2X
3---X
mSquare b
1Less than 2, derive
At Y
1Under=1 the situation, mean 1.X
1X
2X
3---X
mSquare more than or equal to 2, then this square numerical value is expressed as 1X with binary digit
11.X
21X
31---X
M1, this numerical value divided by 2, is equivalent to radix point and moves to left one, obtain numerical value thus
Thereby with 2
Q2Be expressed as binary digit 1.X
11X
21X
31---X
M1, utilize the FPGA multiplier then to 1.X
11X
21X
31---X
M1Square calculate, the result is expressed as b
2, with b
2With 2 compare, if b
2〉=2, then infer and know Y
2=1, on the contrary Y then
2=0; Obtain the right deputy Y as a result of radix point of binary logarithm numerical value Y thus
2
Obtaining Y
2After draw Y
3The recursion independent variable Q of position
3=0.Y
3Y
4Y
n, at Y
2Under=0 the situation, mean 1.X
11X
21X
31---X
M1Square b
2Less than 2, derive
At Y
2Under=1 the situation, mean 1.X
11X
21X
31---X
M1Square more than or equal to 2, then this square numerical value is expressed as 1X with binary digit
12.X
22X
32---X
M2, this numerical value divided by 2, is equivalent to radix point and moves to left one, obtain numerical value thus
Thereby with 2
Q3Be expressed as binary digit 1.X
12X
22X
32---X
M2, utilize the FPGA multiplier then to 1.X
12X
22X
32---X
M2Square calculate, the result is expressed as b
3, with b
3With 2 compare, if b
3〉=2, then infer and know Y
3=1, on the contrary Y then
3=0; Obtain the right tertiary Y as a result of radix point of binary logarithm numerical value Y thus
3
Carry out repeatedly according to above-mentioned steps, up to the Y that obtains required precision
1, Y
2, Y
3..., Y
n, obtain the fraction part of logarithm numerical value thus;
The 4th step, ask the integral part of the logarithm numerical value that the anti-normalization in the counting unit is partly partly tried to achieve normalization and the fraction part of the logarithm numerical value that square comparing unit is tried to achieve to add up, obtain needed result;
In the 5th step, multichannel selects divider under the management coordination unit controls, needed result is sent in the corresponding data register successively exports.
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| CN108170402A (en) * | 2017-11-24 | 2018-06-15 | 中核控制系统工程有限公司 | A kind of floating number logarithmic function implementation method based on FPGA |
| CN110163357B (en) * | 2018-02-13 | 2021-06-25 | 上海寒武纪信息科技有限公司 | Computing device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020190892A1 (en) * | 2001-04-03 | 2002-12-19 | Hallse Brian L. | Digital base-10 logarithm converter |
| US20040122878A1 (en) * | 2002-12-24 | 2004-06-24 | Lockheed Martin Corporation | Circuits and methods for implementing approximations to logarithms |
| US20040153488A1 (en) * | 2002-07-23 | 2004-08-05 | Pioneer Corporation | Logarithmic transformer and method of logarithmic transformation |
| CN1545766A (en) * | 2002-04-10 | 2004-11-10 | ��˹��ŵ�� | Device and method for cdma-signal power estimation |
-
2005
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020190892A1 (en) * | 2001-04-03 | 2002-12-19 | Hallse Brian L. | Digital base-10 logarithm converter |
| CN1545766A (en) * | 2002-04-10 | 2004-11-10 | ��˹��ŵ�� | Device and method for cdma-signal power estimation |
| US20040153488A1 (en) * | 2002-07-23 | 2004-08-05 | Pioneer Corporation | Logarithmic transformer and method of logarithmic transformation |
| US20040122878A1 (en) * | 2002-12-24 | 2004-06-24 | Lockheed Martin Corporation | Circuits and methods for implementing approximations to logarithms |
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Address after: 430205 No.1 tanhu 2nd Road, Canglong Island, Jiangxia District, Wuhan City, Hubei Province Patentee after: CITIC Mobile Communication Technology Co.,Ltd. Address before: 430205 No.1 tanhu 2nd Road, Canglong Island, Jiangxia District, Wuhan City, Hubei Province Patentee before: CITIC Mobile Communication Technology Co., Ltd |