CN100336230C - Multi finger-like transistor - Google Patents
Multi finger-like transistor Download PDFInfo
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- CN100336230C CN100336230C CNB2003101026602A CN200310102660A CN100336230C CN 100336230 C CN100336230 C CN 100336230C CN B2003101026602 A CNB2003101026602 A CN B2003101026602A CN 200310102660 A CN200310102660 A CN 200310102660A CN 100336230 C CN100336230 C CN 100336230C
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- transistor
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- many finger
- finger transistor
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- 239000000758 substrate Substances 0.000 claims abstract description 35
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000035876 healing Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- NOQGZXFMHARMLW-UHFFFAOYSA-N Daminozide Chemical group CN(C)NC(=O)CCC(O)=O NOQGZXFMHARMLW-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a multi-finger type transistor which comprises a plurality of parallel transistors, wherein each transistor comprises a grid dielectric layer, a grid electrode area and a source electrode /drain electrode area, and is positioned in a drift area of the peripheral substrate of the source electrode /drain electrode area. The drift area separates the source electrode /drain electrode area and a channel area under the grid electrode. The width of the drift area extending from the side edge of the source electrode /drain electrode area is gradually increased to the center part from the margin part of the multi-finger type transistor.
Description
Technical field
The present invention relates to a kind of semiconductor assembly structure, be specifically related to a kind of many finger transistor structure, it is suitable for use as static discharge protection component.
Background technology
Because the size of integrated circuit package is more and more little, it is more prone to be subjected to static discharge (electrostatic discharge, the ESD) destruction of electric current, the especially the thinnest gate oxide of thickness.Therefore; extra esd protection assembly generally all is set on the integrated circuit; wherein a kind of promptly is many finger transistor (multi-finger transistor), and this transistorlike is made up of a plurality of N type metal oxide semiconductor transistors (NMOS transistor) usually.
Please refer to Fig. 1, the figure shows existing many finger transistor structure, wherein Fig. 1 (A) is a top view, and Fig. 1 (B)/(C) then is respectively along the profile that B-B '/C-C ' line dissects among Fig. 1 (A).As shown in Figure 1, many finger transistor 100 are positioned in the P type substrate 10, and it comprises a plurality of grids 110, N type source area 120, N type drain region 130, field oxide 140 and drift region 150.Wherein, two electrical contact zones 12 are arranged in the P type substrate 10, they are positioned at the both sides of many finger transistor 100.Grid 110 is separated by by gate dielectric layer 108 and substrate 10, and grid 110 belows are provided with channel region 106.Be separated with field oxide 140 between source/drain region 120/130 and the channel region 106, and drift region 150 is below the field oxide 140 between source/drain region 120/130 and the channel region 106.In addition, the dotted line box indicating among Fig. 1 (A) is in order to the profile of the mask layer opening of definition drift region 150.
Moreover, Fig. 1 (B) shows a plurality of NPN parasitic bipolar junction transistor (the bipolar junction transistor in many finger transistor 100, BJT), wherein each BJT is all by a N type drain region 130 (collector electrode), a N type source area 120 (emitter), and P type substrate 10 (base stage) constitutes.
As shown in Figure 1, because the electrical contact zone 12 of middle NMOS distance is far away, so the base resistance (R of its parasitic BJT
Sub) higher; Simultaneously, because each drain electrode puncture voltage of 130 is identical, so it is all identical to flow to the breakdown current of substrate 10 from each drain electrode 130.Therefore, when ESD takes place when, middle its collector electrode of parasitic BJT (drain electrode 130) can be than higher (because of the relation of V=IR) with the face that the connects voltage of base stage (substrate 10), it is unlocked more earlier, as people such as Hsu described in " An Analytical Breakdown Model forShort-Channel MOSFET ' S " (IEEE Trans.Electron Device November 1982) literary composition.Therefore, on the NMOS in the middle of the ESD electric current will concentrate on, make its drain electrode be easy to generate contact spike (contact spiking) or junction breakdown (junction punch) equivalent damage, cause the ESD protective capacities of these many finger transistor greatly to reduce.
For this reason, United States Patent (USP) 5,831 has proposed a kind of solution No. 316, that is, the electrical contact zone of P well or the substrate of P type is distributed in the source area of many finger transistor, so that the base resistance of each parasitic BJT is identical.Yet this method will increase the area of many finger transistor greatly, be unfavorable for the downsizing of assembly.
Summary of the invention
For addressing the above problem, the present invention proposes a kind of many finger transistor, and the special construction of its drift region can make each parasitic BJT can be unlocked simultaneously when ESD takes place, thereby the drain region that prevents inter-transistor is destroyed.
Many finger transistor of the present invention comprise a plurality of transistors arranged side by side.Each transistor comprises gate dielectric layer, grid, source/drain region, and drift region, wherein gate dielectric layer and grid are positioned in the substrate, source/drain region is arranged in the grid substrate on two sides, and the drift region is arranged in the substrate of source/periphery, drain region, and the channel region of separation source/drain region and grid below.The extended width of the side of each Zi Yuan/drain region, drift region increases with the increase of the distance of corresponding crystal pipe and the electrical contact zone of substrate.That is when electrical contact zone was positioned at dual-side on the transistor arrangement direction of many finger transistor, the drift region extension width increased progressively towards mid portion from the marginal portion of many finger transistor.In addition, above-mentioned drift region for example can be positioned under the separator.
In many finger transistor of the present invention, when healing when big from the extended width of drain region side in the drift region, the puncture voltage of drain region is also bigger, makes its substrate current when the ESD phenomenon takes place littler.Therefore, smaller from the substrate current in transistor drain district far away, the electrical contact zone of substrate, thus can offset the bigger effect of base resistance of its parasitic BJT.So each parasitic BJT can be unlocked simultaneously, make that the ESD electric current is unlikely to concentrate on the part transistor, and can guarantee the electrostatic protection function of many finger transistor.Moreover, because the present invention is not provided with the electrical contact zone of extra substrate, so there is not the problem that the assembly area increases in the existing solution.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, preferred implementation cited below particularly also elaborates in conjunction with the accompanying drawings.In the accompanying drawing:
Fig. 1 shows existing many finger transistor structure, and wherein Fig. 1 (A) is a top view, and Fig. 1 (B)/(C) then is respectively along the profile that B-B '/C-C ' line dissects among Fig. 1 (A);
Fig. 2 shows many finger transistor structure of the preferred embodiment for the present invention, and wherein Fig. 2 (A) is a top view, and Fig. 2 (B)/(C) is respectively along the profile that B-B '/C-C ' line dissects among Fig. 2 (A);
Fig. 3 shows the formation method of drift region in the preferred embodiment for the present invention, wherein Fig. 3 (A) is the top view of the structure of phase I after finishing, Fig. 3 (B)/(C) is respectively the profile that B-B '/C-C ' line dissects in Fig. 3 (A), Fig. 3 (D)/(E) for the structure of second stage after finishing respectively along the middle profile that B-B '/C-C ' line dissects of Fig. 3 (A);
Fig. 4 shows in the preferred embodiment for the present invention another example in order to the mask open shape of definition drift region.
The drawing reference numeral explanation
10,20 substrates
12, the electrical contact zone of 22 substrates
100, finger transistor more than 200
106,260 channel regions
108,208 gate dielectric layers
110,210 grids
120,220 source areas
130,230 drain regions
140,240 field oxides
150,250 drift regions
202 mask layers
204 photoresist layers
206 photoresist openings
400 mask layer openings
Fate, 410 drain region
The W width
Embodiment
Please refer to Fig. 2, the figure shows many finger transistor structure of the preferred embodiment for the present invention, wherein Fig. 2 (A) is a top view, and Fig. 2 (B)/(C) is respectively along the profile that B-B '/C-C ' line dissects among Fig. 2 (A).
As shown in Figure 2, many finger transistor 200 are positioned on substrate of P type or the P well 20, and it comprises a plurality of grids 210, N type source area 220, N type drain region 230, field oxide 240, and drift region 250.Wherein, two electrical contact zones 22 are arranged in the P well 20, they are positioned at the both sides in the nmos pass transistor orientation of many finger transistor 200.The homonymy end of each grid 210 all is electrical connected, and is separated by with gate dielectric layer 208 and substrate, and the below is provided with channel region 260.In the P well 20 between each grid 210 of source area 220 and drain region 230, and alternately arrange, wherein arbitrary drain region 230 or non-outermost arbitrary source area 220 are shared by two NMOS, and the width of drain region 230 is greater than source area 220, shown in Fig. 2 (B).Field oxide 240 is positioned on the zone source/drain region 220/230 and the channel region 260, and separates source/drain region 220/230 and channel region 260.Some is covered this field oxide 240 by grid 210, and drift region 250 then is positioned under the field oxide 240.In addition, the dotted line among Fig. 2 (A) represents that this names a person for a particular job in explanation after a while in order to the profile of the mask layer opening of definition drift region 250.
Please continue with reference to Fig. 2, for the NMOS of both sides alar part, its drift region 250 is only between source/drain region 220/230 and grid 210; And for the NMOS of centre, 250 of its drift regions surround drain region 230.In other words, 230 side extends a width W from the drain region in the drift region 250 of middle NMOS, shown in Fig. 2 (C).Because 230 both sides, drain region of middle NMOS have more one section drift region 250, so its curvature that connects the face exhaustion region can reduce, cause its puncture voltage to be higher than the drain region 230 of the NMOS of two flanks.
In addition, Fig. 2 (B) also shows a plurality of parasitic BJT in many finger transistor 200, and wherein each is by a N type drain region 230 (collector electrode), a N type source area 220 (emitter), and P well 20 (base stage) constitutes.Because electrically contact zone 22 is positioned at the both sides of many finger transistor 200, so more at its base resistance of the parasitic BJT of centre R
SubBigger.
Then please refer to Fig. 3, the figure shows the formation method of drift region 250 in the preferred embodiment for the present invention, wherein Fig. 3 (A) is the top view of the structure of phase I after finishing, and Fig. 3 (B)/(C) for its respectively along B-B '/C-C ' line dissects among Fig. 3 (A) profile.In addition, Fig. 3 (D)/(E) for the structure of second stage after finishing along B-B '/C-C ' line dissects among Fig. 3 (A) profile.
Please refer to Fig. 3 (A)/(B)/(C), at first in substrate 20, form the mask layer 202 of composition, it roughly covers the zone (asking comparison chart 2 (A)) that will form channel region 260 and source/drain region 220/230, in substrate 20, form the photoresist layer 204 of composition again, it has the mid portion broad and divides the opening 206 of making three sections, and the width of each section of described opening 206 is with corresponding with the extension width of the drift region 250 that forms after a while.Then, be mask with mask layer 202 with photoresist layer 204, in exposed substrate 20, form drift region 250, its method for example is an ion implantation.
Then, please refer to Fig. 3 (D)/(E), after removing photoresist layer 204, carry out a thermal oxidation process,, thus, drift region 250 is positioned under the field oxide 240 to form field oxide 240 in the substrate 20 that covers at not masked layer 202.
Ensuing operation is to form gate oxide, definition grid, and source/drain region etc., please refer to Fig. 2.Wherein, the formation method of gate oxide 208 for example is the wet type thermal oxidation method, and the material of grid 210 for example can be with the formed polysilicon of Low Pressure Chemical Vapor Deposition (LPCVD).
In addition, when transistor size that many finger transistor comprised more and in the middle made from the gap of the base resistance of edge transistors when bigger, the extension width of drift region also can have the more variation of multistage.In detail, many finger transistor can be divided into 2m+1 section (m=1,2 or other positive integer) on its transistor arrangement direction, the drift region extension width minimum of edge section wherein, and increase progressively piecemeal towards centre portion.
For instance, when m=2, the mask open shape that is used for defining the drift region can be as shown in Figure 4.In Fig. 4, the mask open label is 400, and label 410 is the predetermined zone that forms the drain region.Mask open 400 is divided into five sections, and wherein two the pairing drift region of section extension widths at edge are 0, and increase progressively piecemeal towards centre portion.That is the pairing drift region of centre portion extension width maximum for example is 1.0 μ m; The two sections pairing drift region extension width adjacent with centre portion takes second place, and for example is 0.5 μ m.
As mentioned above, in many finger transistor of the preferred embodiment for the present invention, when healing when big from the extended width of the side of drain region in the drift region, the puncture voltage of drain region is also bigger, makes its substrate current when the ESD phenomenon takes place littler.Therefore, the substrate current of middle NMOS drain region is smaller, can offset the base resistance R of its parasitic BJT
SubBigger effect.So, each parasitic BJT can be unlocked simultaneously, makes on the unlikely NMOS that concentrates on part of ESD electric current, and can guarantee the electrostatic protection function of many finger transistor.Moreover, because the present invention is not provided with the electrical contact zone of extra substrate, so the problem that does not yet exist the aforementioned components area to increase.
In addition, though the preferred implementation of the invention described above is to be positioned under the situation of many finger transistor both sides in electrical contact zone, the practice that adopts the drift region extension width to increase progressively towards mid portion by many finger transistor marginal portion, but according to principle of the present invention, also can be applicable to electrical contact zone is not the situation that is positioned at many finger transistor both sides.In detail, no matter base resistance R how, as long as the extension width of drift region is increased with the distance between the electrical contact zone of transistor AND gate, just can substrate current effect decrescence be offset in the position of electrical contact zone
SubCumulative effect, and each parasitic BJT is unlocked simultaneously, to reduce the ruined probability of many finger transistor.
Though the present invention discloses as above with preferred implementation; but it is not to be limitation of the present invention; any those of ordinary skills are under the prerequisite that does not exceed design of the present invention and protection range; all can make various remodeling and retouching, so protection scope of the present invention should be as the criterion with the claimed scope of appending claims.
Claims (13)
1. finger transistor more than a kind comprises:
A plurality of transistors arranged side by side, each transistor comprises:
One gate dielectric layer and a grid are positioned in the substrate;
One source/drain region is arranged in the described substrate of described grid both sides; And
One drift region is arranged in the described substrate of described source/periphery, drain region and separates this source/drain region and a channel region of described grid below,
Wherein, the width of each drift region Zi Yuan/drain region side extension increases progressively towards mid portion from the marginal portion of described many finger transistor.
2. many finger transistor as claimed in claim 1 wherein, are divided into 2m+1 section in described transistorized orientation, wherein m is a positive integer, and the drift region extension width minimum of edge section, and this width increases progressively piecemeal towards centre portion.
3. many finger transistor as claimed in claim 2, wherein, m is 1 or 2.
4. many finger transistor as claimed in claim 2, wherein, the drift region extension width of edge section is 0.
5. many finger transistor as claimed in claim 1, wherein, arbitrary transistorized described drift region is positioned under the separator, and this described separator in transistorized described grid cover part.
6. many finger transistor as claimed in claim 5, wherein, described separator comprises a field oxide.
7. many finger transistor as claimed in claim 1, wherein, two adjacent transistor are shared an one source pole district or a drain region.
8. many finger transistor as claimed in claim 7, the width of wherein said drain region is greater than the width of described source area.
9. finger transistor more than a kind comprises:
A plurality of transistors arranged side by side, each transistor comprises:
One gate dielectric layer and a grid, it is positioned in the substrate, and an electrical contact zone is arranged in this substrate;
One source/drain region is arranged in the described substrate of described grid both sides; And
One drift region is arranged in the described substrate of described source/periphery, drain region, and separates one of this source/drain region and described grid below channel region,
Wherein, the width of each drift region Zi Yuan/drain region side extension increases with the distance between the electrical contact zone of described transistor AND gate of correspondence.
10. many finger transistor as claimed in claim 9, wherein, arbitrary transistorized described drift region is positioned under the separator, and this described separator in transistorized described grid cover part.
11. many finger transistor as claimed in claim 10, wherein, described separator comprises a field oxide.
12. many finger transistor as claimed in claim 9, wherein, two adjacent transistor are shared an one source pole district or a drain region.
13. many finger transistor as claimed in claim 12, wherein, the width of described drain region is greater than the width of described source area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101026602A CN100336230C (en) | 2003-10-28 | 2003-10-28 | Multi finger-like transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101026602A CN100336230C (en) | 2003-10-28 | 2003-10-28 | Multi finger-like transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1612354A CN1612354A (en) | 2005-05-04 |
| CN100336230C true CN100336230C (en) | 2007-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101026602A Expired - Lifetime CN100336230C (en) | 2003-10-28 | 2003-10-28 | Multi finger-like transistor |
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| CN (1) | CN100336230C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400839B (en) * | 2013-08-14 | 2016-03-02 | 上海华力微电子有限公司 | High pressure ESD device domain structure and comprise the chip of this domain structure |
| CN106874528A (en) * | 2015-12-10 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | The resistance calculations method of many finger transistors and the emulation mode of many finger transistors |
| CN117010321A (en) * | 2023-06-06 | 2023-11-07 | 北京华大九天科技股份有限公司 | EM and IR analysis method for multi-finger MOS device layout |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005523A2 (en) * | 2001-07-05 | 2003-01-16 | Sarnoff Corporation | Electrostatic discharge (esd) protection device with simultaneous and distributed self-biasing for multi-finger turn-on |
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2003
- 2003-10-28 CN CNB2003101026602A patent/CN100336230C/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005523A2 (en) * | 2001-07-05 | 2003-01-16 | Sarnoff Corporation | Electrostatic discharge (esd) protection device with simultaneous and distributed self-biasing for multi-finger turn-on |
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| CN1612354A (en) | 2005-05-04 |
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