CN100336215C - Micron level chip packing structure - Google Patents
Micron level chip packing structure Download PDFInfo
- Publication number
- CN100336215C CN100336215C CNB2004100648063A CN200410064806A CN100336215C CN 100336215 C CN100336215 C CN 100336215C CN B2004100648063 A CNB2004100648063 A CN B2004100648063A CN 200410064806 A CN200410064806 A CN 200410064806A CN 100336215 C CN100336215 C CN 100336215C
- Authority
- CN
- China
- Prior art keywords
- layer
- packing structure
- copper post
- micron level
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012856 packing Methods 0.000 title claims abstract description 14
- 239000010949 copper Substances 0.000 claims abstract description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000003466 welding Methods 0.000 abstract 4
- 239000000126 substance Substances 0.000 abstract 1
- 229910052718 tin Inorganic materials 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Landscapes
- Gasket Seals (AREA)
- Wire Bonding (AREA)
Abstract
The present invention relates to micron level chip packing structure. A welding pad 2 is arranged on one surface of a chip body 1, and the outer periphery of the welding pad 2 and the surface of the chip body 1 outside the outer periphery are respectively provided with a protecting layer 3. The present invention is characterized in that the protecting layer 3 of the surface of the welding pad 2 and the protecting layer of the outer periphery is stacked with a titan layer 4, a copper layer 5 and a copper post 6 in order, wherein the top end of the copper post 6 is implanted with a tin ball 7. The packing structure of the present invention can enhance the binding force of the jointing position of the implanted balls and creates a sufficient substance space in order to prevent the tin ball from departure from the welding pad.
Description
Technical field:
The present invention relates to a kind of micron level chip packing structure.Belong to integrated circuit or Discrete device packaging technical field.
Background technology:
In recent years, integrated circuit or discrete device consumer products demand heighten, the also corresponding increase of its kind.The metal wire of disk factory reduces, and the Chip Packaging product moves towards semicon industry development of technology such as miniaturization under the prerequisite of the Performance And Reliability that does not influence product, be the mainstay that satisfies this type of demand.
For many years, the naked brilliant encapsulation of chip is widely used, and this is present profile minimum, does not almost have a kind of packing forms of packing or protective materials.This kind encapsulation typically refers to the wafer stage chip encapsulation.The area of this encapsulation is the same with chip area big.Its encapsulating structure is to be provided with a weld pad on chip body one surface, and the chip body surface beyond weld pad neighboring and the neighboring is provided with protective layer, the thin metal layer that superposes on the protective layer of weld pad surface and neighboring thereof, and the metal level top is planted and is put the tin ball.Because the tin ball is a kind of wettable metal, when the tin ball was placed on the metal level top, metal level can be covered therefore to reflux and can form Cu afterwards by the tin ball
3Sn and Cu
6Sn
5, make and plant the adhesion reduction of ball bond place, stability decreases, the tin ball departs from weld pad easily, influences the serviceability of chip.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of can the raising to plant ball bond place adhesion and create enough material space in case the micron level chip packing structure of tin ball denection weld pad.
The object of the present invention is achieved like this: a kind of micron level chip packing structure; comprise the chip body; chip body one surface is provided with a weld pad; chip body surface beyond weld pad neighboring and the neighboring is provided with protective layer; be characterized in superpose successively on the protective layer of weld pad surface and neighboring thereof titanium layer, copper layer and copper post, copper capital end is planted and is put the tin ball.
Above-mentioned tin ball can be with the local coating of copper post; Also copper post, copper layer and titanium layer all can be coated.
Titanium layer, copper layer and copper post constitute combination.This each layer of combination all has its special effect: titanium layer works to strengthen adhesion and anti-excess diffusion; The copper layer can be plants ball solderability is provided; In addition, the material that the copper post is placed the combination top layer can improve disk constitutes.
It is to plant ball bond place adhesion and create enough material space and plant securely on the combination that places the weld pad top to guarantee the tin ball in order to improve that the present invention adopts unique combination structure.
Micron order Chip Packaging of the present invention need not the rewiring technology but finishes Chip Packaging by planting ball.The theory of micron order encapsulation is that a kind of metal column and tin chou of planting ball bond place performance of can improving closed firmly, makes to plant the ball bond place and have more performance.More performance is meant better shearing force, better anti-expansion force and the ability that prevents intermetallic diffusion phenomena generation.
Description of drawings:
Fig. 1 is embodiments of the invention one structural representations.
Fig. 2 is embodiments of the invention two structural representations.
Fig. 3 is embodiments of the invention three structural representations.
Embodiment:
Embodiment one:
Referring to Fig. 1; the present invention is a kind of micron level chip packing structure; it is to be provided with a weld pad 2 on chip body 1 one surfaces; chip body 1 surface beyond weld pad 2 neighborings and the neighboring is provided with protective layer 3; titanium layer 4, copper layer 5 and copper post 6 successively superpose on the protective layer 3 of weld pad 2 surfaces and neighboring thereof; copper post 6 tops are planted and are put tin ball 7, and the tin ball all places copper capital end.
Copper post 6 thickness should be decided according to the requirement of chip reliability, generally are controlled at 5 μ m～100 μ m.
Embodiment two:
Referring to Fig. 2, the difference of present embodiment and embodiment one only is that tin ball 7 is with copper post 6 local coatings.
Embodiment three:
Referring to Fig. 3, the difference of present embodiment and embodiment one only is that tin ball 7 all coats copper post 6, copper layer 5 and titanium layer 4.
Claims (4)
1, a kind of micron level chip packing structure; comprise chip body (1); chip body (1) one surface is provided with a weld pad (2); chip body (1) surface beyond weld pad (2) neighboring and the neighboring is provided with protective layer (3); it is characterized in that superpose successively on the protective layer (3) of weld pad (2) surface and neighboring thereof titanium layer (4), copper layer (5) and copper post (6), copper post (6) top is planted and is put tin ball (7).
2, a kind of micron level chip packing structure according to claim 1 is characterized in that tin ball (7) is with the local coating of copper post (6).
3, a kind of micron level chip packing structure according to claim 1 is characterized in that tin ball (7) all coats copper post (6), copper layer (5) and titanium layer (4).
4,, it is characterized in that copper post (6) thickness is at 5 μ m～100 μ m according to claim 1,2 or 3 described a kind of micron level chip packing structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100648063A CN100336215C (en) | 2004-09-30 | 2004-09-30 | Micron level chip packing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100648063A CN100336215C (en) | 2004-09-30 | 2004-09-30 | Micron level chip packing structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1610106A CN1610106A (en) | 2005-04-27 |
| CN100336215C true CN100336215C (en) | 2007-09-05 |
Family
ID=34764588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100648063A Expired - Lifetime CN100336215C (en) | 2004-09-30 | 2004-09-30 | Micron level chip packing structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100336215C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320960A (en) * | 2000-04-19 | 2001-11-07 | 卓联科技有限公司 | Interconnection method without lead bosses |
| US6452270B1 (en) * | 2000-10-13 | 2002-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrode |
| CN1392607A (en) * | 2002-06-17 | 2003-01-22 | 威盛电子股份有限公司 | Bottom buffering metal lug structure |
| CN2739796Y (en) * | 2004-09-30 | 2005-11-09 | 江阴长电先进封装有限公司 | Micron-level chip packaging structure |
-
2004
- 2004-09-30 CN CNB2004100648063A patent/CN100336215C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320960A (en) * | 2000-04-19 | 2001-11-07 | 卓联科技有限公司 | Interconnection method without lead bosses |
| US6452270B1 (en) * | 2000-10-13 | 2002-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrode |
| CN1392607A (en) * | 2002-06-17 | 2003-01-22 | 威盛电子股份有限公司 | Bottom buffering metal lug structure |
| CN2739796Y (en) * | 2004-09-30 | 2005-11-09 | 江阴长电先进封装有限公司 | Micron-level chip packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1610106A (en) | 2005-04-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070905 |