CN100336048C - Data transmission standard determination method, bridging chip set and memory adaptation arrangement - Google Patents
Data transmission standard determination method, bridging chip set and memory adaptation arrangement Download PDFInfo
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- CN100336048C CN100336048C CNB2004100930007A CN200410093000A CN100336048C CN 100336048 C CN100336048 C CN 100336048C CN B2004100930007 A CNB2004100930007 A CN B2004100930007A CN 200410093000 A CN200410093000 A CN 200410093000A CN 100336048 C CN100336048 C CN 100336048C
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Abstract
The present invention relates to a method for deciding a data transmission specification, and a matching device of a bridge connection chip group and a memory applied to the method. The matching device comprises a central processing unit in a computer system, a bridge connection chip group, a bus connected between the central processing unit and the bridge connection chip group, and a read only memory which is electrically connected to the bridge connection chip group. The method comprises the following steps that the computer system enters a system harmony state; a first specification datum representing the bus data transmission specification of the bridge connection chip group in the read only memory is read by the bridge connection chip group; the first specification datum and a second specification datum which is transmitted into the bridge connection chip group and represents the bus data transmission specification of the central processing unit are responded by the bridge connection chip group. After the working bus data transmission specification of the bus is decided, the computer system is bounced out the system harmony state, and data transmission is carried out by the working bus data transmission specification.
Description
Technical field
The bridging chip group and the memory adaptation arrangement that the present invention relates to a kind of data transmission standard determination method and be applied thereon relate in particular to a kind of CPU (central processing unit) and bridging chip group data transmission standard determination method between the two that is applied in the computer system.
Background technology
The motherboard of the general computing machine of now being sold on the market, its basic comprising mainly is by CPU (central processing unit) (Central Processing Unit, abbreviation CPU), chipset (chipset) and some peripheral circuits are formed, its CPU (central processing unit) is the core place of whole computing machine, most principal work be handle and control whole computing machine each partly between each other operation, and the computing of carrying out logic; Chipset then is the operation of being responsible between contact CPU (central processing unit) and other interfacing equipment, the combination of chipset also has many different modes, be to serve as the present common practice of most manufacturer on the market at present with north bridge (north bridge) and two chipsets that chip was constituted of south bridge (south bridge), difference according to function, wherein north bridge chips is responsible for the bus (bus) of high speeds all on the contact. host plate, and South Bridge chip then is responsible in the coupled system part more at a slow speed.
Seeing also Fig. 1, is the wiring diagram of each arrangement of components on the motherboard 1.Thus shown in the figure as can be known this motherboard 1 with the framework of single CPU (central processing unit) 10 as system, and form a chipset 2 by a north bridge chips 20 and a South Bridge chip 21, this north bridge chips 20 is by a preposition bus (Front SideBus, FSB) 22 and this CPU (central processing unit) 10 get in touch, generally speaking, the frequency of this preposition bus 22 is just can be used under common the support by this CPU (central processing unit) 10 and this north bridge chips 20, and on this motherboard 1, other has an AGP (Accelerated Graphics Port, AGP) interface 31 is via an AGP bus 311, with a random access memory (Random Access Memory, RAM) 32 via a memory bus 321, is connected to separately on this north bridge chips 20; And in this figure, one perimeter component connects (Peripheral Component Interconnect, PCI) interface 30 is connected with this South Bridge chip 21 via a pci bus 301, the parts more at a slow speed such as an ISA (Industry Standard Architecture) interface 40, an IDE (Integrated Drive Electronics) interface 41, a USB (Universal Serial Bus) interface 42, a keyboard 43 and a mouse 44 in addition that are connected with this South Bridge chip 21 in addition.
Therefore, CPU (central processing unit) 10 and north bridge chips 20 just must be worked in coordination and just can be constituted the system of normal operation, and between the two in this collocation partly, for example preposition bus transfer specification each other is not simultaneously, be the bit width of signal transmission or speed (MHz) when different, just can't make CPU (central processing unit) and north bridge chips produce contact to each other.For example: a certain bridging chip just can only be applicable to the processor of the 64 locative preposition highway widths that certain tame manufacturer produces, and just can't be applicable to the processor of the 32 locative preposition highway widths that another manufacturer of family is produced.Therefore, similarly situation has just caused expending of the bridging chip that needs to produce two kinds of patterns, the restriction of CPU (central processing unit) and bridging chip compatibility and the inconvenience of collocation have also been caused, so, with regard at present, therefrom developing a protocol or the coordination technique of this CPU (central processing unit) and this bridging chip, is unquestionable demand.
See also Fig. 2 (a) to Fig. 2 (d), its for this CPU (central processing unit) 10 and this north bridge chips 20 with the arrange in pairs or groups block diagram of the system that forms of different preposition highway widths, on behalf of available big bit width, bigger square frame do the signal transmission among its figure, and on behalf of maximum, the less square frame that comprises in addition between a dashed region then to do the signal transmission with less bit width; And the transmission of signal wherein some be an address (address) information, another then is data (data) information partly, and with an address bus 221 these address informations of transmission with a data bus 222 these data messages of transmission.In Fig. 2 (a), because this CPU (central processing unit) 10 and this north bridge chips 20 are to do the signal transmission with the width of this data bus 222 of this address bus 221 of 32 and 64, so the system that constitutes can normally move, in like manner, in Fig. 2 (b), though the highway width that this CPU (central processing unit) 10 and this north bridge chips are 20 is less, because it is identical to transmit the bit width of this address information and this data message between the two, therefore still can be compatible.But as can be known described by epimere, if do both of signal transmission with different preposition highway widths, then the system that both formed can't normally move.Promptly be in Fig. 2 (c), this data message that 20 transmission of this north bridge chips are 64 can't allow these data bus 222 transmission with 32 bit widths of this CPU (central processing unit) 10, and this address information is this address bus 221 transmission with 13 bit widths in this CPU (central processing unit) 10, but 20 of this north bridge chips is this address bus 221 transmission with 32 bit widths, therefore under system design commonly used, this CPU (central processing unit) 10 and this north bridge chips 20 just can't normally move each other, similarly situation also obtains identical result in Fig. 2 (d).
Because present action computing (mobile computing) accessories of some individual's peripheries on the market, as: the popularizing of PDA (Personal Digital Assistant) or mobile computer etc., and in order to cater to the more frivolous notion of its volume energy, therefore need littler printed circuit board (PCB) or the less chip of pin count to be arranged in pairs or groups, make the designed CPU (central processing unit) of each tame manufacturer also have pin count more to make to heal few trend, for example adopt with 32 designs, can represent as the block diagram among Fig. 2 (b) as preposition highway width; On the other hand, the application system of some desktops may just must be used the chip of more pin count in order to reach usefulness preferably, as preposition highway width with at least 128 transmission mode but not 64 or 32; But when transmitting with the preposition highway width of difference, have again as above-mentioned problem and produce, therefore Chang Rongyi causes user's inconvenience, and for the manufacturer that makes bridging chip, produce the bridging chip of its different types respectively with regard to the CPU (central processing unit) of different types must be responded, the bridging chip of different types can't be supported the CPU (central processing unit) of different types thus, makes these bridging chips that can't use just become the waste in the production.Yet, in the signal transmission design of system, figure place the greater as highway width, be can the supporting bus width the less person of figure place, thus, how to utilize this characteristic to solve the inconvenience of using as previously mentioned and to avoid unnecessary waste on producing, with effective operation ratio of increase system and compatibility each other, be the fundamental purpose that the present invention develops.
Summary of the invention
For solving above-mentioned purpose, the invention provides a kind of data transmission standard determination method, be applied to a CPU (central processing unit), the bridging chip group in the computer system and and be connected a bus between the two and be electrically connected on a ROM (read-only memory) of this bridging chip group, this method comprises the following step: make this computer system enter a system coordination state; When this computer system enters this system coordination state, this bridging chip group is read be arranged in one first specification data of this ROM (read-only memory), this first specification data is represented the bus data transmission standard of this bridging chip group; And make this bridging chip group respond this first specification data and one second specification data that reaches the bus data transmission standard of representing this CPU (central processing unit) in this bridging chip group, but behind a working bus data transmission standard that determines this bus, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this system coordination state can be the Reset Status of this computer system.
According to above-mentioned conception, data transmission standard determination method of the present invention, but the method that wherein determines the working bus data transmission standard of this bus comprises the following step: make this CPU (central processing unit) according to this second specification data, and one first signal that sends the bus data transmission standard of representing its dominant bit is to this bridging chip group; Make this bridging chip group of this first specification data of response send a secondary signal to this CPU (central processing unit); And this CPU (central processing unit) is judged according to this secondary signal that receives, and this bridging chip group is judged according to this first signal that receives, but and after determining this working bus data transmission standard of this bus, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this bridging chip group can include a north bridge chips and a South Bridge chip is formed, this north bridge chips is connected as electric signal with this CPU (central processing unit) via this bus, and this South Bridge chip to be electric signal be connected in this ROM (read-only memory), and also make electric signal between this north bridge chips and this South Bridge chip and connect.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this north bridge chips can support and this CPU (central processing unit) between one first bus data transmission standard and one second bus data transmission standard, and this first specification data is to represent an appointed bus data transmission standard in this first bus data transmission standard and this second bus data transmission standard.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this first specification data store recording is in this ROM (read-only memory), after this computer system enters this system coordination state, send one by this South Bridge chip to this ROM (read-only memory) by this north bridge chips and read signal, to read this first specification data of the bus data transmission standard of representing this north bridge chips, make this north bridge chips be determined the bus data transmission standard of north bridge chips, and send this secondary signal to this CPU (central processing unit) according to this.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein can make amendment, make this north bridge chips can respond this first specification data and send this secondary signal to this CPU (central processing unit) via this first specification data to the bus data transmission standard of representing this north bridge chips in this ROM (read-only memory).
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this second specification data represent this CPU (central processing unit) via this bus can transmit and receive the bus data transmission standard of dominant bit, and send this first signal according to this.
According to above-mentioned conception, data transmission standard determination method of the present invention, but decision that wherein should working bus data transmission standard, for according to the bus data transmission standard of the bus data transmission standard of this first signal representative and this secondary signal representative between the two the bus data transmission standard that can support mutually choose.
According to above-mentioned conception, data transmission standard determination method of the present invention, but wherein determine at this working bus data transmission standard, and jump out after this system coordination state, this bridging chip group can be sent a CPU (central processing unit) reset signal to this CPU (central processing unit) via this bus, notifying this CPU (central processing unit) to move, but make this CPU (central processing unit) and this bridging chip group carry out between the two data transmission with this working bus data transmission standard.
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this bus data transmission standard can be highway width, and when responding this bus data transmission standard and being highway width, but but should working bus data transmission standard be a working bus width
According to above-mentioned conception, data transmission standard determination method of the present invention, wherein this bus data transmission standard can be bus speed, and when responding this bus data transmission standard and being bus speed, but but should working bus data transmission standard be a working bus speed.
The present invention provides a kind of bridging chip group and memory adaptation arrangement again, be applied in the computer system to send a CPU (central processing unit) of one first signal and be connected a bus between this adaptation arrangement and the CPU (central processing unit) by one first pin, this device comprises: a ROM (read-only memory), store recording one first specification data, this data represented bus data transmission standard; An and bridging chip group, be electrically connected on this ROM (read-only memory), this bridging chip group can respond this first specification data that this ROM (read-only memory) provides, by being located on this bridging chip group and being electrically connected on one second pin of this CPU (central processing unit), send a secondary signal to this CPU (central processing unit), this bridging chip group also can receive this first signal that this CPU (central processing unit) is sent, and can judge, but to determine a working bus data transmission standard of this bus to this first signal.
According to above-mentioned conception, bridging chip group of the present invention and memory adaptation arrangement, wherein this bridging chip group comprises: a north bridge chips, its first end is electrically connected on this first pin via this bus, and its second end is electrically connected on this second pin, can support and this CPU (central processing unit) between one first bus data transmission standard and one second bus data transmission standard, and this first specification data is to represent an appointed bus data transmission standard in this first bus data transmission standard and this second bus data transmission standard; And a South Bridge chip, its first end is electrically connected on this north bridge chips, and its second end is electrically connected on this ROM (read-only memory), and what can receive that this north bridge chips sends one reads signal, to read this first specification data in this ROM (read-only memory).
According to above-mentioned conception, bridging chip group of the present invention and memory adaptation arrangement, wherein this north bridge chips can read signal and read this first specification data by this, make this north bridge chips in this bridging chip group be determined bus data transmission standard, and send this secondary signal to this CPU (central processing unit) according to this.
According to above-mentioned conception, bridging chip group of the present invention and memory adaptation arrangement, wherein can make amendment, make this north bridge chips can respond this first specification data and send this secondary signal to this CPU (central processing unit) via this first specification data to the bus data transmission standard of representing this north bridge chips in this ROM (read-only memory).
According to above-mentioned conception, bridging chip group of the present invention and memory adaptation arrangement, wherein this first signal is represented the bus data transmission standard of this CPU (central processing unit) via dominant bit that this bus can transmit and receive.
According to above-mentioned conception, bridging chip group of the present invention and memory adaptation arrangement, but decision that wherein should working bus data transmission standard, for according to the bus data transmission standard of the bus data transmission standard of this first signal representative and this secondary signal representative between the two the bus data transmission standard that can support mutually choose.
The present invention must obtain a more deep understanding by following accompanying drawing and detailed description.
Description of drawings
Fig. 1 is the wiring diagram of each arrangement of components on the motherboard.
Fig. 2 (a) is to the block diagram of the system that Fig. 2 (d) forms with the collocation of different bus width for CPU (central processing unit) and north bridge chips.
Fig. 3 is applied in CPU (central processing unit) in the computer system and the configuration schematic diagram between bridging chip for the present invention.
Fig. 4 is the block diagram of preferred embodiment of the present invention.
Fig. 5 (a) to Fig. 5 (d) be in this preferred embodiment, carry out the signal that the collocation of different bus data transmission standard forms with the present invention and produce sequential chart.
Fig. 6 (a) and Fig. 6 (b) are in this preferred embodiment, and CPU (central processing unit) is carried out the block diagram that different bus data transmission standards disposes with the bridging chip group with the inventive method.
Fig. 7 is the process flow diagram of preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
1 motherboard, 10 CPU (central processing unit)
20 north bridge chips, 21 South Bridge chips
2 chipsets, 22 preposition buses
221 address buss, 222 data buss
30 perimeter component connecting interfaces, 301 pci buss
31 AGP interfaces, 311 AGP buses
32 random access memory, 321 memory buss
40 ISA interfaces, 41 ide interfaces
42 USB interface, 43 keyboards
44 mouses, 50 CPU (central processing unit)
501 first pins, 51 bridging chip groups
512 north bridge chips, 513 South Bridge chips
511 second pins, 52 buses
The HAm first signal HAn secondary signal
53 ROM (read-only memory) DWNCMD read signal
The RDDATA data reception signal
CPURESET CPU (central processing unit) reset signal
The PCIRESET perimeter component connects reset signal
Embodiment
See also Fig. 3, it is a CPU (central processing unit) 50 and a bridging chip group 51 and the configuration schematic diagram that is connected a bus 52 between the two that is applied in the computer system.In preferred embodiment of the present invention, this CPU (central processing unit) 50 and this bridging chip group 51 are described in prior art, for being arranged on the motherboard (not shown), and this bridging chip group 51 just can comprise the north bridge chips in the described chipset of prior art etc., by as can be known shown in Figure 3, this CPU (central processing unit) 50 can be carried out the transmission and the reception of signal by this bus 52 that all is electrically connected each other between the two with this bridging chip group 51.Because this CPU (central processing unit) 50 designs with the chip structure that this bridging chip group 51 is an integrated circuit, so promptly be provided with the interface of many pins to send signal or signal is imported into as it in its appearance.
By the explanation of prior art as can be known, arrange in pairs or groups in this CPU (central processing unit) 50 and this bridging chip group 51 this bus 52 therebetween, the highway width that can transmit dominant bit when both is not simultaneously, promptly can make dominant bit that signal transmits when different, just can't make this CPU (central processing unit) 50 and this bridging chip group 51 produce contact to each other; For instance, a side transmits signal as if the width with 64, and the opposing party does the signal reception with 32 width, and then the data of this transmission can only receive half, and cause the loss of an other half data.But, when if two sides can both utilize the figure place smaller's that figure place the greater of highway width can the supporting bus width characteristic, then this CPU (central processing unit) 50 just can be coordinated out an identical highway width transmitting with this bridging chip group 51, thereby just can solve the above problems.
See also Fig. 4, it is the block diagram of preferred embodiment of the present invention.At first, make this computer system enter a system coordination state, it for example is a system reset state, then responding this computer system enters when this system coordination state, this bridging chip group 51 is read be electrically connected on one first specification data that stores in the ROM (read-only memory) 53 of this bridging chip group 51, and this first specification data is being represented the bus data transmission standard of this bridging chip group 51, at last, make this bridging chip group 51 these first specification data of response and one second specification data that reaches the bus data transmission standard of representing this CPU (central processing unit) 50 in this bridging chip group 51, but behind a working bus data transmission standard that determines this bus 52, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.And in this preferred embodiment, this second specification data is representing this CPU (central processing unit) 50 via 52 bus data transmission standards that can transmit and receive dominant bit of this bus, but the decision of therefore being somebody's turn to do the working bus data transmission standard is to make this CPU (central processing unit) 50 according to this second specification data on the one hand, the one first signal HAm that sends the bus data transmission standard of representing these CPU (central processing unit) 50 dominant bits is to this bridging chip group 51, and this bridging chip group 51 that responds this first specification data is on the other hand also sent a secondary signal HAn to this CPU (central processing unit) 50, make this CPU (central processing unit) 50 to judge according to this first signal HAm that receives according to this secondary signal HAn that receives and this bridging chip group 51, thereby choose this first signal HAm and this secondary signal HAn between the two the bus data transmission standard that can support mutually think representative, but and then after determining this working bus data transmission standard of this bus 52, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.
By as can be known shown in Figure 4, this CPU (central processing unit) 50 is to send this first signal HAm to this bridging chip group 51 by one first pin 501 provided thereon, and this bridging chip group 51 is electrically connected on this ROM (read-only memory) 53, wherein these ROM (read-only memory) 53 store recordings this first specification data (not shown) of representing a bus data transmission standard, therefore this bridging chip group 51 just can respond this first specification data that this ROM (read-only memory) 53 is provided, and then, send this secondary signal HAn to this CPU (central processing unit) 50 by provided thereon and be electrically connected on one second pin 511 of this CPU (central processing unit) 50.This first signal HAm is via inventive concept of the present invention, send by wherein pin that this bus 52 produces in the pin group of getting in touch for selecting this CPU (central processing unit) 50 and this bridging chip group 51 for use, in this preferred embodiment, promptly be to use this first pin 501 to do its way, in like manner, also be like this at this secondary signal HAn on the other hand.
Again by shown in Figure 4, this bridging chip group 51 can include a north bridge chips 512 and a South Bridge chip 513 is formed, wherein first end of this north bridge chips 512 is electrically connected on this first pin 501 on this CPU (central processing unit) 50 via this bus 52, and its second end is electrically connected on this second pin 511, this north bridge chips 512 be for can supporting this bus data transmission standard of 50 of multiple and this CPU (central processing unit), and this first specification data is to represent an appointed bus data transmission standard in the multiple bus data transmission standard of this north bridge chips 512; First end of this South Bridge chip 513 is electrically connected on this north bridge chips 512, and its second end is electrically connected on this ROM (read-only memory) 53.In this preferred embodiment, after this computer system enters this system coordination state, can send one by this South Bridge chip 513 to this ROM (read-only memory) 53 by this north bridge chips 512 and read signal DWNCMD, be arranged in this first specification data that this ROM (read-only memory) 53 is represented the bus data transmission standard of this north bridge chips 512 to read, make this north bridge chips 512 be determined bus data transmission standard by a data reception signal RDDATA, and send this secondary signal HAn to this CPU (central processing unit) 50 according to this.But determined and in the end ought be somebody's turn to do the working bus data transmission standard, and jump out after this system coordination state, this bridging chip group 51 can be sent a CPU (central processing unit) reset signal CPURESET to this CPU (central processing unit) 50 via this bus 52, notifying this CPU (central processing unit) 50 to move, but make this CPU (central processing unit) 50 and this bridging chip group 51 carry out between the two data transmission with this working bus data transmission standard.
In this preferred embodiment, bus data transmission standard can be decided to be highway width, and when responding this bus data transmission standard and being highway width, but but what obtain should working bus data transmission standard just be a working bus width; In like manner, bus data transmission standard can be decided to be bus speed, and when responding this bus data transmission standard and being bus speed, but but what obtain should working bus data transmission standard just be a working bus speed.From the above, before the also inreal transmission data of this CPU (central processing unit) 50 and this bridging chip group 51, the function of this first signal HAm and this secondary signal HAn be inform the other side itself data transmission standard why, so after switching signal was intact, either party just knew compatibility each other; For instance, if itself can transmit 64 highway width, and received the other side's signal is can only transmit 32 the time, can support the characteristic of the less person's of figure place highway width according to the highway width of figure place the greater, promptly coordinate 32 that each other highway width will be all with the less side in position between the two and move.In addition, because this north bridge chips in the present invention 512 is for supporting this bus data transmission standard of 50 of multiple and this CPU (central processing unit), for example can support simultaneously than 32 bit data transmission standards of small dimension and 64 bit data transmission standards of big specification etc., and on known technology, the program that we can utilize default is at an easy rate made amendment via this first specification data to the bus data transmission standard of representing this north bridge chips 512 in this ROM (read-only memory) 53, make this north bridge chips 512 can respond this first specification data and send this secondary signal HAn to this CPU (central processing unit) 50, just can be combined into the configuration that the user needs, so, production firm just needn't be in order to respond the market supply and demand of known CPU (central processing unit) of collocation different size, develop different production lines to make known bridging chip group and increase into this locality, just can solve the waste unnecessary on production and the stock and the problems such as inconvenience of collocation; Simultaneously, also can comply with method and apparatus of the present invention, by this CPU (central processing unit) 50 and this bridging chip group 51 signal exchange between the two, and can avoid described in prior art, producing situation about can't normally move because of compatible each other problem, therefore, successfully reached the fundamental purpose of the present invention's development.
See also Fig. 5 (a) to Fig. 5 (d), for this CPU (central processing unit) 50 and this bridging chip group 51 in this preferred embodiment, carry out the signal that the collocation of different bus data transmission standard forms with the present invention and produce sequential chart.In this preferred embodiment, we are by a perimeter component connecting interface (not shown), send a perimeter component and connect reset signal PCIRESET, so that this computer system enters this system coordination state, because this first signal HAm and the coding way of output of this secondary signal HAn in this computer system can be the high level voltage of the big highway width (or bus speed) of representative, or represent the low level voltage of less highway width (or bus speed), and definition specification the greater is represented high level voltage in this preferred embodiment of the present invention, and the specification smaller just represents low level voltage.By shown in Fig. 5 (a) to (d) as can be known, if wherein this first signal HAm and this secondary signal HAn are rendered as the constant straight line of high level, then represented its bus data transmission standard bigger, otherwise, if be rendered as the section that a level descends, then represented its bus data transmission standard less, therefore in Fig. 5 (a) to (d), present four kinds of possible collocation, at Fig. 5 (a) to Fig. 5 (c), determine this CPU (central processing unit) 50 and do the transmission of signal each other with bus data transmission standard smaller's low level voltage with this bridging chip group 51, and in Fig. 5 (d), then determine with the high level voltage of bus data transmission standard the greater and do the transmission of signal each other.But no matter but why be somebody's turn to do the working bus data transmission standard at last, this CPU (central processing unit) 50 all can be carried out the processing of data with original usefulness itself separately with this bridging chip group 51 at last.
By Fig. 5 (a) to shown in Fig. 5 (d) as can be known, to connect reset signal PCIRESET be to send to enter this system coordination state in 1 o'clock at the time section to this perimeter component of definition in this preferred embodiment, and it is 2 o'clock at the time section, this north bridge chips 512 just can by this South Bridge chip 513 to this ROM (read-only memory) 53 send this read signal DWNCMD (by these figure as can be known this signal also comprise a DWNWR and a DWNADDR two partly), be arranged in this first specification data that this ROM (read-only memory) 53 is represented the bus data transmission standard of this north bridge chips 512 to read, it is 5 o'clock then at the time section, this South Bridge chip 513 can make this north bridge chips 512 be determined bus data transmission standard by this data reception signal RDDATA, wherein this first specification data is just being write down in the k position (being the RDDATAk shown in these figure) on this data reception signal RDDATA, 512 appointed these bus data transmission standards of this north bridge chips have been indicated, and similarly, RDDATAk is if being shown as high level voltage then represents and may operate at bigger bus data transmission standard, otherwise then is represented as and operates in less bus data transmission standard if be shown as low level voltage.At the time section is 7 o'clock, this CPU (central processing unit) 50 and this bridging chip group 51 are sent this first signal HAm and this secondary signal HAn simultaneously to notify the other side, but and after determining this working bus data transmission standard in above-mentioned mode, the time section of being defined in is 8 o'clock, this bridging chip group 51 is just sent this CPU (central processing unit) reset signal CPURESET to this CPU (central processing unit) 50, can move to notify this CPU (central processing unit) 50.The coding way of output in this computer system also can change the low level voltage that is of the big highway width (or bus speed) of representative into as for this first signal HAm and this secondary signal HAn, and represent less highway width (or bus speed) is high level voltage, or when the classification of highway width exceeds two kinds, just available serial or voltage level signal arranged side by side are represented, for example, the low highway width of 00 representative, highway width in 01 representative, and the high highway width of 10 representatives, but these variations should belong to common technological means, so do not repeat them here.
See also Fig. 6 (a) and Fig. 6 (b), it is in this preferred embodiment, and this CPU (central processing unit) 50 is carried out the block diagram that different bus data transmission standards disposes with this bridging chip group 51 with method of the present invention.This north bridge chips 512 in Fig. 6 (a) and Fig. 6 (b) in this bridging chip group 51, be all the design of the bus data transmission standard that can support 50 of multiple and this CPU (central processing unit), with this preferred embodiment for instance, promptly be to represent the bus data transmission standard smaller with 32, and represent bus data transmission standard the greater with 64, therefore this north bridge chips 512 in Fig. 6 (a) and Fig. 6 (b) in this example, just can support simultaneously 32 with 64 bus data transmission standard; And only being store recording this first specification data (not shown) in this ROM (read-only memory) 53, Fig. 6 (a) and Fig. 6 (b) difference representing different bus data transmission standards, represent bigger 64 of specification in this first specification data of Fig. 6 (a), therefore its north bridge chips 512 is just designated operates on 64, and represent less 32 of specification in this first specification data of Fig. 6 (b), therefore its north bridge chips 512 is just designated operates on 32, so, known bridging chip group via described different size before needs make with the known CPU (central processing unit) of arranging in pairs or groups with different production lines, in this preferred embodiment, just develop into multiple bus data transmission standard is incorporated on the same assembly, and only need this first specification data of the bus data transmission standard of representing this north bridge chips 512 in this ROM (read-only memory) 53 is made amendment, just can obtain the configuration that the user needs, the present invention's invention can reduce the expense of cost and the problem of inconvenience really as can be known, has successfully reached development purpose of the present invention.
See also Fig. 7, the process flow diagram of its preferred embodiment of the present invention.At first, computer system enters the system coordination state, secondly, bridging chip group 51 reads and responds and is arranged in first specification data that ROM (read-only memory) 53 is represented the bus data transmission standard of bridging chip group 51, and send secondary signal HAn to CPU (central processing unit) 50, and CPU (central processing unit) 50 is according to second specification data, and the first signal HAm that sends the bus data transmission standard of representing CPU (central processing unit) 50 dominant bits is to bridging chip group 51, then, CPU (central processing unit) 50 is judged according to the first signal HAm that receives according to secondary signal HAn that receives and bridging chip group 51, but behind the working bus data transmission standard that determines bus 52, but jump out the system coordination state and carry out data transmission with the working bus data transmission standard, at last, bridging chip group 51 can be sent CPU (central processing unit) reset signal CPURESET to CPU (central processing unit) 50 via bus 52, can move with notice CPU (central processing unit) 50.
In sum, use the technology of the present invention just can be when making the bridging chip group, reduce even avoid responding the CPU (central processing unit) of different size and the incompatible probability of producing the bridging chip group of different size respectively, thus, the bridging chip group of a certain specification just can be supported the CPU (central processing unit) of different size, and then can solve the described inconvenience in the use of prior art and produce upward unnecessary waste, and increase effective operation ratio of system and compatibility each other, therefore reach development fundamental purpose of the present invention really.Yet the present invention can be appointed in the technician by ability and executes the craftsman and think and do some modifications.
Claims (11)
1. data transmission standard determination method is applied to a CPU (central processing unit), the bridging chip group in the computer system and and be connected a bus between the two and is electrically connected on a ROM (read-only memory) of this bridging chip group, and this method comprises the following step:
This computer system enters a system coordination state;
When this computer system entered this system coordination state, this bridging chip group read one first specification data that is arranged in this ROM (read-only memory), and this first specification data is represented the bus data transmission standard of this bridging chip group; And
This bridging chip group responds this first specification data and one second specification data that reaches the bus data transmission standard of representing this CPU (central processing unit) in this bridging chip group, but behind a working bus data transmission standard that determines this bus, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.
2. data transmission standard determination method according to claim 1, wherein this system coordination state Reset Status that is this computer system.
3. data transmission standard determination method according to claim 1, but the wherein said method that determines the working bus data transmission standard of this bus comprises the following step:
This CPU (central processing unit) is according to this second specification data, and one first signal that sends the bus data transmission standard of representing its dominant bit is to this bridging chip group;
This bridging chip group that responds this first specification data is sent a secondary signal to this CPU (central processing unit); And
This CPU (central processing unit) is judged according to this secondary signal that receives, and this bridging chip group is judged according to this first signal that receives, but and after determining this working bus data transmission standard of this bus, but jump out this system coordination state and carry out data transmission with this working bus data transmission standard.
4. data transmission standard determination method according to claim 3, wherein this bridging chip group includes a north bridge chips and a South Bridge chip, this north bridge chips is connected as electric signal with this CPU (central processing unit) via this bus, and this South Bridge chip electric signal is connected in this ROM (read-only memory), and also making electric signal between this north bridge chips and this South Bridge chip connects, one first bus data transmission standard and one second bus data transmission standard between this north bridge chips support and this CPU (central processing unit), and this first specification data is to represent an appointed bus data transmission standard in this first bus data transmission standard and this second bus data transmission standard, and this first specification data store recording is in this ROM (read-only memory), after this computer system enters this system coordination state, send one by this South Bridge chip to this ROM (read-only memory) by this north bridge chips and read signal, to read this first specification data of the bus data transmission standard of representing this north bridge chips, this north bridge chips is determined the bus data transmission standard of north bridge chips, and send this secondary signal to this CPU (central processing unit) according to this, and make amendment via this first specification data to the bus data transmission standard of representing this north bridge chips in this ROM (read-only memory), this north bridge chips responds this first specification data and sends this secondary signal to this CPU (central processing unit).
5. data transmission standard determination method according to claim 3, wherein this second specification data represent this CPU (central processing unit) via this bus can transmit and receive the bus data transmission standard of dominant bit, and send this first signal according to this, but and decision that should working bus data transmission standard, for according to the bus data transmission standard of the bus data transmission standard of this first signal representative and this secondary signal representative between the two the bus data transmission standard that can support mutually choose.
6. data transmission standard determination method according to claim 3, but wherein determine at this working bus data transmission standard, and jump out after this system coordination state, this bridging chip group is sent a CPU (central processing unit) reset signal via this bus to this CPU (central processing unit), notify this CPU (central processing unit) to move, but this CPU (central processing unit) and this bridging chip group are carried out between the two data transmission with this working bus data transmission standard.
7. data transmission standard determination method according to claim 1, wherein this bus data transmission standard is a highway width, and when responding this bus data transmission standard and being highway width, but but should the working bus data transmission standard be a working bus width, and this bus data transmission standard also can be bus speed, and when responding this bus data transmission standard and being bus speed, but but should working bus data transmission standard be a working bus speed.
8. bridging chip group and memory adaptation arrangement are applied in the computer system to send a CPU (central processing unit) of one first signal by one first pin and are connected a bus between this adaptation arrangement and the CPU (central processing unit), and this device comprises:
One ROM (read-only memory), store recording one first specification data, this data represented bus data transmission standard; And
One bridging chip group, be electrically connected on this ROM (read-only memory), this bridging chip group responds this first specification data that this ROM (read-only memory) provides, by being located on this bridging chip group and being electrically connected on one second pin of this CPU (central processing unit), send a secondary signal to this CPU (central processing unit), this bridging chip group also can receive this first signal that this CPU (central processing unit) is sent, and can judge this first signal, but to determine a working bus data transmission standard of this bus.
9. bridging chip group according to claim 8 and memory adaptation arrangement, wherein this bridging chip group comprises:
One north bridge chips, its first end is electrically connected on this first pin via this bus, and its second end is electrically connected on this second pin, one first bus data transmission standard and one second bus data transmission standard between support and this CPU (central processing unit), and this first specification data is to represent an appointed bus data transmission standard in this first bus data transmission standard and this second bus data transmission standard; And
One South Bridge chip, its first end is electrically connected on this north bridge chips, and its second end is electrically connected on this ROM (read-only memory), and what can receive that this north bridge chips sends one reads signal, to read this first specification data in this ROM (read-only memory).
10. bridging chip group according to claim 9 and memory adaptation arrangement, wherein this north bridge chips reads signal and reads this first specification data by this, make this north bridge chips in this bridging chip group be determined bus data transmission standard, and send this secondary signal to this CPU (central processing unit) according to this, and can make amendment via this first specification data to the bus data transmission standard of representing this north bridge chips in this ROM (read-only memory), make this north bridge chips can respond this first specification data and send this secondary signal to this CPU (central processing unit).
11. bridging chip group according to claim 8 and memory adaptation arrangement, wherein this first signal represent this CPU (central processing unit) via this bus can transmit and receive the bus data transmission standard of dominant bit, but and decision that should working bus data transmission standard, for according to the bus data transmission standard of the bus data transmission standard of this first signal representative and this secondary signal representative between the two the bus data transmission standard that can support mutually choose.
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| US20040073733A1 (en) * | 1999-07-29 | 2004-04-15 | Laberge Paul A. | Bus arbitration |
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| US5991833A (en) * | 1998-03-13 | 1999-11-23 | Compaq Computer Corporation | Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions |
| US6295568B1 (en) * | 1998-04-06 | 2001-09-25 | International Business Machines Corporation | Method and system for supporting multiple local buses operating at different frequencies |
| US20040073733A1 (en) * | 1999-07-29 | 2004-04-15 | Laberge Paul A. | Bus arbitration |
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| CN1604064A (en) | 2005-04-06 |
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