CH710661A2 - DC / DC converter and method for controlling a soft switching bidirectional DC / DC converter. - Google Patents

Abstract

A DC / DC converter according to the invention in the form of a step-down converter, step-up converter or inverter has a converter inductance (L) and an inductance short-circuit switch (Q3, Q4, D3, D4) which is connected in parallel to the converter inductance (L). The inductance short-circuit switch (Q3, Q4, D3, D4) can be controlled separately according to current directions. In a method according to the invention for operating the DC-DC converter, a time interval during which the inductance short-circuiting switch (Q3, Q4, D3, D4) is switched on varies by one period or one switching frequency with which the DC / DC converter operates is going to keep, at least approximately constant. The switching operations are controlled in such a way that soft switching processes ("soft switching") result for all switching elements (Q1, Q2, Q3, Q4).

Description

State of the art

The construction volume of DC / DC converters, e.g. Buck converters is largely due to the passive components, i.e. determined by the output inductance and the output capacitance. The task of the output filter is the low-pass filtering of the voltage generated by the switching stage of the converter; correspondingly, at a higher switching frequency, the kink frequency of the filter can be increased and thus the size of the filter elements can be reduced. However, the increase in the switching frequency is limited by the switching losses that increase with the frequency. At high clock frequencies, soft-switching converters are therefore preferably used, which avoid the simultaneous occurrence of current and voltage of a switching element, i.e. Before switching on, reduce the voltage across the switch to zero (zero voltage turn-on) or when switching off, use the parasitic capacitance of the switching elements as a switch-off relief capacitance so that the voltage rise across the switch is delayed and the current in the switching element is interrupted before the voltage becomes significant Values reached (zero voltage turn-off). Overall, this mode of operation, which is characterized by negligible switching losses, is known as Zero Voltage Switching (ZVS).

ZVS is advantageous through appropriate control of the converter basic structure, i. reached without auxiliary switch. Such an operation is e.g. in the Swiss patent application CH 0 480/10 and the Swiss patent CH 701 856 (application number CH 1 451/09) and is characterized by a triangular course of the current in the buck converter inductance, the current at the end of each switching period, i.e. has a slightly negative current at the end of the switch-off interval of the buck converter switch. The setting of this current is made possible by a switch (freewheeling switch) in antiparallel to the freewheeling diode, which is also switched through in the conduction interval of the diode and thus enables current to be carried with a low forward voltage drop or a reduction in conduction losses (synchronous rectification). Due to the negative current, the parasitic capacitance of the freewheeling switch or freewheeling diode is charged after switching off, or the parasitic capacitance of the buck converter switch (e.g. a power MOSFET) is discharged and thus finally zero voltage at the buck converter switch, with which the parasitic internal diode of the power -MOSFETs becomes conductive and the voltage clamps to zero, so that the buck converter or the power MOSFET at voltage zero, ie can be switched on without losses and the current in the buck converter inductance rises again.

However, the triangular shape of the current in the buck converter inductance causes a relatively high variation in the switching frequency over the operating range, since the steepness of the rising and falling edges of the current are defined by the difference between the input and output voltage and the output voltage , however, the peak value of the current must always be set approximately equal to twice the output current mean value, which results in a switching frequency variation determined directly by the output power. In particular, with a low output power, small current peaks and thus very high switching frequencies occur due to the fixed current slopes. On the other hand, the switching frequency drops to low values at high powers.

To reduce the switching frequency variation, it is known to arrange a short-circuit switch above the buck converter inductance which allows the slightly negative charge reversal to be maintained at the end of the switch-off interval for a longer period of time and so limit the increase in the switching frequency at low output powers. The switch, also known as a clamp switch or inductance short-circuit switch, is switched through at the same time as the freewheeling switch is switched off, thus charging the parasitic capacitance of the freewheeling switch and the freewheeling diode hard to the output voltage or hard discharging the parasitic capacitance of the clamp switch. The negative current of the output inductance then circulates via the clamp switch, voltage is zero across the inductance. This clamp interval ends when the clamp switch is switched off. The current, which is still negative, then charges the capacitance of the freewheeling switch and freewheeling diode and the clamp switch or discharges the capacitance of the buck converter switch in the form of an oscillation until voltage zero occurs across the buck converter switch and the switch can be switched on again under voltage zero as described above . Overall, by increasing the length of the clamp interval, the switching frequency can be reduced and thus a lower switching frequency can be ensured even with low output powers. However, the peak value of the current in the inductance increases because the local mean value of the current in the buck converter inductance must be equal to the output current. It should be noted that the clamp switch only has to be suitable for negative current flow, which is not referred to in the literature.

Due to the freewheeling switch, the buck converter described above can also be used with an inverse power flow direction, i.e. operated with a negative mean current value in the inductance. The freewheeling switch and the step-down converter switch then exchange their function, and there is a total step-up converter operation, since power is now being supplied from the low output voltage to the higher input voltage. Overall, there is a bidirectional DC / DC converter. The clamp switch must therefore carry currents in both directions and be able to block voltages in both directions, i.e. a four-quadrant switch is to be provided. If this switch is activated in the form described above, i. If both transistors are switched through at the same time when the freewheeling switch is switched off, as mentioned above, the parasitic capacitance of the clamp switch is immediately discharged and the parasitic capacitance of the buck converter is suddenly discharged from the full input voltage to the difference between the input and output voltage, as well as sudden charging the output capacitance of the freewheeling switch to the output voltage. This causes switch losses and thus limits the overall increase in switching frequency mentioned at the beginning, or causes electromagnetic interference.

[0006] The object of the invention is therefore to create a DC / DC converter and a method for controlling it, so that soft switching of all switching elements is made possible for buck and boost converter operation.

The DC / DC converter can be implemented in the form of a step-down converter, step-up converter or inverse converter, and has a converter inductance and an inductance short-circuit switch, which is connected in parallel to the converter inductance, and which can be controlled separately according to current directions.

"Separated by current directions" means, for example, that there are switches as part of the inductance short-circuit switch with which it is possible to selectively and independently control whether a current can flow through the switch in one direction or in the opposite direction.

In the method for operating the DC-DC converter, a time interval during which the inductance short-circuit switch (Q3, Q4, D3, D4) is switched on, varies by a period or a switching frequency with which the DC / DC converter is operated to hold at least approximately constant or a predetermined, for example adapt time-dependent setpoint curve. The switching processes are controlled in such a way that soft switching processes result in each case.

A sequence of switching operations can be determined and specified, the switching times determined or the switching operations being triggered when the method is carried out based on measurements of the current through the converter inductance, in particular zero crossings of the same.

In embodiments of the invention, the following aspects are implemented: The clamp switch or inductance short-circuit switch is implemented by a four-quadrant switch that can be controlled separately according to current directions (monolithic bidirectional switch with 2 gates, anti-series connection of two unidirectional switches with anti-parallel freewheeling diodes, anti-parallel connection of semiconductors with reverse blocking characteristics, e.g. reverse blocking IGBTs) The inductance short-circuit switch can be used for bidirectional step-down converter (buck), step-up converter (boost) and inverse converter (buck-boost) converter. In all of these variants, the input terminal, output terminal and reference voltage rail have mutually embossed, e.g. voltages supported by capacitors. In buck converter operation, the input voltage is applied between the input terminal and the reference voltage rail and the output voltage occurs between the output terminal and the reference voltage rail. If the power flow direction of the buck converter is reversed, i.e. if power is fed back from the output of the step-down converter to the input, step-up converter operation is present in the sense of voltage translation. Similarly, a step-up converter with power flow opposite to the voltage conversion direction can be seen as a step-down converter. For inverse converter operation, the input voltage is applied between the buck converter input terminal (positive pole) and buck converter output terminal (negative pole) and the output voltage is tapped between the reference voltage rail (negative pole) and the output terminal of the buck converter (positive pole), so the output terminal provides the input and output terminal The output circuit of the inverse converter represents a common circuit point. Correspondingly, backup capacitors are typically arranged between the input and output terminal and the reference voltage rail and the output terminal. A simplified inductance short-circuit switch, formed from the series connection of a diode and a switch, is sufficient for unidirectional switching. In this case too, the inductance short-circuit switch can be controlled separately according to current directions. The circuit is modified to an AC / DC converter (for example for PFC, Power Factor Correction) or an AC / AC converter. An inductance short-circuit switch can also be used in these cases. In particular at full load, it can only be operated in the vicinity of the zero crossings with an increasing activation interval as the load decreases. Operation of the inductance short-circuit switch with DC / DC converters only in the partial load range, or with DC / DC converters with time-varying input and / or output voltage only in those areas where the switching frequency would reach impermissibly high values. Selection of the width of a rest interval with a negative auxiliary current through the inductance short-circuit switch in such a way that only a relatively small switching frequency variation occurs over a certain load range or an input and output voltage range, or a total period of the repeatedly performed switching operations remains as constant as possible. One of the two switches of the inductance short-circuit switch can remain switched on for synchronous rectification of the inductance short-circuit switch. Alternatively, switching on can be omitted in order to simplify the control, or one of the two switches of the inductance short-circuit switch can be omitted if the power flow is only unidirectional. In this case, the anti-parallel diode to the other of the two switches can also be omitted.

In the following, the subject matter of the invention is explained in more detail on the basis of preferred exemplary embodiments which are illustrated in the accompanying drawings. 1 shows an embodiment of a circuit according to the invention; 2 shows signal profiles according to a control method for operating the circuit; and FIG. 3 shows signal curves according to a modified control method.

The processes and principles described below using a buck converter can be transferred in the same way to other DC / DC converters such as boost converters and inverse converters as well as AC / DC converters or AC / AC converters with inductance short-circuit switches. In some cases, the same sequences of switching operations can be implemented, in other cases analogous considerations lead to other sequences in a manner immediately apparent to a person skilled in the art.

The circuit structure of a bidirectional DC / DC converter with buck converter characteristic is shown in FIG. For the further description, a power flow direction from the input with voltage Upn = U1 to the output with voltage U n = U2 U1 is assumed and the system is accordingly referred to as a buck converter. For reverse power flow direction (which can occur due to the bidirectionality of the converter), i.e. In the case of power recovery or power delivery from the step-down converter output n to the step-down converter input pn, step-up converter operation is actually present, taking into account the voltage translation and power flow direction. In the sense of a simpler description, however, it is not discussed in more detail, but always only speaks of a step-down converter with an inverse power flow direction or of energy recovery of the step-down converter when step-up converter operation is present.

The circuit has an input capacitance C1, a first and a second switch Q1, Q2 of the controller, with a first and a second freewheeling diode D1, D2, a converter inductance L, in this case also called buck converter inductance, and an output capacitance C2. The buck converter inductance L is connected to a circuit point x between the first and second switches Q1, Q2.

The first switch Q1 is connected between the node x and an input terminal p. The second switch Q2 is connected between the node x and a reference voltage rail n. The input capacitance C1 is connected between the input terminal p and the reference voltage rail n. Instead of the input capacitance C1, another element that acts as a voltage source can also be present. The converter inductance L is connected between the node x and an output terminal. The output capacitance C2 is connected between the output terminal and the reference voltage rail n.

It is arranged above the buck inductance L inductance short-circuit switch, also called short-circuit switch, designed as an antiseries switch of a third and fourth switch Q3, Q4 with common emitter or common collector and with anti-parallel (possibly parasitic) freewheeling diodes D3 and D4. The converter function is described below with reference to FIG. 2, which shows the time course of the current iL through the buck converter inductance L, the output current iout, the voltage uQ2 across the buck converter freewheeling diode D2 or the directly anti-parallel buck converter freewheel switch Q2 (which D2 can have as a parasitic element) and shows the drive signals of switches Q1, Q2, Q3 and Q4. Each of the switching elements Q1-Q4 has a parallel parasitic capacitance Cp1-Cp4 (not shown in FIG. 1), also called output capacitance, which can optionally be increased by an external capacitance and to achieve zero voltage switching or generally a soft one Switching (soft switching) is used, ie takes over the current when a live switch is switched off. By operating the entire circuit accordingly, it must then be ensured that the associated capacitance is discharged before a switch is switched on in order to avoid switch-on losses. The control of the buck converter as described here ensures this operation for all switches Q1-Q4.

[0018] Reg. The terms used below are agreed as follows: The value of the voltage uy assigned to a point in time tx is referred to as uytx for short; Example: uQ2 in t1: uQ2t1. The same goes for electricity. Forward voltages of diodes and power transistors are neglected. Hatching of a control signal means that the associated transistor can advantageously remain switched on in this time interval in order to reduce the complexity of the control, but this is not absolutely necessary for fulfilling the basic circuit function. In general, the control signal shown with solid lines in the figures is selected so that, in the interests of minimizing conduction losses in the conduction interval of a diode, the anti-parallel transistor is always switched through as early as possible, with switching through not immediately after the diode becomes conductive, but with a slight time delay takes place, since a detection of the conduction of the diode, which then triggers the switching on of the switch, would have a certain signal run time or, with fixed-time control, safety times would have to be provided.

Time t0

The current iL increases linearly due to the positive voltage uL = U1-U2 applied to L, starting from iLt0 = 0; Q1 was switched on without voltage at the latest immediately before the zero crossing of the current iL, since the current then flows through the anti-parallel diode D1 of Q1 (Q1 can have D1 as a parasitic element). Transistor Q3 is on, i.e. uQ3 = 0 applies; the positive voltage uL across L thus appears across D4 in the reverse direction (Q4 is switched off), i.e. Cp4 is loaded on U1-U2.

Time t1

Q1 is switched off without voltage, where t1 is selected compared to t0 so that on the one hand the desired power transfer takes place over the entire clock period t0 ... t14 and on the other hand enough current is available in L to ultimately switch on Q2 without voltage at a later point in time t6 to enable); the current iLt1 impressed by L then charges the parasitic capacitance Cp1 of Q1 (or D1), discharges Cp2 of Q2 (or D2) and also Cp4 of Q4 (Q3 is now switched on at the latest and enables this discharge current to flow) in the form of a Vibration, ie uL is decreased starting from U1-U2. The part of iL that is not required for recharging Cp4 continues to appear as output current iout.

Time t2

The voltage uCp4 across the parasitic capacitance Cp4 of Q4 reaches the value zero, so that D4 becomes conductive; the entire current iL now runs through Q3 and D4. The charging of Cp1 and the discharging of Cp2 ends accordingly, the circuit point x remains at the voltage uxn = U2.

Time t3

UD4 = uQ4 = 0, Q4 can be switched on without voltage; the low switch-on resistance of Q4 is parallel to D4 and the conduction losses decrease; furthermore, uL = 0 or uxn = U2.

Time t4

Q3 is switched off without voltage (typically the time interval t3 ... t4 is kept so short that Q4 can be safely switched on without voltage), the current flowing previously through Q3 now flows through Cp3 and charges Cp3 in the reverse direction of D3, which between and a voltage U x> 0 occurs at the circuit point x or the voltage of the circuit point x drops towards the reference voltage rail n; part of iL will then take over the further charging of Cp1 and further discharge of Cp2 (compare time interval t1 ... t2) and a corresponding output current iout occurs again.

Time t5

The voltage uQ2 across the second Sehalter Q2 reaches the value zero, D4 becomes conductive and takes over the current iL; Cp3 is charged on U2, Cp1 on U1, the entire current of the inductance L occurs as output current, iLt5 = iout. iL has a negative slope or is reduced against U2.

Time t6

UD2 = 0, Q2 can be switched on without voltage, so that the conduction losses decrease compared to an exclusive conduction of D2.

Time t7

IL reaches the value zero, at the latest now Q2 must be switched on in order to enable a sign reversal of iL.

Time t8

IL <0, Q2 is switched off without voltage (time t8 is selected so that iLt8 is sufficient to subsequently charge or discharge the parasitic capacitances in such a way that Q1 can ultimately be switched on without voltage in t13), Q4 is now at the latest switched on. The negative current iLt8 now flows through Cp2 and charges the capacitance in the reverse direction of D2 in the form of an oscillation. Accordingly, Cp1 and Cp3 must be discharged, i.e. part of the current iL is conducted via Q4 and Cp3, the remainder occurs as output current iout.

Time t9

Cp3 is completely discharged, D3 becomes conductive, the entire current iL now flows through Q4 and D3, so that uL = 0 and uxn = U n, i.e. the node x remains at the level of the output voltage, the charging of Cp2 and discharging of Q1 ends.

Time t10

UD3 = 0, Q3 can thus be switched on without voltage to reduce the conduction losses. The current iL <0 now circulates through Q4 and Q3, there is no power transfer to U2. The interval between t10 and the following point in time t11 can be referred to as the rest interval. In this interval, a current flows through the inductance short-circuit switch, which can be referred to as auxiliary current.

Time t11

Q4 is switched off without voltage. The length of the interval t10 ... t11 is advantageously chosen so that the length of the entire pulse period, i.e. the time difference t14 – t0 does not fall below a defined value, or the switching frequency fs = 1 / (t14 – t0) of the system remains limited to a defined value. By switching off Q4, iL <0 will now charge Cp4 in the reverse direction of D4, while Q3 can remain conductive or be switched off, since D3 is available for the current flow. With the charging of Cp4, uL> 0, i.e. Switching point x is raised in terms of potential, i.e. Cp2 must be charged and Cp1 discharged, for which a part of iL is used, which also occurs as output current iout. The recharging of the capacities takes place again in the form of an oscillation.

Time t12

The voltage across D1 becomes zero, D1 begins to conduct and clamps the node x against the positive input voltage terminal p. iL thus has a constant positive slope defined by U1-U2.

Time t13

[0031] Q1 can be switched on without voltage and reduces the power losses.

Time t14

Coming from negative values, iL reaches the value zero, this corresponds to the condition initially considered in t0, a pulse period has expired.

In summary, the circuit is controlled by varying the time t1-t0, a cessation of the power delivery; and by varying the time t7-t6, setting the negative auxiliary current value to ensure zero voltage switching.

In a unidirectional power flow, one of the switches of the inductance short-circuit switch is only switched on in order to avoid losses in its anti-parallel diode. The switch can then also remain switched off or be omitted, the control being simplified, but losses in the diode being accepted. In the example in FIG. 1, the fourth switch Q4 and the third diode D3 can be omitted when there is a power flow from the input pn to the output n. When power flows from output n to input pn, the third switch D3 and the fourth diode D4 can be omitted

The control described above can be simplified for the output voltage U2> U1 / 2. This modified control method is briefly described below with reference to FIG. 3.

Time t0a

As above

Time t1a

Q1 is switched off without voltage and Q3, if switched on, is also switched off, since the voltage uL will then assume negative values and accordingly D3 must absorb reverse voltage. Cp1 is charged, Cp2 is discharged, and the junction capacitance Cp4 at a U1-U2 in t1a is discharged, with Cp3 being charged accordingly. If uL = 0 is reached, both Cp3 and Cp4 are mutually charged, the charge-reversal oscillation continues and since U2> U1 / 2 applies, a larger amount of voltage must build up across D3 or Cp3 than was located at D4 or Cp4 in t1a whereby uD4 surely reaches the value zero or D4 becomes conductive and ultimately the full voltage U2 is applied to D3 or Cp3 in t2a.

Time t2a

UCp2 or uQ2 reaches the value zero, D2 becomes conductive.

Time t3a

Q.2 can be switched on without voltage, reducing the conduction losses, iL is reduced to U2; Q4 can also be switched on without voltage, since there is no longer any voltage at D4 (see above).

Time t4a

IL becomes zero, at the latest now Q2 must be switched on in order to enable a current reversal.

Time t5a

Q2 is switched off and at the latest now Q4 must be switched through. The negative current iL now charges Cp2, discharges Cp1 and also Cp3 via Q4.

Time t6a

Cp3 is discharged, uD3 becomes zero, D3 becomes conductive, whereby iL flows through Q4 and D3 and the circuit point x remains at uxn = U2.

Time t7a

Q.3 can be switched on without voltage, reducing the conduction losses.

Time t8a

Switching off Q4, iL <0 now charges Cp4 in the reverse direction from D4 via D3 and Q3, Q3 could be switched off, since D3 is available for conducting current. The switching point x is raised in terms of potential, Cp2 is further charged in the form of an oscillation, Cp1 is further discharged, for which a part of iL is required, which also occurs as an output current iout.

Time t9a

UD1 becomes zero, D1 becomes conductive, the negative current iL is reduced against the input voltage U1. Cp4 is at a voltage U1-U2

Time t10a

[0046] Q1 can be switched on without voltage, reducing the conduction losses.

Time t11a

IL becomes zero, Q1 must now be switched on at the latest in order to enable iL to build up towards positive values.

Claims (10)

1. DC / DC converter in the form of a step-down converter, step-up converter or inverse converter, with a converter inductance (L), having an inductance short-circuit switch which is connected in parallel to the converter inductance (L) and which can be controlled separately according to current directions. 2. DC / DC converter according to claim 1, which is designed for a bidirectional power flow, and wherein the inductance short-circuit switch is implemented by a four-quadrant switch (Q3, Q.4, D3, D4). 3. DC / DC converter according to claim 1, which is designed for a unidirectional power flow, and wherein the inductance short-circuit switch is implemented by a series connection of a diode and a switch. 4. DC / DC converter according to claim 2, which is implemented in the form of a buck converter and has the following elements: - an input terminal (p), an output terminal () and a reference voltage rail (n), - A first switch (Q1) with an anti-parallel first diode (D1), which are connected between the input terminal (p) and a circuit point (x); - A second switch (Q2) with an anti-parallel second diode (D2), which are connected between the node (x) and the reference voltage rail (n); - A converter inductance (L) which is connected between the node (x) and an output terminal; - An inductance short-circuit switch (Q3, Q4, D3, D4) which is connected in parallel to the converter inductance (L) and is designed as an anti-series switch of a third and fourth switch (Q3, Q4) with anti-parallel freewheeling diodes (D3) and (D4). 5. A method for operating a DC / DC converter, in particular in the form of a buck converter, which has the following elements: - an input terminal (p), an output terminal () and a reference voltage rail (n), - A first switch (Q1) with an anti-parallel first diode (Dl) which are connected between the input terminal (p) and a circuit point (x); - A second switch (Q2) with an anti-parallel second diode (D2), which are connected between the node (x) and the reference voltage rail (n); - A converter inductance (L) which is connected between the node (x) and an output terminal; - An inductance short-circuit switch (Q3, Q4, D3, D4) which is connected in parallel to the converter inductance (L) and is designed as an anti-series switch of a third and fourth switch (Q3, Q4) with anti-parallel freewheeling diodes (D3) and (D4); wherein, during operation of the DC / DC converter, a current, hereinafter referred to as converter current iL, flows through the converter inductance (L), and wherein for the implementation of soft switching processes - Starting from a starting time t0, at which the converter current is zero, and the first switch (Q1) is switched on or is switched on without voltage, the third switch (Q3) is switched on or off and the second switch (Q2) and the fourth switch (Q4) are switched off follow the steps outlined below in this order: - At a time t1, de-energized switching off of the first switch (Q1); - At a point in time t3, the fourth switch (Q4) is switched on without voltage; - at a time t4, de-energized switching off of the third switch (Q3); - at a point in time t6, switching on the second switch (Q2) without voltage; - at a time t8, de-energized switching off of the second switch (Q2); - At a point in time t10, the third switch (Q3) is switched on without voltage; - at a time t11, de-energized switching off of the fourth switch (Q4); - at a point in time t13, switching on the first switch (Q1) without voltage; and thus the state corresponding to the starting time t0 is reached again. 6. The method according to claim 5, with the further steps - at the earliest at time t11, switching off the third switch (Q3); and - At the latest at time t1 of a subsequent period, the third switch (Q3) is switched on without voltage. 7. The method according to claim 5 or 6, with the further steps - at the earliest at time t4, switching off the fourth switch (Q4); and - At the latest at time t8, the fourth switch (Q4) is switched on without voltage. 8. A method for operating a DC / DC converter, in particular in the form of a buck converter, which has the following elements: - an input terminal (p), an output terminal () and a reference voltage rail (n), - A first switch (Q1) with an anti-parallel first diode (Dl) which are connected between the input terminal (p) and a circuit point (x); - A second switch (Q2) with an anti-parallel second diode (D2), which are connected between the node (x) and the reference voltage rail (n); - A converter inductance (L) which is connected between the node (x) and an output terminal; - An inductance short-circuit switch (Q3, Q4, D3, D4) which is connected in parallel to the converter inductance (L) and is designed as an anti-series switch of a third and fourth switch (Q3, Q4) with anti-parallel freewheeling diodes (D3) and (D4); wherein during operation of the DC / DC converter, a current, hereinafter referred to as converter current iL, flows through the converter inductance (L), and whereby for the realization of soft switching processes - Starting from a starting time t0a, at which the converter current is zero, and the first switch (Q1) is switched on or is switched on without voltage, the third switch (Q3) is switched on or off and the second switch (Q2) and: the fourth Switches (Q4) are switched off follow the steps outlined below in this order: - at a point in time t1a, de-energizing the first switch (Q1), and at the latest at this point in time t1a de-energizing the third switch (Q3), if it is switched on; - At the earliest at a point in time t3a and at the latest at a point in time t4a, the second switch (Q2) is switched on without voltage; - at a point in time t5a, de-energized switching off of the second switch (Q2) and at the latest at this point in time t5a de-energized switching on of the fourth switch (Q4), if it is not yet switched on; - at a point in time t7a, switching on the third switch (Q3) without voltage; - at a time t8a, de-energized switching off of the fourth switch (Q4); - at the earliest at a point in time t10a and at the latest at a point in time t11a, switching on the first switch (Q1) without voltage; - the state corresponding to the starting time t0 being reached again at time t11a. 9. The method according to claim 8, with the further steps - at the earliest at time t8a, switching off the third switch (Q3); and - At the latest at time t1a of a following period, the third switch (Q3) is switched on without voltage. 10. The method according to claim 8 or 9, with the further step - At the earliest at time t3a, the fourth switch (Q.4) is switched on without voltage.